Finally got Marvell 50XX SATA to the point where it, too, complains
about "ATA: abnormal status 0x80 on port ...11C"... which is progress :)
The following updates are now available in the 'marv' branch of
rsync://rsync.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev.git
drivers/scsi/Kconfig | 2
drivers/scsi/sata_mv.c | 900 ++++++++++++++++++++++++++++++++++++++++---------
2 files changed, 749 insertions(+), 153 deletions(-)
Jeff Garzik:
[libata sata_mv] minor fixes
[libata sata_mv] trim trailing whitespace
[libata sata_mv] note driver is "HIGHLY EXPERIMENTAL" in Kconfig
[libata sata_mv] implement a bunch of errata workarounds
[libata sata_mv] move code around
[libata sata_mv] mv_hw_ops for hardware families; new errata
[libata sata_mv] hardware initialization work
[libata sata_mv] move code around
[libata sata_mv] call phy fixups during init, as well as phy reset
[libata sata_mv] fix tons of 50XX bugs
diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index 84c42c4..20dd85a 100644
--- a/drivers/scsi/Kconfig
+++ b/drivers/scsi/Kconfig
@@ -497,7 +497,7 @@ config SCSI_ATA_PIIX
If unsure, say N.
config SCSI_SATA_MV
- tristate "Marvell SATA support"
+ tristate "Marvell SATA support (HIGHLY EXPERIMENTAL)"
depends on SCSI_SATA && PCI && EXPERIMENTAL
help
This option enables support for the Marvell Serial ATA family.
diff --git a/drivers/scsi/sata_mv.c b/drivers/scsi/sata_mv.c
index 257c128..722ab53 100644
--- a/drivers/scsi/sata_mv.c
+++ b/drivers/scsi/sata_mv.c
@@ -1,7 +1,7 @@
/*
* sata_mv.c - Marvell SATA support
*
- * Copyright 2005: EMC Corporation, all rights reserved.
+ * Copyright 2005: EMC Corporation, all rights reserved.
*
* Please ALWAYS copy [email protected] on emails.
*
@@ -50,6 +50,9 @@ enum {
MV_PCI_REG_BASE = 0,
MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
MV_SATAHC0_REG_BASE = 0x20000,
+ MV_FLASH_CTL = 0x1046c,
+ MV_GPIO_PORT_CTL = 0x104f0,
+ MV_RESET_CFG = 0x180d8,
MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
@@ -72,11 +75,6 @@ enum {
MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
- /* Our DMA boundary is determined by an ePRD being unable to handle
- * anything larger than 64KB
- */
- MV_DMA_BOUNDARY = 0xffffU,
-
MV_PORTS_PER_HC = 4,
/* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
MV_PORT_HC_SHIFT = 2,
@@ -86,16 +84,9 @@ enum {
/* Host Flags */
MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
- MV_FLAG_GLBL_SFT_RST = (1 << 28), /* Global Soft Reset support */
MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO),
- MV_6XXX_FLAGS = (MV_FLAG_IRQ_COALESCE |
- MV_FLAG_GLBL_SFT_RST),
-
- chip_504x = 0,
- chip_508x = 1,
- chip_604x = 2,
- chip_608x = 3,
+ MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
CRQB_FLAG_READ = (1 << 0),
CRQB_TAG_SHIFT = 1,
@@ -116,8 +107,19 @@ enum {
PCI_MASTER_EMPTY = (1 << 3),
GLOB_SFT_RST = (1 << 4),
- PCI_IRQ_CAUSE_OFS = 0x1d58,
- PCI_IRQ_MASK_OFS = 0x1d5c,
+ MV_PCI_MODE = 0xd00,
+ MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
+ MV_PCI_DISC_TIMER = 0xd04,
+ MV_PCI_MSI_TRIGGER = 0xc38,
+ MV_PCI_SERR_MASK = 0xc28,
+ MV_PCI_XBAR_TMOUT = 0x1d04,
+ MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
+ MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
+ MV_PCI_ERR_ATTRIBUTE = 0x1d48,
+ MV_PCI_ERR_COMMAND = 0x1d50,
+
+ PCI_IRQ_CAUSE_OFS = 0x1d58,
+ PCI_IRQ_MASK_OFS = 0x1d5c,
PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
@@ -134,7 +136,7 @@ enum {
SELF_INT = (1 << 23),
TWSI_INT = (1 << 24),
HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
- HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
+ HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
HC_MAIN_RSVD),
@@ -153,6 +155,15 @@ enum {
/* SATA registers */
SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
SATA_ACTIVE_OFS = 0x350,
+ PHY_MODE3 = 0x310,
+ PHY_MODE4 = 0x314,
+ PHY_MODE2 = 0x330,
+ MV5_PHY_MODE = 0x74,
+ MV5_LT_MODE = 0x30,
+ MV5_PHY_CTL = 0x0C,
+ SATA_INTERFACE_CTL = 0x050,
+
+ MV_M2_PREAMP_MASK = 0x7e0,
/* Port registers */
EDMA_CFG_OFS = 0,
@@ -182,17 +193,16 @@ enum {
EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
EDMA_ERR_TRANS_PROTO = (1 << 31),
- EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
+ EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
- EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
+ EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
EDMA_ERR_LNK_DATA_RX |
- EDMA_ERR_LNK_DATA_TX |
+ EDMA_ERR_LNK_DATA_TX |
EDMA_ERR_TRANS_PROTO),
EDMA_REQ_Q_BASE_HI_OFS = 0x10,
EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
- EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
EDMA_REQ_Q_PTR_SHIFT = 5,
@@ -200,7 +210,6 @@ enum {
EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
EDMA_RSP_Q_IN_PTR_OFS = 0x20,
EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
- EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
EDMA_RSP_Q_PTR_SHIFT = 3,
EDMA_CMD_OFS = 0x28,
@@ -208,14 +217,44 @@ enum {
EDMA_DS = (1 << 1),
ATA_RST = (1 << 2),
+ EDMA_IORDY_TMOUT = 0x34,
+ EDMA_ARB_CFG = 0x38,
+
/* Host private flags (hp_flags) */
MV_HP_FLAG_MSI = (1 << 0),
+ MV_HP_ERRATA_50XXB0 = (1 << 1),
+ MV_HP_ERRATA_50XXB2 = (1 << 2),
+ MV_HP_ERRATA_60X1B2 = (1 << 3),
+ MV_HP_ERRATA_60X1C0 = (1 << 4),
+ MV_HP_50XX = (1 << 5),
/* Port private flags (pp_flags) */
MV_PP_FLAG_EDMA_EN = (1 << 0),
MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
};
+#define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
+#define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
+
+enum {
+ /* Our DMA boundary is determined by an ePRD being unable to handle
+ * anything larger than 64KB
+ */
+ MV_DMA_BOUNDARY = 0xffffU,
+
+ EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
+
+ EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
+};
+
+enum chip_type {
+ chip_504x,
+ chip_508x,
+ chip_5080,
+ chip_604x,
+ chip_608x,
+};
+
/* Command ReQuest Block: 32B */
struct mv_crqb {
u32 sg_addr;
@@ -252,13 +291,35 @@ struct mv_port_priv {
u32 pp_flags;
};
+struct mv_port_signal {
+ u32 amps;
+ u32 pre;
+};
+
+struct mv_host_priv;
+struct mv_hw_ops {
+ void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
+ unsigned int port);
+ void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
+ void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
+ void __iomem *mmio);
+ int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
+ unsigned int n_hc);
+ void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
+ void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
+};
+
struct mv_host_priv {
u32 hp_flags;
+ struct mv_port_signal signal[8];
+ const struct mv_hw_ops *ops;
};
static void mv_irq_clear(struct ata_port *ap);
static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
+static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
+static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
static void mv_phy_reset(struct ata_port *ap);
static void mv_host_stop(struct ata_host_set *host_set);
static int mv_port_start(struct ata_port *ap);
@@ -270,6 +331,29 @@ static irqreturn_t mv_interrupt(int irq,
static void mv_eng_timeout(struct ata_port *ap);
static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
+static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
+ unsigned int port);
+static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
+static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
+ void __iomem *mmio);
+static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
+ unsigned int n_hc);
+static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
+static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
+
+static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
+ unsigned int port);
+static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
+static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
+ void __iomem *mmio);
+static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
+ unsigned int n_hc);
+static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
+static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
+static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
+ unsigned int port_no);
+static void mv_stop_and_reset(struct ata_port *ap);
+
static struct scsi_host_template mv_sht = {
.module = THIS_MODULE,
.name = DRV_NAME,
@@ -290,7 +374,34 @@ static struct scsi_host_template mv_sht
.ordered_flush = 1,
};
-static const struct ata_port_operations mv_ops = {
+static const struct ata_port_operations mv5_ops = {
+ .port_disable = ata_port_disable,
+
+ .tf_load = ata_tf_load,
+ .tf_read = ata_tf_read,
+ .check_status = ata_check_status,
+ .exec_command = ata_exec_command,
+ .dev_select = ata_std_dev_select,
+
+ .phy_reset = mv_phy_reset,
+
+ .qc_prep = mv_qc_prep,
+ .qc_issue = mv_qc_issue,
+
+ .eng_timeout = mv_eng_timeout,
+
+ .irq_handler = mv_interrupt,
+ .irq_clear = mv_irq_clear,
+
+ .scr_read = mv5_scr_read,
+ .scr_write = mv5_scr_write,
+
+ .port_start = mv_port_start,
+ .port_stop = mv_port_stop,
+ .host_stop = mv_host_stop,
+};
+
+static const struct ata_port_operations mv6_ops = {
.port_disable = ata_port_disable,
.tf_load = ata_tf_load,
@@ -322,37 +433,44 @@ static struct ata_port_info mv_port_info
.sht = &mv_sht,
.host_flags = MV_COMMON_FLAGS,
.pio_mask = 0x1f, /* pio0-4 */
- .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */
- .port_ops = &mv_ops,
+ .udma_mask = 0x7f, /* udma0-6 */
+ .port_ops = &mv5_ops,
},
{ /* chip_508x */
.sht = &mv_sht,
.host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
.pio_mask = 0x1f, /* pio0-4 */
- .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */
- .port_ops = &mv_ops,
+ .udma_mask = 0x7f, /* udma0-6 */
+ .port_ops = &mv5_ops,
+ },
+ { /* chip_5080 */
+ .sht = &mv_sht,
+ .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
+ .pio_mask = 0x1f, /* pio0-4 */
+ .udma_mask = 0x7f, /* udma0-6 */
+ .port_ops = &mv5_ops,
},
{ /* chip_604x */
.sht = &mv_sht,
.host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
.pio_mask = 0x1f, /* pio0-4 */
.udma_mask = 0x7f, /* udma0-6 */
- .port_ops = &mv_ops,
+ .port_ops = &mv6_ops,
},
{ /* chip_608x */
.sht = &mv_sht,
- .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
+ .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
MV_FLAG_DUAL_HC),
.pio_mask = 0x1f, /* pio0-4 */
.udma_mask = 0x7f, /* udma0-6 */
- .port_ops = &mv_ops,
+ .port_ops = &mv6_ops,
},
};
static const struct pci_device_id mv_pci_tbl[] = {
{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
- {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_508x},
+ {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080},
{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
{PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
@@ -371,6 +489,24 @@ static struct pci_driver mv_pci_driver =
.remove = ata_pci_remove_one,
};
+static const struct mv_hw_ops mv5xxx_ops = {
+ .phy_errata = mv5_phy_errata,
+ .enable_leds = mv5_enable_leds,
+ .read_preamp = mv5_read_preamp,
+ .reset_hc = mv5_reset_hc,
+ .reset_flash = mv5_reset_flash,
+ .reset_bus = mv5_reset_bus,
+};
+
+static const struct mv_hw_ops mv6xxx_ops = {
+ .phy_errata = mv6_phy_errata,
+ .enable_leds = mv6_enable_leds,
+ .read_preamp = mv6_read_preamp,
+ .reset_hc = mv6_reset_hc,
+ .reset_flash = mv6_reset_flash,
+ .reset_bus = mv_reset_pci_bus,
+};
+
/*
* Functions
*/
@@ -386,11 +522,27 @@ static inline void __iomem *mv_hc_base(v
return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
}
+static inline unsigned int mv_hc_from_port(unsigned int port)
+{
+ return port >> MV_PORT_HC_SHIFT;
+}
+
+static inline unsigned int mv_hardport_from_port(unsigned int port)
+{
+ return port & MV_PORT_MASK;
+}
+
+static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
+ unsigned int port)
+{
+ return mv_hc_base(base, mv_hc_from_port(port));
+}
+
static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
{
- return (mv_hc_base(base, port >> MV_PORT_HC_SHIFT) +
- MV_SATAHC_ARBTR_REG_SZ +
- ((port & MV_PORT_MASK) * MV_PORT_REG_SZ));
+ return mv_hc_base_from_port(base, port) +
+ MV_SATAHC_ARBTR_REG_SZ +
+ (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
}
static inline void __iomem *mv_ap_base(struct ata_port *ap)
@@ -398,9 +550,9 @@ static inline void __iomem *mv_ap_base(s
return mv_port_base(ap->host_set->mmio_base, ap->port_no);
}
-static inline int mv_get_hc_count(unsigned long hp_flags)
+static inline int mv_get_hc_count(unsigned long host_flags)
{
- return ((hp_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
+ return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
}
static void mv_irq_clear(struct ata_port *ap)
@@ -452,7 +604,7 @@ static void mv_stop_dma(struct ata_port
} else {
assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
}
-
+
/* now properly wait for the eDMA to stop */
for (i = 1000; i > 0; i--) {
reg = readl(port_mmio + EDMA_CMD_OFS);
@@ -503,7 +655,7 @@ static void mv_dump_all_regs(void __iome
struct pci_dev *pdev)
{
#ifdef ATA_DEBUG
- void __iomem *hc_base = mv_hc_base(mmio_base,
+ void __iomem *hc_base = mv_hc_base(mmio_base,
port >> MV_PORT_HC_SHIFT);
void __iomem *port_base;
int start_port, num_ports, p, start_hc, num_hcs, hc;
@@ -517,7 +669,7 @@ static void mv_dump_all_regs(void __iome
start_port = port;
num_ports = num_hcs = 1;
}
- DPRINTK("All registers for port(s) %u-%u:\n", start_port,
+ DPRINTK("All registers for port(s) %u-%u:\n", start_port,
num_ports > 1 ? num_ports - 1 : start_port);
if (NULL != pdev) {
@@ -585,70 +737,6 @@ static void mv_scr_write(struct ata_port
}
/**
- * mv_global_soft_reset - Perform the 6xxx global soft reset
- * @mmio_base: base address of the HBA
- *
- * This routine only applies to 6xxx parts.
- *
- * LOCKING:
- * Inherited from caller.
- */
-static int mv_global_soft_reset(void __iomem *mmio_base)
-{
- void __iomem *reg = mmio_base + PCI_MAIN_CMD_STS_OFS;
- int i, rc = 0;
- u32 t;
-
- /* Following procedure defined in PCI "main command and status
- * register" table.
- */
- t = readl(reg);
- writel(t | STOP_PCI_MASTER, reg);
-
- for (i = 0; i < 1000; i++) {
- udelay(1);
- t = readl(reg);
- if (PCI_MASTER_EMPTY & t) {
- break;
- }
- }
- if (!(PCI_MASTER_EMPTY & t)) {
- printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
- rc = 1;
- goto done;
- }
-
- /* set reset */
- i = 5;
- do {
- writel(t | GLOB_SFT_RST, reg);
- t = readl(reg);
- udelay(1);
- } while (!(GLOB_SFT_RST & t) && (i-- > 0));
-
- if (!(GLOB_SFT_RST & t)) {
- printk(KERN_ERR DRV_NAME ": can't set global reset\n");
- rc = 1;
- goto done;
- }
-
- /* clear reset and *reenable the PCI master* (not mentioned in spec) */
- i = 5;
- do {
- writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
- t = readl(reg);
- udelay(1);
- } while ((GLOB_SFT_RST & t) && (i-- > 0));
-
- if (GLOB_SFT_RST & t) {
- printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
- rc = 1;
- }
-done:
- return rc;
-}
-
-/**
* mv_host_stop - Host specific cleanup/stop routine.
* @host_set: host data structure
*
@@ -701,7 +789,7 @@ static int mv_port_start(struct ata_port
goto err_out;
memset(pp, 0, sizeof(*pp));
- mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
+ mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
GFP_KERNEL);
if (!mem)
goto err_out_pp;
@@ -711,7 +799,7 @@ static int mv_port_start(struct ata_port
if (rc)
goto err_out_priv;
- /* First item in chunk of DMA memory:
+ /* First item in chunk of DMA memory:
* 32-slot command request table (CRQB), 32 bytes each in size
*/
pp->crqb = mem;
@@ -719,7 +807,7 @@ static int mv_port_start(struct ata_port
mem += MV_CRQB_Q_SZ;
mem_dma += MV_CRQB_Q_SZ;
- /* Second item:
+ /* Second item:
* 32-slot command response table (CRPB), 8 bytes each in size
*/
pp->crpb = mem;
@@ -733,18 +821,18 @@ static int mv_port_start(struct ata_port
pp->sg_tbl = mem;
pp->sg_tbl_dma = mem_dma;
- writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
+ writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
- writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
+ writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
- writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
+ writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
pp->req_producer = pp->rsp_consumer = 0;
@@ -859,7 +947,7 @@ static void mv_qc_prep(struct ata_queued
}
/* the req producer index should be the same as we remember it */
- assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
+ assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
pp->req_producer);
@@ -871,9 +959,9 @@ static void mv_qc_prep(struct ata_queued
assert(MV_MAX_Q_DEPTH > qc->tag);
flags |= qc->tag << CRQB_TAG_SHIFT;
- pp->crqb[pp->req_producer].sg_addr =
+ pp->crqb[pp->req_producer].sg_addr =
cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
- pp->crqb[pp->req_producer].sg_addr_hi =
+ pp->crqb[pp->req_producer].sg_addr_hi =
cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
@@ -896,7 +984,7 @@ static void mv_qc_prep(struct ata_queued
#ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
case ATA_CMD_FPDMA_READ:
case ATA_CMD_FPDMA_WRITE:
- mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
+ mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
break;
#endif /* FIXME: remove this line when NCQ added */
@@ -962,7 +1050,7 @@ static int mv_qc_issue(struct ata_queued
pp->req_producer);
/* until we do queuing, the queue should be empty at this point */
assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
- ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
+ ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
mv_inc_q_index(&pp->req_producer); /* now incr producer index */
@@ -999,15 +1087,15 @@ static u8 mv_get_crpb_status(struct ata_
out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
/* the response consumer index should be the same as we remember it */
- assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
+ assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
pp->rsp_consumer);
/* increment our consumer index... */
pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
-
+
/* and, until we do NCQ, there should only be 1 CRPB waiting */
- assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
- EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
+ assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
+ EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
pp->rsp_consumer);
/* write out our inc'd consumer index so EDMA knows we're caught up */
@@ -1055,7 +1143,7 @@ static void mv_err_intr(struct ata_port
/* check for fatal here and recover if needed */
if (EDMA_ERR_FATAL & edma_err_cause) {
- mv_phy_reset(ap);
+ mv_stop_and_reset(ap);
}
}
@@ -1131,7 +1219,7 @@ static void mv_host_intr(struct ata_host
err_mask |= AC_ERR_OTHER;
handled++;
}
-
+
if (handled && ap) {
qc = ata_qc_from_tag(ap, ap->active_tag);
if (NULL != qc) {
@@ -1146,7 +1234,7 @@ static void mv_host_intr(struct ata_host
}
/**
- * mv_interrupt -
+ * mv_interrupt -
* @irq: unused
* @dev_instance: private data; in this case the host structure
* @regs: unused
@@ -1156,7 +1244,7 @@ static void mv_host_intr(struct ata_host
* routine to handle. Also check for PCI errors which are only
* reported here.
*
- * LOCKING:
+ * LOCKING:
* This routine holds the host_set lock while processing pending
* interrupts.
*/
@@ -1202,6 +1290,412 @@ static irqreturn_t mv_interrupt(int irq,
return IRQ_RETVAL(handled);
}
+static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
+{
+ void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
+ unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
+
+ return hc_mmio + ofs;
+}
+
+static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
+{
+ unsigned int ofs;
+
+ switch (sc_reg_in) {
+ case SCR_STATUS:
+ case SCR_ERROR:
+ case SCR_CONTROL:
+ ofs = sc_reg_in * sizeof(u32);
+ break;
+ default:
+ ofs = 0xffffffffU;
+ break;
+ }
+ return ofs;
+}
+
+static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
+{
+ void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
+ unsigned int ofs = mv5_scr_offset(sc_reg_in);
+
+ if (ofs != 0xffffffffU)
+ return readl(mmio + ofs);
+ else
+ return (u32) ofs;
+}
+
+static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
+{
+ void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
+ unsigned int ofs = mv5_scr_offset(sc_reg_in);
+
+ if (ofs != 0xffffffffU)
+ writelfl(val, mmio + ofs);
+}
+
+static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
+{
+ u8 rev_id;
+ int early_5080;
+
+ pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
+
+ early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
+
+ if (!early_5080) {
+ u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
+ tmp |= (1 << 0);
+ writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
+ }
+
+ mv_reset_pci_bus(pdev, mmio);
+}
+
+static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
+{
+ writel(0x0fcfffff, mmio + MV_FLASH_CTL);
+}
+
+static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
+ void __iomem *mmio)
+{
+ void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
+ u32 tmp;
+
+ tmp = readl(phy_mmio + MV5_PHY_MODE);
+
+ hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
+ hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
+}
+
+static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
+{
+ u32 tmp;
+
+ writel(0, mmio + MV_GPIO_PORT_CTL);
+
+ /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
+
+ tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
+ tmp |= ~(1 << 0);
+ writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
+}
+
+static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
+ unsigned int port)
+{
+ void __iomem *phy_mmio = mv5_phy_base(mmio, port);
+ const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
+ u32 tmp;
+ int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
+
+ if (fix_apm_sq) {
+ tmp = readl(phy_mmio + MV5_LT_MODE);
+ tmp |= (1 << 19);
+ writel(tmp, phy_mmio + MV5_LT_MODE);
+
+ tmp = readl(phy_mmio + MV5_PHY_CTL);
+ tmp &= ~0x3;
+ tmp |= 0x1;
+ writel(tmp, phy_mmio + MV5_PHY_CTL);
+ }
+
+ tmp = readl(phy_mmio + MV5_PHY_MODE);
+ tmp &= ~mask;
+ tmp |= hpriv->signal[port].pre;
+ tmp |= hpriv->signal[port].amps;
+ writel(tmp, phy_mmio + MV5_PHY_MODE);
+}
+
+
+#undef ZERO
+#define ZERO(reg) writel(0, port_mmio + (reg))
+static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
+ unsigned int port)
+{
+ void __iomem *port_mmio = mv_port_base(mmio, port);
+
+ writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
+
+ mv_channel_reset(hpriv, mmio, port);
+
+ ZERO(0x028); /* command */
+ writel(0x11f, port_mmio + EDMA_CFG_OFS);
+ ZERO(0x004); /* timer */
+ ZERO(0x008); /* irq err cause */
+ ZERO(0x00c); /* irq err mask */
+ ZERO(0x010); /* rq bah */
+ ZERO(0x014); /* rq inp */
+ ZERO(0x018); /* rq outp */
+ ZERO(0x01c); /* respq bah */
+ ZERO(0x024); /* respq outp */
+ ZERO(0x020); /* respq inp */
+ ZERO(0x02c); /* test control */
+ writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
+}
+#undef ZERO
+
+#define ZERO(reg) writel(0, hc_mmio + (reg))
+static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
+ unsigned int hc)
+{
+ void __iomem *hc_mmio = mv_hc_base(mmio, hc);
+ u32 tmp;
+
+ ZERO(0x00c);
+ ZERO(0x010);
+ ZERO(0x014);
+ ZERO(0x018);
+
+ tmp = readl(hc_mmio + 0x20);
+ tmp &= 0x1c1c1c1c;
+ tmp |= 0x03030303;
+ writel(tmp, hc_mmio + 0x20);
+}
+#undef ZERO
+
+static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
+ unsigned int n_hc)
+{
+ unsigned int hc, port;
+
+ for (hc = 0; hc < n_hc; hc++) {
+ for (port = 0; port < MV_PORTS_PER_HC; port++)
+ mv5_reset_hc_port(hpriv, mmio,
+ (hc * MV_PORTS_PER_HC) + port);
+
+ mv5_reset_one_hc(hpriv, mmio, hc);
+ }
+
+ return 0;
+}
+
+#undef ZERO
+#define ZERO(reg) writel(0, mmio + (reg))
+static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
+{
+ u32 tmp;
+
+ tmp = readl(mmio + MV_PCI_MODE);
+ tmp &= 0xff00ffff;
+ writel(tmp, mmio + MV_PCI_MODE);
+
+ ZERO(MV_PCI_DISC_TIMER);
+ ZERO(MV_PCI_MSI_TRIGGER);
+ writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
+ ZERO(HC_MAIN_IRQ_MASK_OFS);
+ ZERO(MV_PCI_SERR_MASK);
+ ZERO(PCI_IRQ_CAUSE_OFS);
+ ZERO(PCI_IRQ_MASK_OFS);
+ ZERO(MV_PCI_ERR_LOW_ADDRESS);
+ ZERO(MV_PCI_ERR_HIGH_ADDRESS);
+ ZERO(MV_PCI_ERR_ATTRIBUTE);
+ ZERO(MV_PCI_ERR_COMMAND);
+}
+#undef ZERO
+
+static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
+{
+ u32 tmp;
+
+ mv5_reset_flash(hpriv, mmio);
+
+ tmp = readl(mmio + MV_GPIO_PORT_CTL);
+ tmp &= 0x3;
+ tmp |= (1 << 5) | (1 << 6);
+ writel(tmp, mmio + MV_GPIO_PORT_CTL);
+}
+
+/**
+ * mv6_reset_hc - Perform the 6xxx global soft reset
+ * @mmio: base address of the HBA
+ *
+ * This routine only applies to 6xxx parts.
+ *
+ * LOCKING:
+ * Inherited from caller.
+ */
+static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
+ unsigned int n_hc)
+{
+ void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
+ int i, rc = 0;
+ u32 t;
+
+ /* Following procedure defined in PCI "main command and status
+ * register" table.
+ */
+ t = readl(reg);
+ writel(t | STOP_PCI_MASTER, reg);
+
+ for (i = 0; i < 1000; i++) {
+ udelay(1);
+ t = readl(reg);
+ if (PCI_MASTER_EMPTY & t) {
+ break;
+ }
+ }
+ if (!(PCI_MASTER_EMPTY & t)) {
+ printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
+ rc = 1;
+ goto done;
+ }
+
+ /* set reset */
+ i = 5;
+ do {
+ writel(t | GLOB_SFT_RST, reg);
+ t = readl(reg);
+ udelay(1);
+ } while (!(GLOB_SFT_RST & t) && (i-- > 0));
+
+ if (!(GLOB_SFT_RST & t)) {
+ printk(KERN_ERR DRV_NAME ": can't set global reset\n");
+ rc = 1;
+ goto done;
+ }
+
+ /* clear reset and *reenable the PCI master* (not mentioned in spec) */
+ i = 5;
+ do {
+ writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
+ t = readl(reg);
+ udelay(1);
+ } while ((GLOB_SFT_RST & t) && (i-- > 0));
+
+ if (GLOB_SFT_RST & t) {
+ printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
+ rc = 1;
+ }
+done:
+ return rc;
+}
+
+static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
+ void __iomem *mmio)
+{
+ void __iomem *port_mmio;
+ u32 tmp;
+
+ tmp = readl(mmio + MV_RESET_CFG);
+ if ((tmp & (1 << 0)) == 0) {
+ hpriv->signal[idx].amps = 0x7 << 8;
+ hpriv->signal[idx].pre = 0x1 << 5;
+ return;
+ }
+
+ port_mmio = mv_port_base(mmio, idx);
+ tmp = readl(port_mmio + PHY_MODE2);
+
+ hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
+ hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
+}
+
+static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
+{
+ writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
+}
+
+static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
+ unsigned int port)
+{
+ void __iomem *port_mmio = mv_port_base(mmio, port);
+
+ u32 hp_flags = hpriv->hp_flags;
+ int fix_phy_mode2 =
+ hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
+ int fix_phy_mode4 =
+ hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
+ u32 m2, tmp;
+
+ if (fix_phy_mode2) {
+ m2 = readl(port_mmio + PHY_MODE2);
+ m2 &= ~(1 << 16);
+ m2 |= (1 << 31);
+ writel(m2, port_mmio + PHY_MODE2);
+
+ udelay(200);
+
+ m2 = readl(port_mmio + PHY_MODE2);
+ m2 &= ~((1 << 16) | (1 << 31));
+ writel(m2, port_mmio + PHY_MODE2);
+
+ udelay(200);
+ }
+
+ /* who knows what this magic does */
+ tmp = readl(port_mmio + PHY_MODE3);
+ tmp &= ~0x7F800000;
+ tmp |= 0x2A800000;
+ writel(tmp, port_mmio + PHY_MODE3);
+
+ if (fix_phy_mode4) {
+ u32 m4;
+
+ m4 = readl(port_mmio + PHY_MODE4);
+
+ if (hp_flags & MV_HP_ERRATA_60X1B2)
+ tmp = readl(port_mmio + 0x310);
+
+ m4 = (m4 & ~(1 << 1)) | (1 << 0);
+
+ writel(m4, port_mmio + PHY_MODE4);
+
+ if (hp_flags & MV_HP_ERRATA_60X1B2)
+ writel(tmp, port_mmio + 0x310);
+ }
+
+ /* Revert values of pre-emphasis and signal amps to the saved ones */
+ m2 = readl(port_mmio + PHY_MODE2);
+
+ m2 &= ~MV_M2_PREAMP_MASK;
+ m2 |= hpriv->signal[port].amps;
+ m2 |= hpriv->signal[port].pre;
+ m2 &= ~(1 << 16);
+
+ writel(m2, port_mmio + PHY_MODE2);
+}
+
+static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
+ unsigned int port_no)
+{
+ void __iomem *port_mmio = mv_port_base(mmio, port_no);
+
+ writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
+
+ if (IS_60XX(hpriv)) {
+ u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
+ ifctl |= (1 << 12) | (1 << 7);
+ writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
+ }
+
+ udelay(25); /* allow reset propagation */
+
+ /* Spec never mentions clearing the bit. Marvell's driver does
+ * clear the bit, however.
+ */
+ writelfl(0, port_mmio + EDMA_CMD_OFS);
+
+ hpriv->ops->phy_errata(hpriv, mmio, port_no);
+
+ if (IS_50XX(hpriv))
+ mdelay(1);
+}
+
+static void mv_stop_and_reset(struct ata_port *ap)
+{
+ struct mv_host_priv *hpriv = ap->host_set->private_data;
+ void __iomem *mmio = ap->host_set->mmio_base;
+
+ mv_stop_dma(ap);
+
+ mv_channel_reset(hpriv, mmio, ap->port_no);
+
+ mv_phy_reset(ap);
+}
+
/**
* mv_phy_reset - Perform eDMA reset followed by COMRESET
* @ap: ATA channel to manipulate
@@ -1215,6 +1709,7 @@ static irqreturn_t mv_interrupt(int irq,
*/
static void mv_phy_reset(struct ata_port *ap)
{
+ struct mv_port_priv *pp = ap->private_data;
void __iomem *port_mmio = mv_ap_base(ap);
struct ata_taskfile tf;
struct ata_device *dev = &ap->device[0];
@@ -1222,17 +1717,7 @@ static void mv_phy_reset(struct ata_port
VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
- mv_stop_dma(ap);
-
- writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
- udelay(25); /* allow reset propagation */
-
- /* Spec never mentions clearing the bit. Marvell's driver does
- * clear the bit, however.
- */
- writelfl(0, port_mmio + EDMA_CMD_OFS);
-
- VPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
+ DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
"SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
@@ -1247,7 +1732,9 @@ static void mv_phy_reset(struct ata_port
break;
} while (time_before(jiffies, timeout));
- VPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
+ mv_scr_write(ap, SCR_ERROR, mv_scr_read(ap, SCR_ERROR));
+
+ DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
"SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
@@ -1271,6 +1758,11 @@ static void mv_phy_reset(struct ata_port
VPRINTK("Port disabled post-sig: No device present.\n");
ata_port_disable(ap);
}
+
+ writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
+
+ pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
+
VPRINTK("EXIT\n");
}
@@ -1291,16 +1783,16 @@ static void mv_eng_timeout(struct ata_po
printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
DPRINTK("All regs @ start of eng_timeout\n");
- mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
+ mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
to_pci_dev(ap->host_set->dev));
qc = ata_qc_from_tag(ap, ap->active_tag);
printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
- ap->host_set->mmio_base, ap, qc, qc->scsicmd,
+ ap->host_set->mmio_base, ap, qc, qc->scsicmd,
&qc->scsicmd->cmnd);
mv_err_intr(ap);
- mv_phy_reset(ap);
+ mv_stop_and_reset(ap);
if (!qc) {
printk(KERN_ERR "ata%u: BUG: timeout without command\n",
@@ -1336,17 +1828,17 @@ static void mv_port_init(struct ata_iopo
unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
unsigned serr_ofs;
- /* PIO related setup
+ /* PIO related setup
*/
port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
- port->error_addr =
+ port->error_addr =
port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
- port->status_addr =
+ port->status_addr =
port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
/* special case: control/altstatus doesn't have ATA_REG_ address */
port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
@@ -1362,14 +1854,92 @@ static void mv_port_init(struct ata_iopo
/* unmask all EDMA error interrupts */
writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
- VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
+ VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
readl(port_mmio + EDMA_CFG_OFS),
readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
}
+static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
+ unsigned int board_idx)
+{
+ u8 rev_id;
+ u32 hp_flags = hpriv->hp_flags;
+
+ pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
+
+ switch(board_idx) {
+ case chip_5080:
+ hpriv->ops = &mv5xxx_ops;
+ hp_flags |= MV_HP_50XX;
+
+ switch (rev_id) {
+ case 0x1:
+ hp_flags |= MV_HP_ERRATA_50XXB0;
+ break;
+ case 0x3:
+ hp_flags |= MV_HP_ERRATA_50XXB2;
+ break;
+ default:
+ dev_printk(KERN_WARNING, &pdev->dev,
+ "Applying 50XXB2 workarounds to unknown rev\n");
+ hp_flags |= MV_HP_ERRATA_50XXB2;
+ break;
+ }
+ break;
+
+ case chip_504x:
+ case chip_508x:
+ hpriv->ops = &mv5xxx_ops;
+ hp_flags |= MV_HP_50XX;
+
+ switch (rev_id) {
+ case 0x0:
+ hp_flags |= MV_HP_ERRATA_50XXB0;
+ break;
+ case 0x3:
+ hp_flags |= MV_HP_ERRATA_50XXB2;
+ break;
+ default:
+ dev_printk(KERN_WARNING, &pdev->dev,
+ "Applying B2 workarounds to unknown rev\n");
+ hp_flags |= MV_HP_ERRATA_50XXB2;
+ break;
+ }
+ break;
+
+ case chip_604x:
+ case chip_608x:
+ hpriv->ops = &mv6xxx_ops;
+
+ switch (rev_id) {
+ case 0x7:
+ hp_flags |= MV_HP_ERRATA_60X1B2;
+ break;
+ case 0x9:
+ hp_flags |= MV_HP_ERRATA_60X1C0;
+ break;
+ default:
+ dev_printk(KERN_WARNING, &pdev->dev,
+ "Applying B2 workarounds to unknown rev\n");
+ hp_flags |= MV_HP_ERRATA_60X1B2;
+ break;
+ }
+ break;
+
+ default:
+ printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
+ return 1;
+ }
+
+ hpriv->hp_flags = hp_flags;
+
+ return 0;
+}
+
/**
- * mv_host_init - Perform some early initialization of the host.
+ * mv_init_host - Perform some early initialization of the host.
+ * @pdev: host PCI device
* @probe_ent: early data struct representing the host
*
* If possible, do an early global reset of the host. Then do
@@ -1378,23 +1948,48 @@ static void mv_port_init(struct ata_iopo
* LOCKING:
* Inherited from caller.
*/
-static int mv_host_init(struct ata_probe_ent *probe_ent)
+static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
+ unsigned int board_idx)
{
int rc = 0, n_hc, port, hc;
void __iomem *mmio = probe_ent->mmio_base;
- void __iomem *port_mmio;
+ struct mv_host_priv *hpriv = probe_ent->private_data;
- if ((MV_FLAG_GLBL_SFT_RST & probe_ent->host_flags) &&
- mv_global_soft_reset(probe_ent->mmio_base)) {
- rc = 1;
+ /* global interrupt mask */
+ writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
+
+ rc = mv_chip_id(pdev, hpriv, board_idx);
+ if (rc)
goto done;
- }
n_hc = mv_get_hc_count(probe_ent->host_flags);
probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
+ for (port = 0; port < probe_ent->n_ports; port++)
+ hpriv->ops->read_preamp(hpriv, port, mmio);
+
+ rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
+ if (rc)
+ goto done;
+
+ hpriv->ops->reset_flash(hpriv, mmio);
+ hpriv->ops->reset_bus(pdev, mmio);
+ hpriv->ops->enable_leds(hpriv, mmio);
+
+ for (port = 0; port < probe_ent->n_ports; port++) {
+ if (IS_60XX(hpriv)) {
+ void __iomem *port_mmio = mv_port_base(mmio, port);
+
+ u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
+ ifctl |= (1 << 12);
+ writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
+ }
+
+ hpriv->ops->phy_errata(hpriv, mmio, port);
+ }
+
for (port = 0; port < probe_ent->n_ports; port++) {
- port_mmio = mv_port_base(mmio, port);
+ void __iomem *port_mmio = mv_port_base(mmio, port);
mv_port_init(&probe_ent->port[port], port_mmio);
}
@@ -1418,11 +2013,12 @@ static int mv_host_init(struct ata_probe
writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
- "PCI int cause/mask=0x%08x/0x%08x\n",
+ "PCI int cause/mask=0x%08x/0x%08x\n",
readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
readl(mmio + HC_MAIN_IRQ_MASK_OFS),
readl(mmio + PCI_IRQ_CAUSE_OFS),
readl(mmio + PCI_IRQ_MASK_OFS));
+
done:
return rc;
}
@@ -1458,7 +2054,7 @@ static void mv_print_info(struct ata_pro
dev_printk(KERN_INFO, &pdev->dev,
"%u slots %u ports %s mode IRQ via %s\n",
- (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
+ (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
}
@@ -1528,7 +2124,7 @@ static int mv_init_one(struct pci_dev *p
probe_ent->private_data = hpriv;
/* initialize adapter */
- rc = mv_host_init(probe_ent);
+ rc = mv_init_host(pdev, probe_ent, board_idx);
if (rc) {
goto err_out_hpriv;
}
On Mon, 14 Nov 2005, Jeff Garzik wrote:
> Finally got Marvell 50XX SATA to the point where it, too, complains
> about "ATA: abnormal status 0x80 on port ...11C"... which is progress :)
Thanks for picking up the sata_mv development, Jeff!
I can confirm your results on a 5041 controller:
sata_mv 0000:02:08.0: version 0.25
ACPI: PCI Interrupt 0000:02:08.0[A] -> GSI 26 (level, low) -> IRQ 177
sata_mv 0000:02:08.0: 32 slots 4 ports SCSI mode IRQ via MSI
ata11: SATA max UDMA/133 cmd 0x0 ctl 0xF8C22120 bmdma 0x0 irq 177
ata12: SATA max UDMA/133 cmd 0x0 ctl 0xF8C24120 bmdma 0x0 irq 177
ata13: SATA max UDMA/133 cmd 0x0 ctl 0xF8C26120 bmdma 0x0 irq 177
ata14: SATA max UDMA/133 cmd 0x0 ctl 0xF8C28120 bmdma 0x0 irq 177
ATA: abnormal status 0x80 on port 0xF8C2211C
ata11: dev 0 cfg 49:2f00 82:74eb 83:7feb 84:4123 85:74e9 86:3c03 87:4123 88:007f
ata11: dev 0 ATA-7, max UDMA/133, 781422768 sectors: LBA48
(there is a 400GB Hitachi disk attached to the first port)
However, when running 'insmod ./sata_mv.ko' with a disk attched,
insmod doesn't return, it gets blocked into "D" state (gdb says
"ptrace: Operation not permitted." while strace attaches but doesn't
show anything and cannot be detached). This is with the 2.6.15-rc1
based FC devel kernel (2.6.14-1.1665), using up-to-date FC4 user
space, if that helps... This is not an one-off, I was able to
reproduce it three times out of three :-(
Another thing that I noticed and don't know if it's normal is that the
ataXX ports remain "allocated" even after rmmod; I have two ICH6 ports
(ata1 and 2) and then insmod-ed the sata_mv driver 2 times without
disks attached (which took ata3-6 and ata7-10) and then the insmod
shown above.
Thanks again!
--
Bogdan Costescu
IWR - Interdisziplinaeres Zentrum fuer Wissenschaftliches Rechnen
Universitaet Heidelberg, INF 368, D-69120 Heidelberg, GERMANY
Telephone: +49 6221 54 8869, Telefax: +49 6221 54 8868
E-mail: [email protected]
Bogdan Costescu wrote:
> On Mon, 14 Nov 2005, Jeff Garzik wrote:
>
>> Finally got Marvell 50XX SATA to the point where it, too, complains
>> about "ATA: abnormal status 0x80 on port ...11C"... which is progress :)
>
>
> Thanks for picking up the sata_mv development, Jeff!
>
> I can confirm your results on a 5041 controller:
>
> sata_mv 0000:02:08.0: version 0.25
> ACPI: PCI Interrupt 0000:02:08.0[A] -> GSI 26 (level, low) -> IRQ 177
> sata_mv 0000:02:08.0: 32 slots 4 ports SCSI mode IRQ via MSI
> ata11: SATA max UDMA/133 cmd 0x0 ctl 0xF8C22120 bmdma 0x0 irq 177
> ata12: SATA max UDMA/133 cmd 0x0 ctl 0xF8C24120 bmdma 0x0 irq 177
> ata13: SATA max UDMA/133 cmd 0x0 ctl 0xF8C26120 bmdma 0x0 irq 177
> ata14: SATA max UDMA/133 cmd 0x0 ctl 0xF8C28120 bmdma 0x0 irq 177
> ATA: abnormal status 0x80 on port 0xF8C2211C
> ata11: dev 0 cfg 49:2f00 82:74eb 83:7feb 84:4123 85:74e9 86:3c03 87:4123
> 88:007f
> ata11: dev 0 ATA-7, max UDMA/133, 781422768 sectors: LBA48
>
> (there is a 400GB Hitachi disk attached to the first port)
hey, great, that's farther than I got.
> However, when running 'insmod ./sata_mv.ko' with a disk attched, insmod
> doesn't return, it gets blocked into "D" state (gdb says "ptrace:
> Operation not permitted." while strace attaches but doesn't show
> anything and cannot be detached). This is with the 2.6.15-rc1 based FC
> devel kernel (2.6.14-1.1665), using up-to-date FC4 user space, if that
> helps... This is not an one-off, I was able to reproduce it three times
> out of three :-(
any chance you could obtain additional debugging output by turning on
#undef ATA_DEBUG /* debugging output */
#undef ATA_VERBOSE_DEBUG /* yet more debugging output */
in include/linux/libata.h? this would help us see where it is stuck in
'D' state.
Also, you might try turning off CONFIG_PCI_MSI, in case MSI is
problematic on your machine, or on this card.
> Another thing that I noticed and don't know if it's normal is that the
> ataXX ports remain "allocated" even after rmmod; I have two ICH6 ports
> (ata1 and 2) and then insmod-ed the sata_mv driver 2 times without disks
> attached (which took ata3-6 and ata7-10) and then the insmod shown above.
That's expect, as we just use a simple counter to create a unique id:
host->unique_id = ata_unique_id++;
Regards and thanks,
Jeff
On Tue, 15 Nov 2005, Jeff Garzik wrote:
> any chance you could obtain additional debugging output by turning on
> #undef ATA_DEBUG /* debugging output */
> #undef ATA_VERBOSE_DEBUG /* yet more debugging output */
>
> in include/linux/libata.h? this would help us see where it is stuck in 'D'
> state.
Recompiled only the driver after modification and the output is:
sata_mv 0000:02:08.0: version 0.25
ACPI: PCI Interrupt 0000:02:08.0[A] -> GSI 26 (level, low) -> IRQ 177
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_init_host: HC0: HC config=0x11dcf013 HC IRQ cause (before clear)=0x00000000
mv_init_host: HC MAIN IRQ cause/mask=0x00000000/0x0007ffff PCI int cause/mask=0x00000000/0x00577fe6
mv_dump_pci_cfg: 00: 504111ab 02b00003 01000003 00002008
mv_dump_pci_cfg: 10: f5000004 00000000 00000000 00000000
mv_dump_pci_cfg: 20: 00000000 00000000 00000000 81241043
mv_dump_pci_cfg: 30: 00000000 00000040 00000000 00000109
mv_dump_pci_cfg: 40: 000a5001 00000000 00000000 00000000
mv_dump_pci_cfg: 50: 00816005 fee00000 00000000 000040c1
mv_dump_pci_cfg: 60: 00300007 01830240
sata_mv 0000:02:08.0: 32 slots 4 ports SCSI mode IRQ via MSI
ata7: SATA max UDMA/133 cmd 0x0 ctl 0xF8C22120 bmdma 0x0 irq 177
ata8: SATA max UDMA/133 cmd 0x0 ctl 0xF8C24120 bmdma 0x0 irq 177
ata9: SATA max UDMA/133 cmd 0x0 ctl 0xF8C26120 bmdma 0x0 irq 177
ata10: SATA max UDMA/133 cmd 0x0 ctl 0xF8C28120 bmdma 0x0 irq 177
mv_phy_reset: ENTER, port 0, mmio 0xf8c22000
mv_phy_reset: S-regs after ATA_RST: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
mv_phy_reset: S-regs after PHY wake: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
mv_phy_reset: EXIT
ATA: abnormal status 0x80 on port 0xF8C2211C
ata7: dev 0 cfg 49:2f00 82:74eb 83:7feb 84:4123 85:74e9 86:3c03 87:4123 88:007f
ata7: dev 0 ATA-7, max UDMA/133, 781422768 sectors: LBA48
I don't think that this is really what you wanted - you probably
wanted the place in libata where insmod stops, but the root FS is on
another SATA disk connected to the ICH6, so if I enable DEBUG for
libata this controller/disk will log quite a lot, right ?
> Also, you might try turning off CONFIG_PCI_MSI, in case MSI is
> problematic on your machine, or on this card.
I'll try, but this requires recompiling the kernel. But I'll wait for
the confirmation on whether the whole libata should be DEBUG-ed before
starting the recompilation.
--
Bogdan Costescu
IWR - Interdisziplinaeres Zentrum fuer Wissenschaftliches Rechnen
Universitaet Heidelberg, INF 368, D-69120 Heidelberg, GERMANY
Telephone: +49 6221 54 8869, Telefax: +49 6221 54 8868
E-mail: [email protected]
Bogdan Costescu wrote:
> I don't think that this is really what you wanted - you probably wanted
> the place in libata where insmod stops, but the root FS is on another
> SATA disk connected to the ICH6, so if I enable DEBUG for libata this
> controller/disk will log quite a lot, right ?
Correct on all counts :(
Jeff
On Tue, 15 Nov 2005, Jeff Garzik wrote:
> any chance you could obtain additional debugging output by turning on
> #undef ATA_DEBUG /* debugging output */
> #undef ATA_VERBOSE_DEBUG /* yet more debugging output */
With these 2 defined and CONFIG_PCI_MSI turned off (and root FS on an
IDE disk...), insmod finishes properly, but there is a failed
assertion and the disk is not found anymore :-(
sata_mv 0000:02:08.0: version 0.25
ACPI: PCI Interrupt 0000:02:08.0[A] -> GSI 26 (level, low) -> IRQ 20
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_init_host: HC0: HC config=0x11dcf013 HC IRQ cause (before clear)=0x00000000
mv_init_host: HC MAIN IRQ cause/mask=0x00000000/0x0007ffff PCI int cause/mask=0x00000000/0x00577fe6
mv_dump_pci_cfg: 00: 504111ab 02b00003 01000003 00002008
mv_dump_pci_cfg: 10: f5000004 00000000 00000000 00000000
mv_dump_pci_cfg: 20: 00000000 00000000 00000000 81241043
mv_dump_pci_cfg: 30: 00000000 00000040 00000000 00000109
mv_dump_pci_cfg: 40: 000a5001 00000000 00000000 00000000
mv_dump_pci_cfg: 50: 00806005 00000000 00000000 00000000
mv_dump_pci_cfg: 60: 00300007 01830240
sata_mv 0000:02:08.0: 32 slots 4 ports SCSI mode IRQ via INTx
ata_device_add: ENTER
ata_host_add: ENTER
ata5: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA2120 bmdma 0x0 irq 20
ata_host_add: ENTER
ata6: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA4120 bmdma 0x0 irq 20
ata_host_add: ENTER
ata7: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA6120 bmdma 0x0 irq 20
ata_host_add: ENTER
ata8: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA8120 bmdma 0x0 irq 20
ata_device_add: probe begin
ata_device_add: ata5: probe begin
mv_phy_reset: ENTER, port 0, mmio 0xf8ba2000
mv_phy_reset: S-regs after ATA_RST: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
mv_phy_reset: S-regs after PHY wake: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
ata_dev_classify: found ATA device by sig
mv_phy_reset: EXIT
ata_dev_identify: ENTER, host 5, dev 0
ata_dev_select: ENTER, ata5: device 0, wait 1
ATA: abnormal status 0x80 on port 0xF8BA211C
ata_dev_identify: do ATA identify
ata_dev_select: ENTER, ata5: device 0, wait 1
ata_exec_command_mmio: ata5: cmd 0xEC
mv_host_intr: ENTER, hc0 relevant=0x00000002 HC IRQ cause=0x00000100
mv_host_intr: port 0 IRQ found for qc, ata_status 0x58
ata_qc_complete: EXIT
mv_host_intr: EXIT
mv_host_intr: ENTER, hc0 relevant=0x00000002 HC IRQ cause=0x00000100
mv_host_intr: EXIT
ata5: dev 0 cfg 49:0000 82:0000 83:0000 84:0000 85:0000 86:0000 87:0000 88:0000
ata5: no dma
ata5: dev 0 not supported, ignoring
ata_dev_identify: EXIT, err
ata_dev_identify: ENTER/EXIT (host 5, dev 1) -- nodev
Assertion failed! qc != NULL,drivers/scsi/libata-core.c,ata_pio_block,line=3170
Unable to handle kernel NULL pointer dereference at virtual address 00000014
printing eip:
f886da39
*pde = 3ea2c067
Oops: 0000 [#1]
SMP
Modules linked in: sata_mv(U) sunrpc dm_mod video button battery ac hfc_usb hisax crc_ccitt isdn slhc uhci_hcd ehci_hcd shpchp i6300esb i2c_i801 i2c_core e1000 ext3 jbd ata_piix libata sd_mod scsi_mod
CPU: 1
EIP: 0060:[<f886da39>] Not tainted VLI
EFLAGS: 00010292 (2.6.14-1.1665_FC5nomsismp)
EIP is at ata_pio_block+0x54/0x131 [libata]
eax: 00000056 ebx: 00000058 ecx: 00020000 edx: 00000246
esi: f6fa1314 edi: 00000000 ebp: f6fa1314 esp: f7ecdf3c
ds: 007b es: 007b ss: 0068
Process ata/1 (pid: 380, threadinfo=f7ecd000 task=f7ed2030)
Stack: f8871f88 f8872c86 f88728fa f887926a 00000c62 f6fa1314 f6fa18cc f780111c
f886dbbb 00000212 c0136d06 00000000 f7ecd000 00000000 f7801134 f780113c
f7801154 f7ecd000 f6fa18c8 f886db8f 00000001 00000000 00000000 00010000
Call Trace:
[<f886dbbb>] ata_pio_task+0x2c/0x59 [libata]
[<c0136d06>] worker_thread+0x184/0x235
[<f886db8f>] ata_pio_task+0x0/0x59 [libata]
[<c0122363>] default_wake_function+0x0/0xc
[<c0136b82>] worker_thread+0x0/0x235
[<c013acd9>] kthread+0x93/0x97
[<c013ac46>] kthread+0x0/0x97
[<c010243d>] kernel_thread_helper+0x5/0xb
Code: 0f 95 c0 84 d0 75 dd 89 cb 84 c9 78 58 31 ff 8b 86 70 05 00 00 85 c0 0f 85 ba 00 00 00 89 f7 81 c7 d4 04 00 00 0f 84 ac 00 00 00 <0f> b6 47 14 2c 05 3c 02 77 1a 80 e3 08 0f 85 8c 00 00 00 c7 86
<3>ata_device_add: ata5: probe end
scsi4 : sata_mv
ata_device_add: ata6: probe begin
mv_phy_reset: ENTER, port 1, mmio 0xf8ba4000
mv_phy_reset: S-regs after ATA_RST: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
mv_phy_reset: S-regs after PHY wake: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
ata6: no device found (phy stat 00000000)
ata_device_add: ata6: probe end
scsi5 : sata_mv
ata_device_add: ata7: probe begin
mv_phy_reset: ENTER, port 2, mmio 0xf8ba6000
mv_phy_reset: S-regs after ATA_RST: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
mv_phy_reset: S-regs after PHY wake: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
ata7: no device found (phy stat 00000000)
ata_device_add: ata7: probe end
scsi6 : sata_mv
ata_device_add: ata8: probe begin
mv_phy_reset: ENTER, port 3, mmio 0xf8ba8000
mv_phy_reset: S-regs after ATA_RST: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
mv_phy_reset: S-regs after PHY wake: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
ata8: no device found (phy stat 00000000)
ata_device_add: ata8: probe end
scsi7 : sata_mv
ata_device_add: probe begin
ata_device_add: EXIT, returning 4
--
Bogdan Costescu
IWR - Interdisziplinaeres Zentrum fuer Wissenschaftliches Rechnen
Universitaet Heidelberg, INF 368, D-69120 Heidelberg, GERMANY
Telephone: +49 6221 54 8869, Telefax: +49 6221 54 8868
E-mail: [email protected]
On Tue, 15 Nov 2005, Jeff Garzik wrote:
> any chance you could obtain additional debugging output by turning on
> #undef ATA_DEBUG /* debugging output */
> #undef ATA_VERBOSE_DEBUG /* yet more debugging output */
> Also, you might try turning off CONFIG_PCI_MSI, in case MSI is problematic on
> your machine, or on this card.
With ATA*DEBUG _and_ CONFIG_PCI_MSI, I get again the insmod problem;
the logs are:
sata_mv 0000:02:08.0: version 0.25
ACPI: PCI Interrupt 0000:02:08.0[A] -> GSI 26 (level, low) -> IRQ 201
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_init_host: HC0: HC config=0x11dcf013 HC IRQ cause (before clear)=0x00000000
mv_init_host: HC MAIN IRQ cause/mask=0x00000000/0x0007ffff PCI int cause/mask=0x00000000/0x00577fe6
mv_dump_pci_cfg: 00: 504111ab 02b00007 01000003 00002008
mv_dump_pci_cfg: 10: f5000004 00000000 00000000 00000000
mv_dump_pci_cfg: 20: 00000000 00000000 00000000 81241043
mv_dump_pci_cfg: 30: 00000000 00000040 00000000 00000109
mv_dump_pci_cfg: 40: 000a5001 00000000 00000000 00000000
mv_dump_pci_cfg: 50: 00816005 fee00000 00000000 000040d9
mv_dump_pci_cfg: 60: 00300007 01830240
sata_mv 0000:02:08.0: 32 slots 4 ports SCSI mode IRQ via MSI
ata_device_add: ENTER
ata_host_add: ENTER
ata1: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA2120 bmdma 0x0 irq 201
ata_host_add: ENTER
ata2: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA4120 bmdma 0x0 irq 201
ata_host_add: ENTER
ata3: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA6120 bmdma 0x0 irq 201
ata_host_add: ENTER
ata4: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA8120 bmdma 0x0 irq 201
ata_device_add: probe begin
ata_device_add: ata1: probe begin
mv_phy_reset: ENTER, port 0, mmio 0xf8ba2000
mv_phy_reset: S-regs after ATA_RST: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
mv_phy_reset: S-regs after PHY wake: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
ata_dev_classify: found ATA device by sig
mv_phy_reset: EXIT
ata_dev_identify: ENTER, host 1, dev 0
ata_dev_select: ENTER, ata1: device 0, wait 1
ATA: abnormal status 0x80 on port 0xF8BA211C
ata_dev_identify: do ATA identify
ata_dev_select: ENTER, ata1: device 0, wait 1
ata_exec_command_mmio: ata1: cmd 0xEC
ata_pio_sector: data read
ata_qc_complete: EXIT
ata1: dev 0 cfg 49:2f00 82:74eb 83:7feb 84:4123 85:74e9 86:3c03 87:4123 88:007f
ata_dump_id: 49==0x2f00 53==0x0007 63==0x0407 64==0x0003 75==0x001f
ata_dump_id: 80==0x00fc 81==0x001a 82==0x74eb 83==0x7feb 84==0x4123
ata_dump_id: 88==0x007f 93==0x0000
ata1: dev 0 ATA-7, max UDMA/133, 781422768 sectors: LBA48
ata_dev_identify: EXIT, drv_stat = 0x50
ata_dev_identify: ENTER/EXIT (host 1, dev 1) -- nodev
ata_host_set_pio: base 0x8 xfer_mode 0xc mask 0x1f x 4
ata_dev_set_xfermode: set features - xfer mode
ata_dev_select: ENTER, ata1: device 0, wait 1
ata_tf_load_mmio: feat 0x3 nsect 0x46 lba 0x0 0x0 0x0
ata_tf_load_mmio: device 0xA0
ata_exec_command_mmio: ata1: cmd 0xEF
So, the insmod problem seem to be related to using MSI. OTOH, using
MSI goes a bit further in identifying the attached disk...
--
Bogdan Costescu
IWR - Interdisziplinaeres Zentrum fuer Wissenschaftliches Rechnen
Universitaet Heidelberg, INF 368, D-69120 Heidelberg, GERMANY
Telephone: +49 6221 54 8869, Telefax: +49 6221 54 8868
E-mail: [email protected]
See if you can give the latest git tree a try (what will be
2.6.15-rc1-git6, later tonight). I think I've killed most of the
sata_mv bugs, and have it working here on both 50xx and 60xx.
Jeff
On 11/17/05, Jeff Garzik <[email protected]> wrote:
> See if you can give the latest git tree a try (what will be
> 2.6.15-rc1-git6, later tonight). I think I've killed most of the
> sata_mv bugs, and have it working here on both 50xx and 60xx.
Hey Jeff,
Been reading the patches you've been sending. Thanks for picking it
up--there's no way I have time to work on it lately. Glad to hear you
got it working on 50xx. Some comments:
-in the future, can you separate whitespace only patch mailings with
functional patches? I know that's something you request of others,
but it helps us too.
-the version # of sata_mv doesn't look like it was bumped. Did I miss it?
thanks,
BR
Brett Russ wrote:
> On 11/17/05, Jeff Garzik <[email protected]> wrote:
>
>>See if you can give the latest git tree a try (what will be
>>2.6.15-rc1-git6, later tonight). I think I've killed most of the
>>sata_mv bugs, and have it working here on both 50xx and 60xx.
>
>
> Hey Jeff,
>
> Been reading the patches you've been sending. Thanks for picking it
> up--there's no way I have time to work on it lately. Glad to hear you
> got it working on 50xx. Some comments:
>
> -in the future, can you separate whitespace only patch mailings with
> functional patches? I know that's something you request of others,
> but it helps us too.
They are separated out in the git repo, and also in the automated
mailing list [email protected].
> -the version # of sata_mv doesn't look like it was bumped. Did I miss it?
That was intentional: since sata_mv just went upstream in this upcoming
release (2.6.15), the version number was already bumped.
Jeff
Jeff Garzik wrote:
> Brett Russ wrote:
>> -the version # of sata_mv doesn't look like it was bumped. Did I miss
>> it?
>
>
> That was intentional: since sata_mv just went upstream in this upcoming
> release (2.6.15), the version number was already bumped.
Nevertheless, I needed to add Red Hat to the copyright, so I used that
as an excuse to update the version to 0.5...
Jeff
On Thu, 17 Nov 2005, Jeff Garzik wrote:
> See if you can give the latest git tree a try (what will be
> 2.6.15-rc1-git6, later tonight). I think I've killed most of the
> sata_mv bugs, and have it working here on both 50xx and 60xx.
I can report success as well on a 504x. However it only works without
MSI, with MSI I get the same insmod blocked in D state as before.
I'll try some torture tests with the 2 disks currently attached (on
port 1 and port 3), but I'll have to revert to a non-DEBUG libata to
get rid of the logging...
Many thanks!
--------------------------------------------------------
Without MSI:
sata_mv 0000:02:08.0: version 0.5
ACPI: PCI Interrupt 0000:02:08.0[A] -> GSI 26 (level, low) -> IRQ 20
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_init_host: HC0: HC config=0x11dcf013 HC IRQ cause (before clear)=0x00000000
mv_init_host: HC MAIN IRQ cause/mask=0x00000000/0x0007ffff PCI int cause/mask=0x00000000/0x00577fe6
mv_dump_pci_cfg: 00: 504111ab 02b00007 01000003 00002008
mv_dump_pci_cfg: 10: f5000004 00000000 00000000 00000000
mv_dump_pci_cfg: 20: 00000000 00000000 00000000 81241043
mv_dump_pci_cfg: 30: 00000000 00000040 00000000 00000109
mv_dump_pci_cfg: 40: 000a5001 00000000 00000000 00000000
mv_dump_pci_cfg: 50: 00806005 00000000 00000000 00000000
mv_dump_pci_cfg: 60: 00300007 01830240
sata_mv 0000:02:08.0: 32 slots 4 ports SCSI mode IRQ via INTx
ata_device_add: ENTER
ata_host_add: ENTER
ata1: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA2120 bmdma 0x0 irq 20
ata_host_add: ENTER
ata2: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA4120 bmdma 0x0 irq 20
ata_host_add: ENTER
ata3: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA6120 bmdma 0x0 irq 20
ata_host_add: ENTER
ata4: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA8120 bmdma 0x0 irq 20
ata_device_add: probe begin
ata_device_add: ata1: probe begin
__mv_phy_reset: ENTER, port 0, mmio 0xf8ba2000
__mv_phy_reset: S-regs after ATA_RST: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
__mv_phy_reset: S-regs after PHY wake: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
ata_dev_classify: found ATA device by sig
__mv_phy_reset: EXIT
ata_dev_identify: ENTER, host 1, dev 0
ata_dev_select: ENTER, ata1: device 0, wait 1
ata_dev_identify: do ATA identify
ata_dev_select: ENTER, ata1: device 0, wait 1
ata_exec_command_mmio: ata1: cmd 0xEC
mv_host_intr: ENTER, hc0 relevant=0x00000002 HC IRQ cause=0x00000100
mv_host_intr: port 0 IRQ found for qc, ata_status 0x58
mv_host_intr: EXIT
mv_host_intr: ENTER, hc0 relevant=0x00000002 HC IRQ cause=0x00000100
mv_host_intr: port 0 IRQ found for qc, ata_status 0x58
mv_host_intr: EXIT
ata_pio_sector: data read
ata_qc_complete: EXIT
ata1: dev 0 cfg 49:2f00 82:74eb 83:7feb 84:4123 85:74e9 86:3c03 87:4123 88:007f
ata_dump_id: 49==0x2f00 53==0x0007 63==0x0407 64==0x0003 75==0x001f
ata_dump_id: 80==0x00fc 81==0x001a 82==0x74eb 83==0x7feb 84==0x4123
ata_dump_id: 88==0x007f 93==0x0000
ata1: dev 0 ATA-7, max UDMA/133, 781422768 sectors: LBA48
ata_dev_identify: EXIT, drv_stat = 0x50
ata_dev_identify: ENTER/EXIT (host 1, dev 1) -- nodev
ata_host_set_pio: base 0x8 xfer_mode 0xc mask 0x1f x 4
ata_dev_set_xfermode: set features - xfer mode
ata_dev_select: ENTER, ata1: device 0, wait 1
ata_tf_load_mmio: feat 0x3 nsect 0x46 lba 0x0 0x0 0x0
ata_tf_load_mmio: device 0xA0
ata_exec_command_mmio: ata1: cmd 0xEF
mv_host_intr: ENTER, hc0 relevant=0x00000002 HC IRQ cause=0x00000100
mv_host_intr: port 0 IRQ found for qc, ata_status 0x50
ata_qc_complete: EXIT
mv_host_intr: EXIT
mv_host_intr: ENTER, hc0 relevant=0x00000002 HC IRQ cause=0x00000100
mv_host_intr: EXIT
ata_dev_set_xfermode: EXIT
ata_dev_set_mode: idx=6 xfer_shift=0, xfer_mode=0x46, base=0x40, offset=6
ata1: dev 0 configured for UDMA/133
ata_device_add: ata1: probe end
scsi0 : sata_mv
ata_device_add: ata2: probe begin
__mv_phy_reset: ENTER, port 1, mmio 0xf8ba4000
__mv_phy_reset: S-regs after ATA_RST: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
__mv_phy_reset: S-regs after PHY wake: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
ata2: no device found (phy stat 00000000)
ata_device_add: ata2: probe end
scsi1 : sata_mv
ata_device_add: ata3: probe begin
__mv_phy_reset: ENTER, port 2, mmio 0xf8ba6000
__mv_phy_reset: S-regs after ATA_RST: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
__mv_phy_reset: S-regs after PHY wake: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
ata3: no device found (phy stat 00000000)
ata_device_add: ata3: probe end
scsi2 : sata_mv
ata_device_add: ata4: probe begin
__mv_phy_reset: ENTER, port 3, mmio 0xf8ba8000
__mv_phy_reset: S-regs after ATA_RST: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
__mv_phy_reset: S-regs after PHY wake: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
ata_dev_classify: found ATA device by sig
__mv_phy_reset: EXIT
ata_dev_identify: ENTER, host 4, dev 0
ata_dev_select: ENTER, ata4: device 0, wait 1
ata_dev_identify: do ATA identify
ata_dev_select: ENTER, ata4: device 0, wait 1
ata_exec_command_mmio: ata4: cmd 0xEC
mv_host_intr: ENTER, hc0 relevant=0x00000080 HC IRQ cause=0x00000800
mv_host_intr: port 3 IRQ found for qc, ata_status 0x58
mv_host_intr: EXIT
mv_host_intr: ENTER, hc0 relevant=0x00000080 HC IRQ cause=0x00000800
mv_host_intr: port 3 IRQ found for qc, ata_status 0x58
mv_host_intr: EXIT
ata_pio_sector: data read
ata_qc_complete: EXIT
ata4: dev 0 cfg 49:2f00 82:7c6b 83:7b09 84:4003 85:7c69 86:3a01 87:4003 88:407f
ata_dump_id: 49==0x2f00 53==0x0007 63==0x0407 64==0x0003 75==0x0000
ata_dump_id: 80==0x00fe 81==0x001e 82==0x7c6b 83==0x7b09 84==0x4003
ata_dump_id: 88==0x407f 93==0x0000
ata4: dev 0 ATA-7, max UDMA/133, 240121728 sectors: LBA
ata_dev_identify: EXIT, drv_stat = 0x50
ata_dev_identify: ENTER/EXIT (host 4, dev 1) -- nodev
ata_host_set_pio: base 0x8 xfer_mode 0xc mask 0x1f x 4
ata_dev_set_xfermode: set features - xfer mode
ata_dev_select: ENTER, ata4: device 0, wait 1
ata_tf_load_mmio: feat 0x3 nsect 0x46 lba 0x0 0x0 0x0
ata_tf_load_mmio: device 0xA0
ata_exec_command_mmio: ata4: cmd 0xEF
mv_host_intr: ENTER, hc0 relevant=0x00000080 HC IRQ cause=0x00000800
mv_host_intr: port 3 IRQ found for qc, ata_status 0x50
ata_qc_complete: EXIT
mv_host_intr: EXIT
mv_host_intr: ENTER, hc0 relevant=0x00000080 HC IRQ cause=0x00000800
mv_host_intr: EXIT
ata_dev_set_xfermode: EXIT
ata_dev_set_mode: idx=6 xfer_shift=0, xfer_mode=0x46, base=0x40, offset=6
ata4: dev 0 configured for UDMA/133
ata_device_add: ata4: probe end
scsi3 : sata_mv
ata_device_add: probe begin
ata_scsi_dump_cdb: CDB (1:0,0,0) 12 00 00 00 24 00 5a 5a 5a
ata_scsiop_inq_std: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 12 00 00 00 60 00 5a 5a 5a
ata_scsiop_inq_std: ENTER
Vendor: ATA Model: HDS724040KLSA80 Rev: KFAO
Type: Direct-Access ANSI SCSI revision: 05
ata_scsi_dump_cdb: CDB (1:0,0,0) 00 00 00 00 00 00 5a 5a 5a
ata_scsiop_noop: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 25 00 00 00 00 00 00 00 00
ata_scsiop_read_cap: ENTER
SCSI device sda: 781422768 512-byte hdwr sectors (400088 MB)
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 08 00 00 00 00 00 08
ata_scsiop_mode_sense: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 08 00 00 00 00 00 24
ata_scsiop_mode_sense: ENTER
SCSI device sda: drive cache: write back
ata_scsi_dump_cdb: CDB (1:0,0,0) 00 00 00 00 00 00 5a 5a 5a
ata_scsiop_noop: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 25 00 00 00 00 00 00 00 00
ata_scsiop_read_cap: ENTER
SCSI device sda: 781422768 512-byte hdwr sectors (400088 MB)
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 08 00 00 00 00 00 08
ata_scsiop_mode_sense: ENTER
ata_scsi_dump_cdb: CDB (1:0,0,0) 5a 00 08 00 00 00 00 00 24
ata_scsiop_mode_sense: ENTER
SCSI device sda: drive cache: write back
sda:<3>ata_scsi_dump_cdb: CDB (1:0,0,0) 28 00 00 00 00 00 00 00 08
ata_scsi_translate: ENTER
scsi_10_lba_len: ten-byte command
ata_sg_setup: ENTER, ata1
ata_sg_setup: 1 sg elements mapped
ata_scsi_translate: EXIT
mv_host_intr: ENTER, hc0 relevant=0x00000102 HC IRQ cause=0x00000011
mv_host_intr: port 0 IRQ found for qc, ata_status 0x0
ata_sg_clean: unmapping 1 sg elements
ata_qc_complete: EXIT
mv_host_intr: EXIT
sd 0:0:0:0: Attached scsi disk sda
ata_scsi_dump_cdb: CDB (4:0,0,0) 12 00 00 00 24 00 5a 5a 5a
ata_scsiop_inq_std: ENTER
ata_scsi_dump_cdb: CDB (4:0,0,0) 12 00 00 00 60 00 5a 5a 5a
ata_scsiop_inq_std: ENTER
Vendor: ATA Model: Maxtor 6Y120M0 Rev: YAR5
Type: Direct-Access ANSI SCSI revision: 05
ata_scsi_dump_cdb: CDB (4:0,0,0) 00 00 00 00 00 00 5a 5a 5a
ata_scsiop_noop: ENTER
ata_scsi_dump_cdb: CDB (4:0,0,0) 25 00 00 00 00 00 00 00 00
ata_scsiop_read_cap: ENTER
SCSI device sdb: 240121728 512-byte hdwr sectors (122942 MB)
ata_scsi_dump_cdb: CDB (4:0,0,0) 5a 00 08 00 00 00 00 00 08
ata_scsiop_mode_sense: ENTER
ata_scsi_dump_cdb: CDB (4:0,0,0) 5a 00 08 00 00 00 00 00 24
ata_scsiop_mode_sense: ENTER
SCSI device sdb: drive cache: write back
ata_scsi_dump_cdb: CDB (4:0,0,0) 00 00 00 00 00 00 5a 5a 5a
ata_scsiop_noop: ENTER
ata_scsi_dump_cdb: CDB (4:0,0,0) 25 00 00 00 00 00 00 00 00
ata_scsiop_read_cap: ENTER
SCSI device sdb: 240121728 512-byte hdwr sectors (122942 MB)
ata_scsi_dump_cdb: CDB (4:0,0,0) 5a 00 08 00 00 00 00 00 08
ata_scsiop_mode_sense: ENTER
ata_scsi_dump_cdb: CDB (4:0,0,0) 5a 00 08 00 00 00 00 00 24
ata_scsiop_mode_sense: ENTER
SCSI device sdb: drive cache: write back
sdb:<3>ata_scsi_dump_cdb: CDB (4:0,0,0) 28 00 00 00 00 00 00 00 08
ata_scsi_translate: ENTER
scsi_10_lba_len: ten-byte command
ata_sg_setup: ENTER, ata4
ata_sg_setup: 1 sg elements mapped
ata_scsi_translate: EXIT
mv_host_intr: ENTER, hc0 relevant=0x00000180 HC IRQ cause=0x00000018
mv_host_intr: port 3 IRQ found for qc, ata_status 0x0
ata_sg_clean: unmapping 1 sg elements
ata_qc_complete: EXIT
mv_host_intr: EXIT
sdb1 sdb2
sd 3:0:0:0: Attached scsi disk sdb
ata_device_add: EXIT, returning 4
----------------------------------------------------------
With MSI:
sata_mv 0000:02:08.0: version 0.5
ACPI: PCI Interrupt 0000:02:08.0[A] -> GSI 26 (level, low) -> IRQ 201
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_port_init: EDMA cfg=0x0000011f EDMA IRQ err cause/mask=0x00000000/0x00001f7f
mv_init_host: HC0: HC config=0x11dcf013 HC IRQ cause (before clear)=0x00000000
mv_init_host: HC MAIN IRQ cause/mask=0x00000000/0x0007ffff PCI int cause/mask=0x00000000/0x00577fe6
mv_dump_pci_cfg: 00: 504111ab 02b00007 01000003 00002008
mv_dump_pci_cfg: 10: f5000004 00000000 00000000 00000000
mv_dump_pci_cfg: 20: 00000000 00000000 00000000 81241043
mv_dump_pci_cfg: 30: 00000000 00000040 00000000 00000109
mv_dump_pci_cfg: 40: 000a5001 00000000 00000000 00000000
mv_dump_pci_cfg: 50: 00816005 fee00000 00000000 000040d9
mv_dump_pci_cfg: 60: 00300007 01830240
sata_mv 0000:02:08.0: 32 slots 4 ports SCSI mode IRQ via MSI
ata_device_add: ENTER
ata_host_add: ENTER
ata1: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA2120 bmdma 0x0 irq 201
ata_host_add: ENTER
ata2: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA4120 bmdma 0x0 irq 201
ata_host_add: ENTER
ata3: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA6120 bmdma 0x0 irq 201
ata_host_add: ENTER
ata4: SATA max UDMA/133 cmd 0x0 ctl 0xF8BA8120 bmdma 0x0 irq 201
ata_device_add: probe begin
ata_device_add: ata1: probe begin
__mv_phy_reset: ENTER, port 0, mmio 0xf8ba2000
__mv_phy_reset: S-regs after ATA_RST: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
__mv_phy_reset: S-regs after PHY wake: SStat 0x00000000 SErr 0x00000000 SCtrl 0x00000000
ata_dev_classify: found ATA device by sig
__mv_phy_reset: EXIT
ata_dev_identify: ENTER, host 1, dev 0
ata_dev_select: ENTER, ata1: device 0, wait 1
ata_dev_identify: do ATA identify
ata_dev_select: ENTER, ata1: device 0, wait 1
ata_exec_command_mmio: ata1: cmd 0xEC
ata_pio_sector: data read
ata_qc_complete: EXIT
ata1: dev 0 cfg 49:2f00 82:74eb 83:7feb 84:4123 85:74e9 86:3c03 87:4123 88:007f
ata_dump_id: 49==0x2f00 53==0x0007 63==0x0407 64==0x0003 75==0x001f
ata_dump_id: 80==0x00fc 81==0x001a 82==0x74eb 83==0x7feb 84==0x4123
ata_dump_id: 88==0x007f 93==0x0000
ata1: dev 0 ATA-7, max UDMA/133, 781422768 sectors: LBA48
ata_dev_identify: EXIT, drv_stat = 0x50
ata_dev_identify: ENTER/EXIT (host 1, dev 1) -- nodev
ata_host_set_pio: base 0x8 xfer_mode 0xc mask 0x1f x 4
ata_dev_set_xfermode: set features - xfer mode
ata_dev_select: ENTER, ata1: device 0, wait 1
ata_tf_load_mmio: feat 0x3 nsect 0x46 lba 0x0 0x0 0x0
ata_tf_load_mmio: device 0xA0
ata_exec_command_mmio: ata1: cmd 0xEF
--
Bogdan Costescu
IWR - Interdisziplinaeres Zentrum fuer Wissenschaftliches Rechnen
Universitaet Heidelberg, INF 368, D-69120 Heidelberg, GERMANY
Telephone: +49 6221 54 8869, Telefax: +49 6221 54 8868
E-mail: [email protected]
On Fri, Nov 18, 2005 at 10:50:04PM +0100, Bogdan Costescu wrote:
> On Thu, 17 Nov 2005, Jeff Garzik wrote:
>
> > See if you can give the latest git tree a try (what will be
> > 2.6.15-rc1-git6, later tonight). I think I've killed most of the
> > sata_mv bugs, and have it working here on both 50xx and 60xx.
>
> I can report success as well on a 504x. However it only works without
> MSI, with MSI I get the same insmod blocked in D state as before.
Yes, for both 50xx and 60xx, I had to turn off MSI in order to get
sata_mv to work...
Jeff
Jeff> Yes, for both 50xx and 60xx, I had to turn off MSI in order
Jeff> to get sata_mv to work...
Sounds like MSI is broken in the Marvell chip. This is exactly the
type of knowledge that needs to be in the low-level driver: which
devices/revisions don't have working MSI.
- R.
On Fri, 18 Nov 2005, Jeff Garzik wrote:
> Yes, for both 50xx and 60xx, I had to turn off MSI in order to get
> sata_mv to work...
With MSI and libata DEBUG turned off I had a crash - solid one, SysRQ
doesn't work. I have forgotten to set console to serial port when
booting this kernel, so what follows is what I had on the screen,
hopefully without any typos (and without the initial addresses):
do_IRQ+0x4e/0x86
=====================
common_interrupt+0x1a/0x20
__do_softirq+0x5e/0xdc
do_sortirq+0x4b/0x4f
=====================
apic_timer_interrupt+0x1c/0x24
scsi_request_fn+0x221/0x369 [scsi_mod]
blk_run_queue+0x28/0x37
scsi_next_command+0x26/0x30 [scsi_mod]
scsi_end_request+0x83/0xb0 [scsi_mod]
scsi_io_completion+0x151/0x4d7 [scsi_mod]
sd_rw_intr+0xc9/0x3b4 [sd_mod]
apic_timer_interrupt+0x1c/0x24
scsi_finish_command+0x82/0xd0 [scsi_mod]
scsi_error_handler+0x0/0x124 [scsi_mod]
ata_scsi_qc_complete+0x64/0x77 [libata]
ata_qc_complete+0x32/0xaa [libata]
mv_eng_timeout+0x8b/0x9e [sata_mv]
ata_scsi_error+0xf/0x23 [libata]
scsi_error_handler+0xbc/0x124 [scsi_mod]
kthread+0x93/0x97
kthread+0x0/0x97
kernel+thread_helper+0x5/0xb
This was a SMP kernel running on an Intel PIV with HyperThreading and
with 2 disks attached to the controller. I'll try to get this crash
again with serial console...
--
Bogdan Costescu
IWR - Interdisziplinaeres Zentrum fuer Wissenschaftliches Rechnen
Universitaet Heidelberg, INF 368, D-69120 Heidelberg, GERMANY
Telephone: +49 6221 54 8869, Telefax: +49 6221 54 8868
E-mail: [email protected]
On Mon, 21 Nov 2005, Bogdan Costescu wrote:
> This was a SMP kernel running on an Intel PIV with HyperThreading
> and with 2 disks attached to the controller. I'll try to get this
> crash again with serial console...
I seem to have some problems getting the serial console to work, but
in the mean time I have some more results, this time using a UP
kernel (again without MSI and libata DEBUG):
1. several badblocks tests finished fine; the speed is also fine
(about 50Mbytes/s both read and write as reported by both iostat
during badblocks and bonnie++ on an ext2 FS).
2. I know that we are not yet talking about hotplugging, but this
is what happens if you do it (unplug) :-)
Badness in mv_channel_reset at /root/sata_mv/sata_mv.c:1701 (Not
tainted)
[<f8955282>] mv_channel_reset+0xe3/0xed [sata_mv]
[<f89552b0>] mv_stop_and_reset+0x24/0x2d [sata_mv]
[<f8954ae0>] mv_host_intr+0x13d/0x17c [sata_mv]
[<f8954b92>] mv_interrupt+0x73/0xeb [sata_mv]
[<c0141f0d>] handle_IRQ_event+0x2e/0x5a
[<c0141fb7>] __do_IRQ+0x7e/0xd7
[<c0104e7e>] do_IRQ+0x4a/0x82
=======================
[<c01038ca>] common_interrupt+0x1a/0x20
[<c023a35f>] acpi_safe_halt+0x22/0x2c
[<c023a472>] acpi_processor_idle+0x109/0x27a
[<c01010c1>] cpu_idle+0x40/0x58
[<c03f873f>] start_kernel+0x15b/0x1b2
[<c03f831d>] unknown_bootoption+0x0/0x1b6
Badness in __msleep at /root/sata_mv/sata_mv.c:1721 (Not tainted)
[<f8955649>] __mv_phy_reset+0x390/0x405 [sata_mv]
[<c0111923>] delay_tsc+0xb/0x13
[<c01e7659>] __delay+0x9/0xa
[<f8954ae0>] mv_host_intr+0x13d/0x17c [sata_mv]
[<f8954b92>] mv_interrupt+0x73/0xeb [sata_mv]
[<c0141f0d>] handle_IRQ_event+0x2e/0x5a
[<c0141fb7>] __do_IRQ+0x7e/0xd7
[<c0104e7e>] do_IRQ+0x4a/0x82
=======================
[<c01038ca>] common_interrupt+0x1a/0x20
[<c023a35f>] acpi_safe_halt+0x22/0x2c
[<c023a472>] acpi_processor_idle+0x109/0x27a
[<c01010c1>] cpu_idle+0x40/0x58
[<c03f873f>] start_kernel+0x15b/0x1b2
[<c03f831d>] unknown_bootoption+0x0/0x1b6
ata4: no device found (phy stat 00000000)
The acpi_* stuff might be due to the fact that this interrupt is taken
over first by ACPI and later assigned also to sata_mv; this happens
only with the UP kernel, for the SMP kernel sata_mv did not share the
interrupt.
--
Bogdan Costescu
IWR - Interdisziplinaeres Zentrum fuer Wissenschaftliches Rechnen
Universitaet Heidelberg, INF 368, D-69120 Heidelberg, GERMANY
Telephone: +49 6221 54 8869, Telefax: +49 6221 54 8868
E-mail: [email protected]
Bogdan Costescu wrote:
> On Fri, 18 Nov 2005, Jeff Garzik wrote:
>
>> Yes, for both 50xx and 60xx, I had to turn off MSI in order to get
>> sata_mv to work...
>
>
> With MSI and libata DEBUG turned off I had a crash - solid one, SysRQ
> doesn't work. I have forgotten to set console to serial port when
> booting this kernel, so what follows is what I had on the screen,
> hopefully without any typos (and without the initial addresses):
I wonder if the global reset disables MSI... may be a driver bug.
You could play around with moving the pci_enable_msi until after the
global reset...
Jeff
Bogdan Costescu wrote:
> 1. several badblocks tests finished fine; the speed is also fine (about
> 50Mbytes/s both read and write as reported by both iostat during
> badblocks and bonnie++ on an ext2 FS).
cool
> 2. I know that we are not yet talking about hotplugging, but this is
> what happens if you do it (unplug) :-)
expected (unfortunately...)
Jeff
Roland Dreier wrote:
> Jeff> Yes, for both 50xx and 60xx, I had to turn off MSI in order
> Jeff> to get sata_mv to work...
>
> Sounds like MSI is broken in the Marvell chip. This is exactly the
No, it could be any one of
* broken Marvell chip
* broken system
* driver bug
It hasn't been narrowed down yet.
Jeff
On Wed, 23 Nov 2005, Jeff Garzik wrote:
>> 1. several badblocks tests finished fine; the speed is also fine (about
>> 50Mbytes/s both read and write as reported by both iostat during badblocks
>> and bonnie++ on an ext2 FS).
> cool
... and it's getting even cooler: with 4 WD Raptor 74GB, I get about
65MB/s per disk up to 3 disks accessed simultaneously; only when also
using the 4th disk, the speed per disk decreases to about 50MB/s.
Given than 3*65 ~ 4*50, I might reach some hidden limit, but it's
already quite good. So I'd appreciate if people with similar hardware
could test this, to see if there's a limit in the controller or in my
system ;-)
I have to mention that the above figures were obtained not with RAID0,
but with individual reading from each drive. RAID0 somehow made reads
slower, I got only 120-130 MB/s total speed; writes over RAID0 were as
expected about 200MB/s (I only tried RAID0 with 128k and 1024k chunk
sizes).
When creating the array (with mdadm --create), I got these messages
which I haven't seen before, although I played with SATA and RAID0
with some older kernels:
ata4: translated ATA stat/err 0xd0/00 to SCSI SK/ASC/ASCQ 0xb/47/00
ata4: status=0xd0 { Busy }
ata3: translated ATA stat/err 0xd0/00 to SCSI SK/ASC/ASCQ 0xb/47/00
ata3: status=0xd0 { Busy }
ata2: translated ATA stat/err 0xd0/00 to SCSI SK/ASC/ASCQ 0xb/47/00
ata2: status=0xd0 { Busy }
ata1: translated ATA stat/err 0xd0/00 to SCSI SK/ASC/ASCQ 0xb/47/00
ata1: status=0xd0 { Busy }
(in this order, although the order specified on the mdadm command line
was the opposite).
--
Bogdan Costescu
IWR - Interdisziplinaeres Zentrum fuer Wissenschaftliches Rechnen
Universitaet Heidelberg, INF 368, D-69120 Heidelberg, GERMANY
Telephone: +49 6221 54 8869, Telefax: +49 6221 54 8868
E-mail: [email protected]
On Wed, 23 Nov 2005, Jeff Garzik wrote:
> Bogdan Costescu wrote:
>> With MSI and libata DEBUG turned off I had a crash
>
> I wonder if the global reset disables MSI... may be a driver bug.
I'm sorry, but I don't follow you here: I have specified that MSI was
disabled, so why do you expect this to have any effect ? (I could have
made it clearer by adding a "both" before "turned off"...)
> You could play around with moving the pci_enable_msi until after the global
> reset...
I also don't follow:
pci_enable_msi() is only called from mv_init_one(); I think that the
global reset that you refer to is part of mv_init_host(), but this is
already called in mv_init_one() before pci_enable_msi().
Anyway, during all the speed testing, I was running the exact same
kernel that crashed - with more disks and more activity, and I
couldn't crash it anymore. Could you suggest, based on the stack dump,
how to make it more likely to crash again ?
--
Bogdan Costescu
IWR - Interdisziplinaeres Zentrum fuer Wissenschaftliches Rechnen
Universitaet Heidelberg, INF 368, D-69120 Heidelberg, GERMANY
Telephone: +49 6221 54 8869, Telefax: +49 6221 54 8868
E-mail: [email protected]