In this version of shdma Device Tree support I preserved the DT
configuration approach via OF device ID tables from v4, but now it is only
used for the DT-mode, the C-version is left untouched. In this series I
only include one platform: r8a73a4-based APE6EVM, if accepted, others can
be added easily. I also took care not to include mach/*.h headers in
driver .c files. To illustrate the use of DT DMA support for MMC DMA on
APE6EVM a patch from a previously separate patch series "DMA for MMCIF and
SDHI devices in DT mode"
http://thread.gmane.org/gmane.linux.ports.sh.devel/25445
is now also included in this series.
This series should be applied on top of my previous shdma patches
"DMA: shdma: fix CHCLR register address calculation"
https://lkml.org/lkml/2013/7/2/331
"DMA: shdma: several stylistic improvements and support for new SoCs"
http://thread.gmane.org/gmane.linux.ports.sh.devel/24826
"DMA: shdma: make a pointer const"
http://marc.info/?l=linux-sh&m=137545309332395&w=2
The above dependencies also mean, that the ARM patches shall only be
applied after the DMA patches are upstream.
Cc: Guennadi Liakhovetski <[email protected]>
Guennadi Liakhovetski (7):
DMA: shdma: switch DT mode to use configuration data from a match
table
DMA: shdma: remove private and unused defines from a global header
DMA: shdma: add a header with common for ARM SoCs defines
DMA: shdma: add r8a73a4 DMAC data to the device ID table
ARM: shmobile: r8a73a4: add a DMAC platform device and clock for it
ARM: shmobile: r8a73a4: add a DT node and a clock alias for the DMAC
ARM: shmobile: ape6evm-reference: enable DMA for the MMC interface
Documentation/devicetree/bindings/dma/shdma.txt | 61 +++++++++-------
arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 3 +
arch/arm/boot/dts/r8a73a4.dtsi | 43 +++++++++++
arch/arm/mach-shmobile/clock-r8a73a4.c | 5 +-
arch/arm/mach-shmobile/include/mach/r8a73a4.h | 9 ++
arch/arm/mach-shmobile/setup-r8a73a4.c | 91 +++++++++++++++++++++++
drivers/dma/sh/Kconfig | 4 +
drivers/dma/sh/Makefile | 5 +
drivers/dma/sh/shdma-arm.h | 51 +++++++++++++
drivers/dma/sh/shdma-base.c | 15 ++--
drivers/dma/sh/shdma-of.c | 3 -
drivers/dma/sh/shdma-r8a73a4.c | 77 +++++++++++++++++++
drivers/dma/sh/shdma.h | 8 ++
drivers/dma/sh/{shdma.c => shdmac.c} | 40 +++++++---
drivers/dma/sh/sudmac.c | 3 +-
include/linux/sh_dma.h | 21 -----
include/linux/shdma-base.h | 2 +-
17 files changed, 371 insertions(+), 70 deletions(-)
create mode 100644 drivers/dma/sh/shdma-arm.h
create mode 100644 drivers/dma/sh/shdma-r8a73a4.c
rename drivers/dma/sh/{shdma.c => shdmac.c} (97%)
--
1.7.2.5
Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
This patch adds DMA slave bindings for the two required DMA channels
for MMCIF0 to ape6evm-reference.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
---
arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
index 6797fac..631086a 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
@@ -112,6 +112,9 @@
vmmc-supply = <&vcc_mmc0>;
bus-width = <8>;
non-removable;
+ dmas = <&dmac 0xd1
+ &dmac 0xd2>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
status = "okay";
--
1.7.2.5
Macros, named like TEND or SAR lack a namespace and are too broadly named
for a global header. Besides, they aren't needed globally. Move them to
where they belong - into the driver. Some other macros aren't used at all,
remove them.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
---
drivers/dma/sh/shdmac.c | 9 +++++++++
include/linux/sh_dma.h | 21 ---------------------
2 files changed, 9 insertions(+), 21 deletions(-)
diff --git a/drivers/dma/sh/shdmac.c b/drivers/dma/sh/shdmac.c
index 7a01faa..4412cad 100644
--- a/drivers/dma/sh/shdmac.c
+++ b/drivers/dma/sh/shdmac.c
@@ -37,6 +37,15 @@
#include "../dmaengine.h"
#include "shdma.h"
+/* DMA register */
+#define SAR 0x00
+#define DAR 0x04
+#define TCR 0x08
+#define CHCR 0x0C
+#define DMAOR 0x40
+
+#define TEND 0x18 /* USB-DMAC */
+
#define SH_DMAE_DRV_NAME "sh-dma-engine"
/* Default MEMCPY transfer size = 2^2 = 4 bytes */
diff --git a/include/linux/sh_dma.h b/include/linux/sh_dma.h
index 776ed9d..b7b43b8 100644
--- a/include/linux/sh_dma.h
+++ b/include/linux/sh_dma.h
@@ -94,39 +94,18 @@ struct sh_dmae_pdata {
unsigned int slave_only:1;
};
-/* DMA register */
-#define SAR 0x00
-#define DAR 0x04
-#define TCR 0x08
-#define CHCR 0x0C
-#define DMAOR 0x40
-
-#define TEND 0x18 /* USB-DMAC */
-
/* DMAOR definitions */
#define DMAOR_AE 0x00000004
#define DMAOR_NMIF 0x00000002
#define DMAOR_DME 0x00000001
/* Definitions for the SuperH DMAC */
-#define REQ_L 0x00000000
-#define REQ_E 0x00080000
-#define RACK_H 0x00000000
-#define RACK_L 0x00040000
-#define ACK_R 0x00000000
-#define ACK_W 0x00020000
-#define ACK_H 0x00000000
-#define ACK_L 0x00010000
#define DM_INC 0x00004000
#define DM_DEC 0x00008000
#define DM_FIX 0x0000c000
#define SM_INC 0x00001000
#define SM_DEC 0x00002000
#define SM_FIX 0x00003000
-#define RS_IN 0x00000200
-#define RS_OUT 0x00000300
-#define TS_BLK 0x00000040
-#define TM_BUR 0x00000020
#define CHCR_DE 0x00000001
#define CHCR_TE 0x00000002
#define CHCR_IE 0x00000004
--
1.7.2.5
All shdma DMACs on ARM SoCs share certain register layout patterns, which
are currently defined in arch/arm/mach-shmobile/include/mach/dma-register.h.
That header is included by SoC-specific setup-*.c files to be used in DMAC
platform data. That header, however, cannot be directly used by the driver.
This patch copies those defines into a driver-local header to be used by
Device Tree configurations.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
---
drivers/dma/sh/shdma-arm.h | 51 ++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 51 insertions(+), 0 deletions(-)
create mode 100644 drivers/dma/sh/shdma-arm.h
diff --git a/drivers/dma/sh/shdma-arm.h b/drivers/dma/sh/shdma-arm.h
new file mode 100644
index 0000000..a2b8258
--- /dev/null
+++ b/drivers/dma/sh/shdma-arm.h
@@ -0,0 +1,51 @@
+/*
+ * Renesas SuperH DMA Engine support
+ *
+ * Copyright (C) 2013 Renesas Electronics, Inc.
+ *
+ * This is free software; you can redistribute it and/or modify it under the
+ * terms of version 2 the GNU General Public License as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef SHDMA_ARM_H
+#define SHDMA_ARM_H
+
+#include "shdma.h"
+
+/* Transmit sizes and respective CHCR register values */
+enum {
+ XMIT_SZ_8BIT = 0,
+ XMIT_SZ_16BIT = 1,
+ XMIT_SZ_32BIT = 2,
+ XMIT_SZ_64BIT = 7,
+ XMIT_SZ_128BIT = 3,
+ XMIT_SZ_256BIT = 4,
+ XMIT_SZ_512BIT = 5,
+};
+
+/* log2(size / 8) - used to calculate number of transfers */
+#define SH_DMAE_TS_SHIFT { \
+ [XMIT_SZ_8BIT] = 0, \
+ [XMIT_SZ_16BIT] = 1, \
+ [XMIT_SZ_32BIT] = 2, \
+ [XMIT_SZ_64BIT] = 3, \
+ [XMIT_SZ_128BIT] = 4, \
+ [XMIT_SZ_256BIT] = 5, \
+ [XMIT_SZ_512BIT] = 6, \
+}
+
+#define TS_LOW_BIT 0x3 /* --xx */
+#define TS_HI_BIT 0xc /* xx-- */
+
+#define TS_LOW_SHIFT (3)
+#define TS_HI_SHIFT (20 - 2) /* 2 bits for shifted low TS */
+
+#define TS_INDEX2VAL(i) \
+ ((((i) & TS_LOW_BIT) << TS_LOW_SHIFT) |\
+ (((i) & TS_HI_BIT) << TS_HI_SHIFT))
+
+#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
+#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
+
+#endif
--
1.7.2.5
This configuration data will be used, when DMAC DT support is added to
r8a73a4.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
---
v5:
1. don't include mach/*.h headers
2. don't change the C-case
3. don't include unrelated patches
4. include only one architecture
5. don't use slave addresses and IDs in slave lists
drivers/dma/sh/Kconfig | 4 ++
drivers/dma/sh/Makefile | 3 ++
drivers/dma/sh/shdma-r8a73a4.c | 77 ++++++++++++++++++++++++++++++++++++++++
drivers/dma/sh/shdma.h | 7 ++++
drivers/dma/sh/shdmac.c | 1 +
5 files changed, 92 insertions(+), 0 deletions(-)
create mode 100644 drivers/dma/sh/shdma-r8a73a4.c
diff --git a/drivers/dma/sh/Kconfig b/drivers/dma/sh/Kconfig
index 5c1dee2..d0924b6 100644
--- a/drivers/dma/sh/Kconfig
+++ b/drivers/dma/sh/Kconfig
@@ -22,3 +22,7 @@ config SUDMAC
depends on SH_DMAE_BASE
help
Enable support for the Renesas SUDMAC controllers.
+
+config SHDMA_R8A73A4
+ def_bool y
+ depends on ARCH_R8A73A4 && SH_DMAE != n
diff --git a/drivers/dma/sh/Makefile b/drivers/dma/sh/Makefile
index 893ee09..05a31d4 100644
--- a/drivers/dma/sh/Makefile
+++ b/drivers/dma/sh/Makefile
@@ -1,5 +1,8 @@
obj-$(CONFIG_SH_DMAE_BASE) += shdma-base.o shdma-of.o
obj-$(CONFIG_SH_DMAE) += shdma.o
shdma-y := shdmac.o
+ifeq ($(CONFIG_OF),y)
+shdma-$(CONFIG_SHDMA_R8A73A4) += shdma-r8a73a4.o
+endif
shdma-objs := $(shdma-y)
obj-$(CONFIG_SUDMAC) += sudmac.o
diff --git a/drivers/dma/sh/shdma-r8a73a4.c b/drivers/dma/sh/shdma-r8a73a4.c
new file mode 100644
index 0000000..7cad656
--- /dev/null
+++ b/drivers/dma/sh/shdma-r8a73a4.c
@@ -0,0 +1,77 @@
+/*
+ * Renesas SuperH DMA Engine support for r8a73a4 (APE6) SoCs
+ *
+ * Copyright (C) 2013 Renesas Electronics, Inc.
+ *
+ * This is free software; you can redistribute it and/or modify it under the
+ * terms of version 2 the GNU General Public License as published by the Free
+ * Software Foundation.
+ */
+#include <linux/sh_dma.h>
+
+#include "shdma-arm.h"
+
+const unsigned int dma_ts_shift[] = SH_DMAE_TS_SHIFT;
+
+static const struct sh_dmae_slave_config dma_slaves[] = {
+ {
+ .chcr = CHCR_TX(XMIT_SZ_32BIT),
+ .mid_rid = 0xd1, /* MMC0 Tx */
+ }, {
+ .chcr = CHCR_RX(XMIT_SZ_32BIT),
+ .mid_rid = 0xd2, /* MMC0 Rx */
+ }, {
+ .chcr = CHCR_TX(XMIT_SZ_32BIT),
+ .mid_rid = 0xe1, /* MMC1 Tx */
+ }, {
+ .chcr = CHCR_RX(XMIT_SZ_32BIT),
+ .mid_rid = 0xe2, /* MMC1 Rx */
+ },
+};
+
+#define DMAE_CHANNEL(a, b) \
+ { \
+ .offset = (a) - 0x20, \
+ .dmars = (a) - 0x20 + 0x40, \
+ .chclr_bit = (b), \
+ .chclr_offset = 0x80 - 0x20, \
+ }
+
+static const struct sh_dmae_channel dma_channels[] = {
+ DMAE_CHANNEL(0x8000, 0),
+ DMAE_CHANNEL(0x8080, 1),
+ DMAE_CHANNEL(0x8100, 2),
+ DMAE_CHANNEL(0x8180, 3),
+ DMAE_CHANNEL(0x8200, 4),
+ DMAE_CHANNEL(0x8280, 5),
+ DMAE_CHANNEL(0x8300, 6),
+ DMAE_CHANNEL(0x8380, 7),
+ DMAE_CHANNEL(0x8400, 8),
+ DMAE_CHANNEL(0x8480, 9),
+ DMAE_CHANNEL(0x8500, 10),
+ DMAE_CHANNEL(0x8580, 11),
+ DMAE_CHANNEL(0x8600, 12),
+ DMAE_CHANNEL(0x8680, 13),
+ DMAE_CHANNEL(0x8700, 14),
+ DMAE_CHANNEL(0x8780, 15),
+ DMAE_CHANNEL(0x8800, 16),
+ DMAE_CHANNEL(0x8880, 17),
+ DMAE_CHANNEL(0x8900, 18),
+ DMAE_CHANNEL(0x8980, 19),
+};
+
+const struct sh_dmae_pdata r8a73a4_dma_pdata = {
+ .slave = dma_slaves,
+ .slave_num = ARRAY_SIZE(dma_slaves),
+ .channel = dma_channels,
+ .channel_num = ARRAY_SIZE(dma_channels),
+ .ts_low_shift = TS_LOW_SHIFT,
+ .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
+ .ts_high_shift = TS_HI_SHIFT,
+ .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
+ .ts_shift = dma_ts_shift,
+ .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
+ .dmaor_init = DMAOR_DME,
+ .chclr_present = 1,
+ .chclr_bitwise = 1,
+};
diff --git a/drivers/dma/sh/shdma.h b/drivers/dma/sh/shdma.h
index ff2f93b..5210900 100644
--- a/drivers/dma/sh/shdma.h
+++ b/drivers/dma/sh/shdma.h
@@ -62,4 +62,11 @@ struct sh_dmae_desc {
#define to_sh_dev(chan) container_of(chan->shdma_chan.dma_chan.device,\
struct sh_dmae_device, shdma_dev.dma_dev)
+#ifdef CONFIG_SHDMA_R8A73A4
+extern const struct sh_dmae_pdata r8a73a4_dma_pdata;
+#define r8a73a4_shdma_devid &r8a73a4_dma_pdata
+#else
+#define r8a73a4_shdma_devid NULL
+#endif
+
#endif /* __DMA_SHDMA_H */
diff --git a/drivers/dma/sh/shdmac.c b/drivers/dma/sh/shdmac.c
index 4412cad..bf16b3d 100644
--- a/drivers/dma/sh/shdmac.c
+++ b/drivers/dma/sh/shdmac.c
@@ -677,6 +677,7 @@ static const struct shdma_ops sh_dmae_shdma_ops = {
};
static const struct of_device_id sh_dmae_of_match[] = {
+ {.compatible = "renesas,shdma-r8a73a4", .data = r8a73a4_shdma_devid,},
{}
};
MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
--
1.7.2.5
Add a DMAC platform device and clock definitions for it on r8a73a4.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
---
Depends on "DMA: shdma: support the new CHCLR register layout"
https://lkml.org/lkml/2013/7/10/146
arch/arm/mach-shmobile/clock-r8a73a4.c | 4 +-
arch/arm/mach-shmobile/include/mach/r8a73a4.h | 9 +++
arch/arm/mach-shmobile/setup-r8a73a4.c | 91 +++++++++++++++++++++++++
3 files changed, 103 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 8ea5ef6..357b9bc 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -504,7 +504,7 @@ static struct clk div6_clks[DIV6_NR] = {
/* MSTP */
enum {
- MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
+ MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
MSTP411, MSTP410, MSTP409,
@@ -519,6 +519,7 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */
[MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */
[MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */
+ [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC */
[MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */
[MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
[MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
@@ -578,6 +579,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
+ CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index f3a9b70..3a0ea48 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -1,6 +1,15 @@
#ifndef __ASM_R8A73A4_H__
#define __ASM_R8A73A4_H__
+/* DMA slave IDs */
+enum {
+ SHDMA_SLAVE_INVALID,
+ SHDMA_SLAVE_MMCIF0_TX,
+ SHDMA_SLAVE_MMCIF0_RX,
+ SHDMA_SLAVE_MMCIF1_TX,
+ SHDMA_SLAVE_MMCIF1_RX,
+};
+
void r8a73a4_add_standard_devices(void);
void r8a73a4_add_dt_devices(void);
void r8a73a4_clock_init(void);
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index 2ee45d5..ec77059 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -22,8 +22,10 @@
#include <linux/of_platform.h>
#include <linux/platform_data/irq-renesas-irqc.h>
#include <linux/serial_sci.h>
+#include <linux/sh_dma.h>
#include <linux/sh_timer.h>
#include <mach/common.h>
+#include <mach/dma-register.h>
#include <mach/irqs.h>
#include <mach/r8a73a4.h>
#include <asm/mach/arch.h>
@@ -199,12 +201,101 @@ void __init r8a73a4_add_dt_devices(void)
r8a7790_register_cmt(10);
}
+/* DMA */
+static const struct sh_dmae_slave_config dma_slaves[] = {
+ {
+ .slave_id = SHDMA_SLAVE_MMCIF0_TX,
+ .addr = 0xee200034,
+ .chcr = CHCR_TX(XMIT_SZ_32BIT),
+ .mid_rid = 0xd1,
+ }, {
+ .slave_id = SHDMA_SLAVE_MMCIF0_RX,
+ .addr = 0xee200034,
+ .chcr = CHCR_RX(XMIT_SZ_32BIT),
+ .mid_rid = 0xd2,
+ }, {
+ .slave_id = SHDMA_SLAVE_MMCIF1_TX,
+ .addr = 0xee220034,
+ .chcr = CHCR_TX(XMIT_SZ_32BIT),
+ .mid_rid = 0xe1,
+ }, {
+ .slave_id = SHDMA_SLAVE_MMCIF1_RX,
+ .addr = 0xee220034,
+ .chcr = CHCR_RX(XMIT_SZ_32BIT),
+ .mid_rid = 0xe2,
+ },
+};
+
+#define DMAE_CHANNEL(a, b) \
+ { \
+ .offset = (a) - 0x20, \
+ .dmars = (a) - 0x20 + 0x40, \
+ .chclr_bit = (b), \
+ .chclr_offset = 0x80 - 0x20, \
+ }
+
+static const struct sh_dmae_channel dma_channels[] = {
+ DMAE_CHANNEL(0x8000, 0),
+ DMAE_CHANNEL(0x8080, 1),
+ DMAE_CHANNEL(0x8100, 2),
+ DMAE_CHANNEL(0x8180, 3),
+ DMAE_CHANNEL(0x8200, 4),
+ DMAE_CHANNEL(0x8280, 5),
+ DMAE_CHANNEL(0x8300, 6),
+ DMAE_CHANNEL(0x8380, 7),
+ DMAE_CHANNEL(0x8400, 8),
+ DMAE_CHANNEL(0x8480, 9),
+ DMAE_CHANNEL(0x8500, 10),
+ DMAE_CHANNEL(0x8580, 11),
+ DMAE_CHANNEL(0x8600, 12),
+ DMAE_CHANNEL(0x8680, 13),
+ DMAE_CHANNEL(0x8700, 14),
+ DMAE_CHANNEL(0x8780, 15),
+ DMAE_CHANNEL(0x8800, 16),
+ DMAE_CHANNEL(0x8880, 17),
+ DMAE_CHANNEL(0x8900, 18),
+ DMAE_CHANNEL(0x8980, 19),
+};
+
+static const struct sh_dmae_pdata dma_pdata = {
+ .slave = dma_slaves,
+ .slave_num = ARRAY_SIZE(dma_slaves),
+ .channel = dma_channels,
+ .channel_num = ARRAY_SIZE(dma_channels),
+ .ts_low_shift = TS_LOW_SHIFT,
+ .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
+ .ts_high_shift = TS_HI_SHIFT,
+ .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
+ .ts_shift = dma_ts_shift,
+ .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
+ .dmaor_init = DMAOR_DME,
+ .chclr_present = 1,
+ .chclr_bitwise = 1,
+};
+
+static struct resource dma_resources[] = {
+ DEFINE_RES_MEM(0xe6700020, 0x89e0),
+ DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"),
+ {
+ /* IRQ for channels 0-19 */
+ .start = gic_spi(200),
+ .end = gic_spi(219),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+#define r8a73a4_register_dmac() \
+ platform_device_register_resndata(&platform_bus, "sh-dma-engine", 0, \
+ dma_resources, ARRAY_SIZE(dma_resources), \
+ &dma_pdata, sizeof(dma_pdata))
+
void __init r8a73a4_add_standard_devices(void)
{
r8a73a4_add_dt_devices();
r8a73a4_register_irqc(0);
r8a73a4_register_irqc(1);
r8a73a4_register_thermal();
+ r8a73a4_register_dmac();
}
void __init r8a73a4_init_delay(void)
--
1.7.2.5
Add a DT node for the only system DMAC instance on r8a73a4. The RT DMAC
can be added later under the same multiplexer, because they can serve the
same slaves and use the same MID-RID values. Configuration data is
supplied to the driver, using a compatibility match string.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
---
arch/arm/boot/dts/r8a73a4.dtsi | 43 ++++++++++++++++++++++++++++++++
arch/arm/mach-shmobile/clock-r8a73a4.c | 1 +
2 files changed, 44 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index e344b10..3c9c7f2 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -78,6 +78,49 @@
<0 56 4>, <0 57 4>;
};
+ dmac: dma-multiplexer@0 {
+ compatible = "renesas,shdma-mux";
+ #dma-cells = <1>;
+ dma-channels = <20>;
+ dma-requests = <256>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dma0: dma-controller@e6700020 {
+ compatible = "renesas,shdma-r8a73a4";
+ reg = <0 0xe6700020 0 0x89e0>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 220 4
+ 0 200 4
+ 0 201 4
+ 0 202 4
+ 0 203 4
+ 0 204 4
+ 0 205 4
+ 0 206 4
+ 0 207 4
+ 0 208 4
+ 0 209 4
+ 0 210 4
+ 0 211 4
+ 0 212 4
+ 0 213 4
+ 0 214 4
+ 0 215 4
+ 0 216 4
+ 0 217 4
+ 0 218 4
+ 0 219 4>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19";
+ };
+ };
+
thermal@e61f0000 {
compatible = "renesas,rcar-thermal";
reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 357b9bc..74841ed 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -580,6 +580,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
+ CLKDEV_DEV_ID("e6700020.dma-controller", &mstp_clks[MSTP218]),
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
--
1.7.2.5
This facilitates DMAC DT support by eliminating the need in AUXDATA and
avoiding creating complex DT data. This also fits well with DMAC devices,
of which SoCs often have multiple identical copies and it is perfectly
valid to use a single configuration data set for all of them.
Signed-off-by: Guennadi Liakhovetski <[email protected]>
---
v5: support taking slave addresses from dmaengine_slave_config() calls
and don't use slave IDs.
Documentation/devicetree/bindings/dma/shdma.txt | 61 +++++++++++++----------
drivers/dma/sh/Makefile | 2 +
drivers/dma/sh/shdma-base.c | 15 +++--
drivers/dma/sh/shdma-of.c | 3 -
drivers/dma/sh/shdma.h | 1 +
drivers/dma/sh/{shdma.c => shdmac.c} | 30 +++++++----
drivers/dma/sh/sudmac.c | 3 +-
include/linux/shdma-base.h | 2 +-
8 files changed, 69 insertions(+), 48 deletions(-)
rename drivers/dma/sh/{shdma.c => shdmac.c} (98%)
diff --git a/Documentation/devicetree/bindings/dma/shdma.txt b/Documentation/devicetree/bindings/dma/shdma.txt
index c15994a..2a3f3b8 100644
--- a/Documentation/devicetree/bindings/dma/shdma.txt
+++ b/Documentation/devicetree/bindings/dma/shdma.txt
@@ -22,42 +22,51 @@ Optional properties (currently unused):
* DMA controller
Required properties:
-- compatible: should be "renesas,shdma"
+- compatible: should be of the form "renesas,shdma-<soc>", where <soc> should
+ be replaced with the desired SoC model, e.g.
+ "renesas,shdma-r8a73a4" for the system DMAC on r8a73a4 SoC
Example:
- dmac: dma-mux0 {
+ dmac: dma-multiplexer@0 {
compatible = "renesas,shdma-mux";
#dma-cells = <1>;
- dma-channels = <6>;
+ dma-channels = <20>;
dma-requests = <256>;
- reg = <0 0>; /* Needed for AUXDATA */
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
- dma0: shdma@fe008020 {
- compatible = "renesas,shdma";
- reg = <0xfe008020 0x270>,
- <0xfe009000 0xc>;
+ dma0: dma-controller@e6700020 {
+ compatible = "renesas,shdma-r8a73a4";
+ reg = <0 0xe6700020 0 0x89e0>;
interrupt-parent = <&gic>;
- interrupts = <0 34 4
- 0 28 4
- 0 29 4
- 0 30 4
- 0 31 4
- 0 32 4
- 0 33 4>;
+ interrupts = <0 220 4
+ 0 200 4
+ 0 201 4
+ 0 202 4
+ 0 203 4
+ 0 204 4
+ 0 205 4
+ 0 206 4
+ 0 207 4
+ 0 208 4
+ 0 209 4
+ 0 210 4
+ 0 211 4
+ 0 212 4
+ 0 213 4
+ 0 214 4
+ 0 215 4
+ 0 216 4
+ 0 217 4
+ 0 218 4
+ 0 219 4>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
- "ch4", "ch5";
- };
-
- dma1: shdma@fe018020 {
- ...
- };
-
- dma2: shdma@fe028020 {
- ...
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19";
};
};
diff --git a/drivers/dma/sh/Makefile b/drivers/dma/sh/Makefile
index c962138..893ee09 100644
--- a/drivers/dma/sh/Makefile
+++ b/drivers/dma/sh/Makefile
@@ -1,3 +1,5 @@
obj-$(CONFIG_SH_DMAE_BASE) += shdma-base.o shdma-of.o
obj-$(CONFIG_SH_DMAE) += shdma.o
+shdma-y := shdmac.o
+shdma-objs := $(shdma-y)
obj-$(CONFIG_SUDMAC) += sudmac.o
diff --git a/drivers/dma/sh/shdma-base.c b/drivers/dma/sh/shdma-base.c
index c5ea256..d94ab59 100644
--- a/drivers/dma/sh/shdma-base.c
+++ b/drivers/dma/sh/shdma-base.c
@@ -171,7 +171,8 @@ static struct shdma_desc *shdma_get_desc(struct shdma_chan *schan)
return NULL;
}
-static int shdma_setup_slave(struct shdma_chan *schan, int slave_id)
+static int shdma_setup_slave(struct shdma_chan *schan, int slave_id,
+ dma_addr_t slave_addr)
{
struct shdma_dev *sdev = to_shdma_dev(schan->dma_chan.device);
const struct shdma_ops *ops = sdev->ops;
@@ -179,7 +180,7 @@ static int shdma_setup_slave(struct shdma_chan *schan, int slave_id)
if (schan->dev->of_node) {
match = schan->hw_req;
- ret = ops->set_slave(schan, match, true);
+ ret = ops->set_slave(schan, match, slave_addr, true);
if (ret < 0)
return ret;
@@ -194,7 +195,7 @@ static int shdma_setup_slave(struct shdma_chan *schan, int slave_id)
if (test_and_set_bit(slave_id, shdma_slave_used))
return -EBUSY;
- ret = ops->set_slave(schan, match, false);
+ ret = ops->set_slave(schan, match, slave_addr, false);
if (ret < 0) {
clear_bit(slave_id, shdma_slave_used);
return ret;
@@ -236,7 +237,7 @@ bool shdma_chan_filter(struct dma_chan *chan, void *arg)
if (!schan->dev->of_node && match >= slave_num)
return false;
- ret = ops->set_slave(schan, match, true);
+ ret = ops->set_slave(schan, match, 0, true);
if (ret < 0)
return false;
@@ -259,7 +260,7 @@ static int shdma_alloc_chan_resources(struct dma_chan *chan)
*/
if (slave) {
/* Legacy mode: .private is set in filter */
- ret = shdma_setup_slave(schan, slave->slave_id);
+ ret = shdma_setup_slave(schan, slave->slave_id, 0);
if (ret < 0)
goto esetslave;
} else {
@@ -680,7 +681,9 @@ static int shdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
* channel, while using it...
*/
config = (struct dma_slave_config *)arg;
- ret = shdma_setup_slave(schan, config->slave_id);
+ ret = shdma_setup_slave(schan, config->slave_id,
+ config->direction == DMA_DEV_TO_MEM ?
+ config->src_addr : config->dst_addr);
if (ret < 0)
return ret;
break;
diff --git a/drivers/dma/sh/shdma-of.c b/drivers/dma/sh/shdma-of.c
index 11bcb05..2acf7b6 100644
--- a/drivers/dma/sh/shdma-of.c
+++ b/drivers/dma/sh/shdma-of.c
@@ -45,9 +45,6 @@ static int shdma_of_probe(struct platform_device *pdev)
const struct of_dev_auxdata *lookup = pdev->dev.platform_data;
int ret;
- if (!lookup)
- return -EINVAL;
-
ret = of_dma_controller_register(pdev->dev.of_node,
shdma_of_xlate, pdev);
if (ret < 0)
diff --git a/drivers/dma/sh/shdma.h b/drivers/dma/sh/shdma.h
index 3d9dca1..ff2f93b 100644
--- a/drivers/dma/sh/shdma.h
+++ b/drivers/dma/sh/shdma.h
@@ -31,6 +31,7 @@ struct sh_dmae_chan {
void __iomem *base;
char dev_id[16]; /* unique name per DMAC of channel */
int pm_error;
+ dma_addr_t slave_addr;
};
struct sh_dmae_device {
diff --git a/drivers/dma/sh/shdma.c b/drivers/dma/sh/shdmac.c
similarity index 98%
rename from drivers/dma/sh/shdma.c
rename to drivers/dma/sh/shdmac.c
index 7af64b9..7a01faa 100644
--- a/drivers/dma/sh/shdma.c
+++ b/drivers/dma/sh/shdmac.c
@@ -20,6 +20,8 @@
#include <linux/init.h>
#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/dmaengine.h>
@@ -333,7 +335,7 @@ static const struct sh_dmae_slave_config *dmae_find_slave(
} else {
for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
if (cfg->mid_rid == match) {
- sh_chan->shdma_chan.slave_id = cfg->slave_id;
+ sh_chan->shdma_chan.slave_id = i;
return cfg;
}
}
@@ -342,7 +344,7 @@ static const struct sh_dmae_slave_config *dmae_find_slave(
}
static int sh_dmae_set_slave(struct shdma_chan *schan,
- int slave_id, bool try)
+ int slave_id, dma_addr_t slave_addr, bool try)
{
struct sh_dmae_chan *sh_chan = container_of(schan, struct sh_dmae_chan,
shdma_chan);
@@ -350,8 +352,10 @@ static int sh_dmae_set_slave(struct shdma_chan *schan,
if (!cfg)
return -ENXIO;
- if (!try)
+ if (!try) {
sh_chan->config = cfg;
+ sh_chan->slave_addr = slave_addr ? : cfg->addr;
+ }
return 0;
}
@@ -641,7 +645,7 @@ static dma_addr_t sh_dmae_slave_addr(struct shdma_chan *schan)
* This is an exclusive slave DMA operation, may only be called after a
* successful slave configuration.
*/
- return sh_chan->config->addr;
+ return sh_chan->slave_addr;
}
static struct shdma_desc *sh_dmae_embedded_desc(void *buf, int i)
@@ -663,9 +667,14 @@ static const struct shdma_ops sh_dmae_shdma_ops = {
.get_partial = sh_dmae_get_partial,
};
+static const struct of_device_id sh_dmae_of_match[] = {
+ {}
+};
+MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
+
static int sh_dmae_probe(struct platform_device *pdev)
{
- const struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
+ const struct sh_dmae_pdata *pdata;
unsigned long irqflags = IRQF_DISABLED,
chan_flag[SH_DMAE_MAX_CHANNELS] = {};
int errirq, chan_irq[SH_DMAE_MAX_CHANNELS];
@@ -674,6 +683,11 @@ static int sh_dmae_probe(struct platform_device *pdev)
struct dma_device *dma_dev;
struct resource *chan, *dmars, *errirq_res, *chanirq_res;
+ if (pdev->dev.of_node)
+ pdata = of_match_device(sh_dmae_of_match, &pdev->dev)->data;
+ else
+ pdata = pdev->dev.platform_data;
+
/* get platform data */
if (!pdata || !pdata->channel_num)
return -ENODEV;
@@ -897,12 +911,6 @@ static int sh_dmae_remove(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id sh_dmae_of_match[] = {
- { .compatible = "renesas,shdma", },
- { }
-};
-MODULE_DEVICE_TABLE(of, sh_dmae_of_match);
-
static struct platform_driver sh_dmae_driver = {
.driver = {
.owner = THIS_MODULE,
diff --git a/drivers/dma/sh/sudmac.c b/drivers/dma/sh/sudmac.c
index 3477901..2a8e3c2 100644
--- a/drivers/dma/sh/sudmac.c
+++ b/drivers/dma/sh/sudmac.c
@@ -150,7 +150,8 @@ static const struct sudmac_slave_config *sudmac_find_slave(
return NULL;
}
-static int sudmac_set_slave(struct shdma_chan *schan, int slave_id, bool try)
+static int sudmac_set_slave(struct shdma_chan *schan, int slave_id,
+ dma_addr_t slave_addr, bool try)
{
struct sudmac_chan *sc = to_chan(schan);
const struct sudmac_slave_config *cfg = sudmac_find_slave(sc, slave_id);
diff --git a/include/linux/shdma-base.h b/include/linux/shdma-base.h
index 31cf89f..f92c0a4 100644
--- a/include/linux/shdma-base.h
+++ b/include/linux/shdma-base.h
@@ -96,7 +96,7 @@ struct shdma_ops {
dma_addr_t (*slave_addr)(struct shdma_chan *);
int (*desc_setup)(struct shdma_chan *, struct shdma_desc *,
dma_addr_t, dma_addr_t, size_t *);
- int (*set_slave)(struct shdma_chan *, int, bool);
+ int (*set_slave)(struct shdma_chan *, int, dma_addr_t, bool);
void (*setup_xfer)(struct shdma_chan *, int);
void (*start_xfer)(struct shdma_chan *, struct shdma_desc *);
struct shdma_desc *(*embedded_desc)(void *, int);
--
1.7.2.5
On Fri, Aug 02, 2013 at 04:50:35PM +0200, Guennadi Liakhovetski wrote:
> In this version of shdma Device Tree support I preserved the DT
> configuration approach via OF device ID tables from v4, but now it is only
> used for the DT-mode, the C-version is left untouched. In this series I
> only include one platform: r8a73a4-based APE6EVM, if accepted, others can
> be added easily. I also took care not to include mach/*.h headers in
> driver .c files. To illustrate the use of DT DMA support for MMC DMA on
> APE6EVM a patch from a previously separate patch series "DMA for MMCIF and
> SDHI devices in DT mode"
I have applied all the dma patches, the ARM ones fail for me so should possible
go thru ARM tree.
thanks
~Vinod
On Sun, Aug 25, 2013 at 01:06:57PM +0530, Vinod Koul wrote:
> On Fri, Aug 02, 2013 at 04:50:35PM +0200, Guennadi Liakhovetski wrote:
> > In this version of shdma Device Tree support I preserved the DT
> > configuration approach via OF device ID tables from v4, but now it is only
> > used for the DT-mode, the C-version is left untouched. In this series I
> > only include one platform: r8a73a4-based APE6EVM, if accepted, others can
> > be added easily. I also took care not to include mach/*.h headers in
> > driver .c files. To illustrate the use of DT DMA support for MMC DMA on
> > APE6EVM a patch from a previously separate patch series "DMA for MMCIF and
> > SDHI devices in DT mode"
> I have applied all the dma patches, the ARM ones fail for me so should possible
> go thru ARM tree.
Guennadi, if you need me to queue up any patches please repost them
once their dependencies are available in a stable branch.
On Mon, Aug 26, 2013 at 04:17:25PM +0900, Simon Horman wrote:
> On Sun, Aug 25, 2013 at 01:06:57PM +0530, Vinod Koul wrote:
> > On Fri, Aug 02, 2013 at 04:50:35PM +0200, Guennadi Liakhovetski wrote:
> > > In this version of shdma Device Tree support I preserved the DT
> > > configuration approach via OF device ID tables from v4, but now it is only
> > > used for the DT-mode, the C-version is left untouched. In this series I
> > > only include one platform: r8a73a4-based APE6EVM, if accepted, others can
> > > be added easily. I also took care not to include mach/*.h headers in
> > > driver .c files. To illustrate the use of DT DMA support for MMC DMA on
> > > APE6EVM a patch from a previously separate patch series "DMA for MMCIF and
> > > SDHI devices in DT mode"
> > I have applied all the dma patches, the ARM ones fail for me so should possible
> > go thru ARM tree.
>
> Guennadi, if you need me to queue up any patches please repost them
> once their dependencies are available in a stable branch.
I think Guennadi is on vacation, so can someone queue up the ARM patches and
mierge them thru ARM tree...
~Vinod
--
On Mon, Aug 26, 2013 at 01:19:13PM +0530, Vinod Koul wrote:
> On Mon, Aug 26, 2013 at 04:17:25PM +0900, Simon Horman wrote:
> > On Sun, Aug 25, 2013 at 01:06:57PM +0530, Vinod Koul wrote:
> > > On Fri, Aug 02, 2013 at 04:50:35PM +0200, Guennadi Liakhovetski wrote:
> > > > In this version of shdma Device Tree support I preserved the DT
> > > > configuration approach via OF device ID tables from v4, but now it is only
> > > > used for the DT-mode, the C-version is left untouched. In this series I
> > > > only include one platform: r8a73a4-based APE6EVM, if accepted, others can
> > > > be added easily. I also took care not to include mach/*.h headers in
> > > > driver .c files. To illustrate the use of DT DMA support for MMC DMA on
> > > > APE6EVM a patch from a previously separate patch series "DMA for MMCIF and
> > > > SDHI devices in DT mode"
> > > I have applied all the dma patches, the ARM ones fail for me so should possible
> > > go thru ARM tree.
> >
> > Guennadi, if you need me to queue up any patches please repost them
> > once their dependencies are available in a stable branch.
> I think Guennadi is on vacation, so can someone queue up the ARM patches and
> mierge them thru ARM tree...
I believe he is back from vacation.
Hi Simon,
On Mon, 26 Aug 2013, Simon Horman wrote:
> On Sun, Aug 25, 2013 at 01:06:57PM +0530, Vinod Koul wrote:
> > On Fri, Aug 02, 2013 at 04:50:35PM +0200, Guennadi Liakhovetski wrote:
> > > In this version of shdma Device Tree support I preserved the DT
> > > configuration approach via OF device ID tables from v4, but now it is only
> > > used for the DT-mode, the C-version is left untouched. In this series I
> > > only include one platform: r8a73a4-based APE6EVM, if accepted, others can
> > > be added easily. I also took care not to include mach/*.h headers in
> > > driver .c files. To illustrate the use of DT DMA support for MMC DMA on
> > > APE6EVM a patch from a previously separate patch series "DMA for MMCIF and
> > > SDHI devices in DT mode"
> > I have applied all the dma patches, the ARM ones fail for me so should possible
> > go thru ARM tree.
>
> Guennadi, if you need me to queue up any patches please repost them
> once their dependencies are available in a stable branch.
I've just verified, that the current -next has all DMA and MMCIF
prerequisites for the following my patches:
ARM: shmobile: armadillo800eva-reference: add MMCIF and SDHI DT nodes
ARM: shmobile: r8a73a4: add a DMAC platform device and clock for it
ARM: shmobile: r8a73a4: add a DT node and a clock alias for the DMAC
ARM: shmobile: ape6evm-reference: enable DMA for the MMC interface
ARM: shmobile: ape6evm: disable MMCIF Command Completion Signal
ARM: shmobile: ape6evm: add DMA support to MMCIF
ARM: shmobile: armadillo800eva: disable MMCIF Command Completion Signal
ARM: shmobile: kzm9g: disable MMCIF Command Completion Signal
ARM: shmobile: lager: disable MMCIF Command Completion Signal, add CLK_CTRL2
I can re-send them all to your privetly as an archive, if you like, or you
can pick their latest versions from an archive or from patchwork.
Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
On Thu, Aug 29, 2013 at 01:24:31PM +0200, Guennadi Liakhovetski wrote:
> Hi Simon,
>
> On Mon, 26 Aug 2013, Simon Horman wrote:
>
> > On Sun, Aug 25, 2013 at 01:06:57PM +0530, Vinod Koul wrote:
> > > On Fri, Aug 02, 2013 at 04:50:35PM +0200, Guennadi Liakhovetski wrote:
> > > > In this version of shdma Device Tree support I preserved the DT
> > > > configuration approach via OF device ID tables from v4, but now it is only
> > > > used for the DT-mode, the C-version is left untouched. In this series I
> > > > only include one platform: r8a73a4-based APE6EVM, if accepted, others can
> > > > be added easily. I also took care not to include mach/*.h headers in
> > > > driver .c files. To illustrate the use of DT DMA support for MMC DMA on
> > > > APE6EVM a patch from a previously separate patch series "DMA for MMCIF and
> > > > SDHI devices in DT mode"
> > > I have applied all the dma patches, the ARM ones fail for me so should possible
> > > go thru ARM tree.
> >
> > Guennadi, if you need me to queue up any patches please repost them
> > once their dependencies are available in a stable branch.
>
> I've just verified, that the current -next has all DMA and MMCIF
> prerequisites for the following my patches:
>
> ARM: shmobile: armadillo800eva-reference: add MMCIF and SDHI DT nodes
> ARM: shmobile: r8a73a4: add a DMAC platform device and clock for it
> ARM: shmobile: r8a73a4: add a DT node and a clock alias for the DMAC
> ARM: shmobile: ape6evm-reference: enable DMA for the MMC interface
> ARM: shmobile: ape6evm: disable MMCIF Command Completion Signal
> ARM: shmobile: ape6evm: add DMA support to MMCIF
> ARM: shmobile: armadillo800eva: disable MMCIF Command Completion Signal
> ARM: shmobile: kzm9g: disable MMCIF Command Completion Signal
> ARM: shmobile: lager: disable MMCIF Command Completion Signal, add CLK_CTRL2
>
> I can re-send them all to your privetly as an archive, if you like, or you
> can pick their latest versions from an archive or from patchwork.
Thanks, I can pick them out of patchwork.
On Fri, Aug 02, 2013 at 04:50:40PM +0200, Guennadi Liakhovetski wrote:
> Add a DMAC platform device and clock definitions for it on r8a73a4.
>
> Signed-off-by: Guennadi Liakhovetski <[email protected]>
> ---
>
> Depends on "DMA: shdma: support the new CHCLR register layout"
> https://lkml.org/lkml/2013/7/10/146
That change seems to be present upstream.
Does this patch depend on any of the other patches
in this series?
>
> arch/arm/mach-shmobile/clock-r8a73a4.c | 4 +-
> arch/arm/mach-shmobile/include/mach/r8a73a4.h | 9 +++
> arch/arm/mach-shmobile/setup-r8a73a4.c | 91 +++++++++++++++++++++++++
> 3 files changed, 103 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
> index 8ea5ef6..357b9bc 100644
> --- a/arch/arm/mach-shmobile/clock-r8a73a4.c
> +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
> @@ -504,7 +504,7 @@ static struct clk div6_clks[DIV6_NR] = {
>
> /* MSTP */
> enum {
> - MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
> + MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
> MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
> MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
> MSTP411, MSTP410, MSTP409,
> @@ -519,6 +519,7 @@ static struct clk mstp_clks[MSTP_NR] = {
> [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */
> [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */
> [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */
> + [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC */
> [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */
> [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
> [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
> @@ -578,6 +579,7 @@ static struct clk_lookup lookups[] = {
> CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
> CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
> CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
> + CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
> CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
> CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
> CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
> diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
> index f3a9b70..3a0ea48 100644
> --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
> +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
> @@ -1,6 +1,15 @@
> #ifndef __ASM_R8A73A4_H__
> #define __ASM_R8A73A4_H__
>
> +/* DMA slave IDs */
> +enum {
> + SHDMA_SLAVE_INVALID,
> + SHDMA_SLAVE_MMCIF0_TX,
> + SHDMA_SLAVE_MMCIF0_RX,
> + SHDMA_SLAVE_MMCIF1_TX,
> + SHDMA_SLAVE_MMCIF1_RX,
> +};
> +
> void r8a73a4_add_standard_devices(void);
> void r8a73a4_add_dt_devices(void);
> void r8a73a4_clock_init(void);
> diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
> index 2ee45d5..ec77059 100644
> --- a/arch/arm/mach-shmobile/setup-r8a73a4.c
> +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
> @@ -22,8 +22,10 @@
> #include <linux/of_platform.h>
> #include <linux/platform_data/irq-renesas-irqc.h>
> #include <linux/serial_sci.h>
> +#include <linux/sh_dma.h>
> #include <linux/sh_timer.h>
> #include <mach/common.h>
> +#include <mach/dma-register.h>
> #include <mach/irqs.h>
> #include <mach/r8a73a4.h>
> #include <asm/mach/arch.h>
> @@ -199,12 +201,101 @@ void __init r8a73a4_add_dt_devices(void)
> r8a7790_register_cmt(10);
> }
>
> +/* DMA */
> +static const struct sh_dmae_slave_config dma_slaves[] = {
> + {
> + .slave_id = SHDMA_SLAVE_MMCIF0_TX,
> + .addr = 0xee200034,
> + .chcr = CHCR_TX(XMIT_SZ_32BIT),
> + .mid_rid = 0xd1,
> + }, {
> + .slave_id = SHDMA_SLAVE_MMCIF0_RX,
> + .addr = 0xee200034,
> + .chcr = CHCR_RX(XMIT_SZ_32BIT),
> + .mid_rid = 0xd2,
> + }, {
> + .slave_id = SHDMA_SLAVE_MMCIF1_TX,
> + .addr = 0xee220034,
> + .chcr = CHCR_TX(XMIT_SZ_32BIT),
> + .mid_rid = 0xe1,
> + }, {
> + .slave_id = SHDMA_SLAVE_MMCIF1_RX,
> + .addr = 0xee220034,
> + .chcr = CHCR_RX(XMIT_SZ_32BIT),
> + .mid_rid = 0xe2,
> + },
> +};
> +
> +#define DMAE_CHANNEL(a, b) \
> + { \
> + .offset = (a) - 0x20, \
> + .dmars = (a) - 0x20 + 0x40, \
> + .chclr_bit = (b), \
> + .chclr_offset = 0x80 - 0x20, \
> + }
> +
> +static const struct sh_dmae_channel dma_channels[] = {
> + DMAE_CHANNEL(0x8000, 0),
> + DMAE_CHANNEL(0x8080, 1),
> + DMAE_CHANNEL(0x8100, 2),
> + DMAE_CHANNEL(0x8180, 3),
> + DMAE_CHANNEL(0x8200, 4),
> + DMAE_CHANNEL(0x8280, 5),
> + DMAE_CHANNEL(0x8300, 6),
> + DMAE_CHANNEL(0x8380, 7),
> + DMAE_CHANNEL(0x8400, 8),
> + DMAE_CHANNEL(0x8480, 9),
> + DMAE_CHANNEL(0x8500, 10),
> + DMAE_CHANNEL(0x8580, 11),
> + DMAE_CHANNEL(0x8600, 12),
> + DMAE_CHANNEL(0x8680, 13),
> + DMAE_CHANNEL(0x8700, 14),
> + DMAE_CHANNEL(0x8780, 15),
> + DMAE_CHANNEL(0x8800, 16),
> + DMAE_CHANNEL(0x8880, 17),
> + DMAE_CHANNEL(0x8900, 18),
> + DMAE_CHANNEL(0x8980, 19),
> +};
> +
> +static const struct sh_dmae_pdata dma_pdata = {
> + .slave = dma_slaves,
> + .slave_num = ARRAY_SIZE(dma_slaves),
> + .channel = dma_channels,
> + .channel_num = ARRAY_SIZE(dma_channels),
> + .ts_low_shift = TS_LOW_SHIFT,
> + .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
> + .ts_high_shift = TS_HI_SHIFT,
> + .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
> + .ts_shift = dma_ts_shift,
> + .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
> + .dmaor_init = DMAOR_DME,
> + .chclr_present = 1,
> + .chclr_bitwise = 1,
> +};
> +
> +static struct resource dma_resources[] = {
> + DEFINE_RES_MEM(0xe6700020, 0x89e0),
> + DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"),
> + {
> + /* IRQ for channels 0-19 */
> + .start = gic_spi(200),
> + .end = gic_spi(219),
> + .flags = IORESOURCE_IRQ,
> + },
> +};
> +
> +#define r8a73a4_register_dmac() \
> + platform_device_register_resndata(&platform_bus, "sh-dma-engine", 0, \
> + dma_resources, ARRAY_SIZE(dma_resources), \
> + &dma_pdata, sizeof(dma_pdata))
> +
> void __init r8a73a4_add_standard_devices(void)
> {
> r8a73a4_add_dt_devices();
> r8a73a4_register_irqc(0);
> r8a73a4_register_irqc(1);
> r8a73a4_register_thermal();
> + r8a73a4_register_dmac();
> }
>
> void __init r8a73a4_init_delay(void)
> --
> 1.7.2.5
>
On Fri, Aug 02, 2013 at 04:50:41PM +0200, Guennadi Liakhovetski wrote:
> Add a DT node for the only system DMAC instance on r8a73a4. The RT DMAC
> can be added later under the same multiplexer, because they can serve the
> same slaves and use the same MID-RID values. Configuration data is
> supplied to the driver, using a compatibility match string.
>
> Signed-off-by: Guennadi Liakhovetski <[email protected]>
> ---
> arch/arm/boot/dts/r8a73a4.dtsi | 43 ++++++++++++++++++++++++++++++++
> arch/arm/mach-shmobile/clock-r8a73a4.c | 1 +
> 2 files changed, 44 insertions(+), 0 deletions(-)
Other than patch 5 of this series, which adds the relevant clock,
does this patch depend on any other patches in this series?
>
> diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
> index e344b10..3c9c7f2 100644
> --- a/arch/arm/boot/dts/r8a73a4.dtsi
> +++ b/arch/arm/boot/dts/r8a73a4.dtsi
> @@ -78,6 +78,49 @@
> <0 56 4>, <0 57 4>;
> };
>
> + dmac: dma-multiplexer@0 {
> + compatible = "renesas,shdma-mux";
> + #dma-cells = <1>;
> + dma-channels = <20>;
> + dma-requests = <256>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + dma0: dma-controller@e6700020 {
> + compatible = "renesas,shdma-r8a73a4";
> + reg = <0 0xe6700020 0 0x89e0>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 220 4
> + 0 200 4
> + 0 201 4
> + 0 202 4
> + 0 203 4
> + 0 204 4
> + 0 205 4
> + 0 206 4
> + 0 207 4
> + 0 208 4
> + 0 209 4
> + 0 210 4
> + 0 211 4
> + 0 212 4
> + 0 213 4
> + 0 214 4
> + 0 215 4
> + 0 216 4
> + 0 217 4
> + 0 218 4
> + 0 219 4>;
> + interrupt-names = "error",
> + "ch0", "ch1", "ch2", "ch3",
> + "ch4", "ch5", "ch6", "ch7",
> + "ch8", "ch9", "ch10", "ch11",
> + "ch12", "ch13", "ch14", "ch15",
> + "ch16", "ch17", "ch18", "ch19";
> + };
> + };
> +
> thermal@e61f0000 {
> compatible = "renesas,rcar-thermal";
> reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
> diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
> index 357b9bc..74841ed 100644
> --- a/arch/arm/mach-shmobile/clock-r8a73a4.c
> +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
> @@ -580,6 +580,7 @@ static struct clk_lookup lookups[] = {
> CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
> CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
> CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
> + CLKDEV_DEV_ID("e6700020.dma-controller", &mstp_clks[MSTP218]),
> CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
> CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
> CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
> --
> 1.7.2.5
>
On Fri, Aug 02, 2013 at 04:50:42PM +0200, Guennadi Liakhovetski wrote:
> This patch adds DMA slave bindings for the two required DMA channels
> for MMCIF0 to ape6evm-reference.
>
> Signed-off-by: Guennadi Liakhovetski <[email protected]>
Does this patch depend on any of the other paches in this series?
> ---
> arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
> index 6797fac..631086a 100644
> --- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
> +++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
> @@ -112,6 +112,9 @@
> vmmc-supply = <&vcc_mmc0>;
> bus-width = <8>;
> non-removable;
> + dmas = <&dmac 0xd1
> + &dmac 0xd2>;
> + dma-names = "tx", "rx";
> pinctrl-names = "default";
> pinctrl-0 = <&mmc0_pins>;
> status = "okay";
> --
> 1.7.2.5
>
Hi Simon,
Thanks for following up on this.
On Wed, 25 Sep 2013, Simon Horman wrote:
> On Fri, Aug 02, 2013 at 04:50:40PM +0200, Guennadi Liakhovetski wrote:
> > Add a DMAC platform device and clock definitions for it on r8a73a4.
> >
> > Signed-off-by: Guennadi Liakhovetski <[email protected]>
> > ---
> >
> > Depends on "DMA: shdma: support the new CHCLR register layout"
> > https://lkml.org/lkml/2013/7/10/146
>
> That change seems to be present upstream.
>
> Does this patch depend on any of the other patches
> in this series?
I don't think this one does, however, ?atches 6 and 7 do. But patches 1-4
from this series are already in next, so, the rest can go in too?
Thanks
Guennadi
>
> >
> > arch/arm/mach-shmobile/clock-r8a73a4.c | 4 +-
> > arch/arm/mach-shmobile/include/mach/r8a73a4.h | 9 +++
> > arch/arm/mach-shmobile/setup-r8a73a4.c | 91 +++++++++++++++++++++++++
> > 3 files changed, 103 insertions(+), 1 deletions(-)
> >
> > diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
> > index 8ea5ef6..357b9bc 100644
> > --- a/arch/arm/mach-shmobile/clock-r8a73a4.c
> > +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
> > @@ -504,7 +504,7 @@ static struct clk div6_clks[DIV6_NR] = {
> >
> > /* MSTP */
> > enum {
> > - MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
> > + MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
> > MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
> > MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
> > MSTP411, MSTP410, MSTP409,
> > @@ -519,6 +519,7 @@ static struct clk mstp_clks[MSTP_NR] = {
> > [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */
> > [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */
> > [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */
> > + [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC */
> > [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */
> > [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
> > [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
> > @@ -578,6 +579,7 @@ static struct clk_lookup lookups[] = {
> > CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
> > CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
> > CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
> > + CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
> > CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
> > CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
> > CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
> > diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
> > index f3a9b70..3a0ea48 100644
> > --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
> > +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
> > @@ -1,6 +1,15 @@
> > #ifndef __ASM_R8A73A4_H__
> > #define __ASM_R8A73A4_H__
> >
> > +/* DMA slave IDs */
> > +enum {
> > + SHDMA_SLAVE_INVALID,
> > + SHDMA_SLAVE_MMCIF0_TX,
> > + SHDMA_SLAVE_MMCIF0_RX,
> > + SHDMA_SLAVE_MMCIF1_TX,
> > + SHDMA_SLAVE_MMCIF1_RX,
> > +};
> > +
> > void r8a73a4_add_standard_devices(void);
> > void r8a73a4_add_dt_devices(void);
> > void r8a73a4_clock_init(void);
> > diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
> > index 2ee45d5..ec77059 100644
> > --- a/arch/arm/mach-shmobile/setup-r8a73a4.c
> > +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
> > @@ -22,8 +22,10 @@
> > #include <linux/of_platform.h>
> > #include <linux/platform_data/irq-renesas-irqc.h>
> > #include <linux/serial_sci.h>
> > +#include <linux/sh_dma.h>
> > #include <linux/sh_timer.h>
> > #include <mach/common.h>
> > +#include <mach/dma-register.h>
> > #include <mach/irqs.h>
> > #include <mach/r8a73a4.h>
> > #include <asm/mach/arch.h>
> > @@ -199,12 +201,101 @@ void __init r8a73a4_add_dt_devices(void)
> > r8a7790_register_cmt(10);
> > }
> >
> > +/* DMA */
> > +static const struct sh_dmae_slave_config dma_slaves[] = {
> > + {
> > + .slave_id = SHDMA_SLAVE_MMCIF0_TX,
> > + .addr = 0xee200034,
> > + .chcr = CHCR_TX(XMIT_SZ_32BIT),
> > + .mid_rid = 0xd1,
> > + }, {
> > + .slave_id = SHDMA_SLAVE_MMCIF0_RX,
> > + .addr = 0xee200034,
> > + .chcr = CHCR_RX(XMIT_SZ_32BIT),
> > + .mid_rid = 0xd2,
> > + }, {
> > + .slave_id = SHDMA_SLAVE_MMCIF1_TX,
> > + .addr = 0xee220034,
> > + .chcr = CHCR_TX(XMIT_SZ_32BIT),
> > + .mid_rid = 0xe1,
> > + }, {
> > + .slave_id = SHDMA_SLAVE_MMCIF1_RX,
> > + .addr = 0xee220034,
> > + .chcr = CHCR_RX(XMIT_SZ_32BIT),
> > + .mid_rid = 0xe2,
> > + },
> > +};
> > +
> > +#define DMAE_CHANNEL(a, b) \
> > + { \
> > + .offset = (a) - 0x20, \
> > + .dmars = (a) - 0x20 + 0x40, \
> > + .chclr_bit = (b), \
> > + .chclr_offset = 0x80 - 0x20, \
> > + }
> > +
> > +static const struct sh_dmae_channel dma_channels[] = {
> > + DMAE_CHANNEL(0x8000, 0),
> > + DMAE_CHANNEL(0x8080, 1),
> > + DMAE_CHANNEL(0x8100, 2),
> > + DMAE_CHANNEL(0x8180, 3),
> > + DMAE_CHANNEL(0x8200, 4),
> > + DMAE_CHANNEL(0x8280, 5),
> > + DMAE_CHANNEL(0x8300, 6),
> > + DMAE_CHANNEL(0x8380, 7),
> > + DMAE_CHANNEL(0x8400, 8),
> > + DMAE_CHANNEL(0x8480, 9),
> > + DMAE_CHANNEL(0x8500, 10),
> > + DMAE_CHANNEL(0x8580, 11),
> > + DMAE_CHANNEL(0x8600, 12),
> > + DMAE_CHANNEL(0x8680, 13),
> > + DMAE_CHANNEL(0x8700, 14),
> > + DMAE_CHANNEL(0x8780, 15),
> > + DMAE_CHANNEL(0x8800, 16),
> > + DMAE_CHANNEL(0x8880, 17),
> > + DMAE_CHANNEL(0x8900, 18),
> > + DMAE_CHANNEL(0x8980, 19),
> > +};
> > +
> > +static const struct sh_dmae_pdata dma_pdata = {
> > + .slave = dma_slaves,
> > + .slave_num = ARRAY_SIZE(dma_slaves),
> > + .channel = dma_channels,
> > + .channel_num = ARRAY_SIZE(dma_channels),
> > + .ts_low_shift = TS_LOW_SHIFT,
> > + .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
> > + .ts_high_shift = TS_HI_SHIFT,
> > + .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
> > + .ts_shift = dma_ts_shift,
> > + .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
> > + .dmaor_init = DMAOR_DME,
> > + .chclr_present = 1,
> > + .chclr_bitwise = 1,
> > +};
> > +
> > +static struct resource dma_resources[] = {
> > + DEFINE_RES_MEM(0xe6700020, 0x89e0),
> > + DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"),
> > + {
> > + /* IRQ for channels 0-19 */
> > + .start = gic_spi(200),
> > + .end = gic_spi(219),
> > + .flags = IORESOURCE_IRQ,
> > + },
> > +};
> > +
> > +#define r8a73a4_register_dmac() \
> > + platform_device_register_resndata(&platform_bus, "sh-dma-engine", 0, \
> > + dma_resources, ARRAY_SIZE(dma_resources), \
> > + &dma_pdata, sizeof(dma_pdata))
> > +
> > void __init r8a73a4_add_standard_devices(void)
> > {
> > r8a73a4_add_dt_devices();
> > r8a73a4_register_irqc(0);
> > r8a73a4_register_irqc(1);
> > r8a73a4_register_thermal();
> > + r8a73a4_register_dmac();
> > }
> >
> > void __init r8a73a4_init_delay(void)
> > --
> > 1.7.2.5
> >
>
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
On Wed, Sep 25, 2013 at 08:52:17AM +0200, Guennadi Liakhovetski wrote:
> Hi Simon,
>
> Thanks for following up on this.
>
> On Wed, 25 Sep 2013, Simon Horman wrote:
>
> > On Fri, Aug 02, 2013 at 04:50:40PM +0200, Guennadi Liakhovetski wrote:
> > > Add a DMAC platform device and clock definitions for it on r8a73a4.
> > >
> > > Signed-off-by: Guennadi Liakhovetski <[email protected]>
> > > ---
> > >
> > > Depends on "DMA: shdma: support the new CHCLR register layout"
> > > https://lkml.org/lkml/2013/7/10/146
> >
> > That change seems to be present upstream.
> >
> > Does this patch depend on any of the other patches
> > in this series?
>
> I don't think this one does, however, üatches 6 and 7 do. But patches 1-4
> from this series are already in next, so, the rest can go in too?
Yes, I think there should be a way.
It seems to me that patches 1-4 are present in v3.12-rc1,
could you confirm that is the case? If so it should be straightforward
for me to queue up patches 6 and 7 (and 5 which seems to already be
straightforward).
>
> Thanks
> Guennadi
>
> >
> > >
> > > arch/arm/mach-shmobile/clock-r8a73a4.c | 4 +-
> > > arch/arm/mach-shmobile/include/mach/r8a73a4.h | 9 +++
> > > arch/arm/mach-shmobile/setup-r8a73a4.c | 91 +++++++++++++++++++++++++
> > > 3 files changed, 103 insertions(+), 1 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
> > > index 8ea5ef6..357b9bc 100644
> > > --- a/arch/arm/mach-shmobile/clock-r8a73a4.c
> > > +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
> > > @@ -504,7 +504,7 @@ static struct clk div6_clks[DIV6_NR] = {
> > >
> > > /* MSTP */
> > > enum {
> > > - MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
> > > + MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
> > > MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
> > > MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
> > > MSTP411, MSTP410, MSTP409,
> > > @@ -519,6 +519,7 @@ static struct clk mstp_clks[MSTP_NR] = {
> > > [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */
> > > [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */
> > > [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */
> > > + [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC */
> > > [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */
> > > [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
> > > [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
> > > @@ -578,6 +579,7 @@ static struct clk_lookup lookups[] = {
> > > CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
> > > CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
> > > CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
> > > + CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
> > > CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
> > > CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
> > > CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
> > > diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
> > > index f3a9b70..3a0ea48 100644
> > > --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
> > > +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
> > > @@ -1,6 +1,15 @@
> > > #ifndef __ASM_R8A73A4_H__
> > > #define __ASM_R8A73A4_H__
> > >
> > > +/* DMA slave IDs */
> > > +enum {
> > > + SHDMA_SLAVE_INVALID,
> > > + SHDMA_SLAVE_MMCIF0_TX,
> > > + SHDMA_SLAVE_MMCIF0_RX,
> > > + SHDMA_SLAVE_MMCIF1_TX,
> > > + SHDMA_SLAVE_MMCIF1_RX,
> > > +};
> > > +
> > > void r8a73a4_add_standard_devices(void);
> > > void r8a73a4_add_dt_devices(void);
> > > void r8a73a4_clock_init(void);
> > > diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
> > > index 2ee45d5..ec77059 100644
> > > --- a/arch/arm/mach-shmobile/setup-r8a73a4.c
> > > +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
> > > @@ -22,8 +22,10 @@
> > > #include <linux/of_platform.h>
> > > #include <linux/platform_data/irq-renesas-irqc.h>
> > > #include <linux/serial_sci.h>
> > > +#include <linux/sh_dma.h>
> > > #include <linux/sh_timer.h>
> > > #include <mach/common.h>
> > > +#include <mach/dma-register.h>
> > > #include <mach/irqs.h>
> > > #include <mach/r8a73a4.h>
> > > #include <asm/mach/arch.h>
> > > @@ -199,12 +201,101 @@ void __init r8a73a4_add_dt_devices(void)
> > > r8a7790_register_cmt(10);
> > > }
> > >
> > > +/* DMA */
> > > +static const struct sh_dmae_slave_config dma_slaves[] = {
> > > + {
> > > + .slave_id = SHDMA_SLAVE_MMCIF0_TX,
> > > + .addr = 0xee200034,
> > > + .chcr = CHCR_TX(XMIT_SZ_32BIT),
> > > + .mid_rid = 0xd1,
> > > + }, {
> > > + .slave_id = SHDMA_SLAVE_MMCIF0_RX,
> > > + .addr = 0xee200034,
> > > + .chcr = CHCR_RX(XMIT_SZ_32BIT),
> > > + .mid_rid = 0xd2,
> > > + }, {
> > > + .slave_id = SHDMA_SLAVE_MMCIF1_TX,
> > > + .addr = 0xee220034,
> > > + .chcr = CHCR_TX(XMIT_SZ_32BIT),
> > > + .mid_rid = 0xe1,
> > > + }, {
> > > + .slave_id = SHDMA_SLAVE_MMCIF1_RX,
> > > + .addr = 0xee220034,
> > > + .chcr = CHCR_RX(XMIT_SZ_32BIT),
> > > + .mid_rid = 0xe2,
> > > + },
> > > +};
> > > +
> > > +#define DMAE_CHANNEL(a, b) \
> > > + { \
> > > + .offset = (a) - 0x20, \
> > > + .dmars = (a) - 0x20 + 0x40, \
> > > + .chclr_bit = (b), \
> > > + .chclr_offset = 0x80 - 0x20, \
> > > + }
> > > +
> > > +static const struct sh_dmae_channel dma_channels[] = {
> > > + DMAE_CHANNEL(0x8000, 0),
> > > + DMAE_CHANNEL(0x8080, 1),
> > > + DMAE_CHANNEL(0x8100, 2),
> > > + DMAE_CHANNEL(0x8180, 3),
> > > + DMAE_CHANNEL(0x8200, 4),
> > > + DMAE_CHANNEL(0x8280, 5),
> > > + DMAE_CHANNEL(0x8300, 6),
> > > + DMAE_CHANNEL(0x8380, 7),
> > > + DMAE_CHANNEL(0x8400, 8),
> > > + DMAE_CHANNEL(0x8480, 9),
> > > + DMAE_CHANNEL(0x8500, 10),
> > > + DMAE_CHANNEL(0x8580, 11),
> > > + DMAE_CHANNEL(0x8600, 12),
> > > + DMAE_CHANNEL(0x8680, 13),
> > > + DMAE_CHANNEL(0x8700, 14),
> > > + DMAE_CHANNEL(0x8780, 15),
> > > + DMAE_CHANNEL(0x8800, 16),
> > > + DMAE_CHANNEL(0x8880, 17),
> > > + DMAE_CHANNEL(0x8900, 18),
> > > + DMAE_CHANNEL(0x8980, 19),
> > > +};
> > > +
> > > +static const struct sh_dmae_pdata dma_pdata = {
> > > + .slave = dma_slaves,
> > > + .slave_num = ARRAY_SIZE(dma_slaves),
> > > + .channel = dma_channels,
> > > + .channel_num = ARRAY_SIZE(dma_channels),
> > > + .ts_low_shift = TS_LOW_SHIFT,
> > > + .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
> > > + .ts_high_shift = TS_HI_SHIFT,
> > > + .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
> > > + .ts_shift = dma_ts_shift,
> > > + .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
> > > + .dmaor_init = DMAOR_DME,
> > > + .chclr_present = 1,
> > > + .chclr_bitwise = 1,
> > > +};
> > > +
> > > +static struct resource dma_resources[] = {
> > > + DEFINE_RES_MEM(0xe6700020, 0x89e0),
> > > + DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"),
> > > + {
> > > + /* IRQ for channels 0-19 */
> > > + .start = gic_spi(200),
> > > + .end = gic_spi(219),
> > > + .flags = IORESOURCE_IRQ,
> > > + },
> > > +};
> > > +
> > > +#define r8a73a4_register_dmac() \
> > > + platform_device_register_resndata(&platform_bus, "sh-dma-engine", 0, \
> > > + dma_resources, ARRAY_SIZE(dma_resources), \
> > > + &dma_pdata, sizeof(dma_pdata))
> > > +
> > > void __init r8a73a4_add_standard_devices(void)
> > > {
> > > r8a73a4_add_dt_devices();
> > > r8a73a4_register_irqc(0);
> > > r8a73a4_register_irqc(1);
> > > r8a73a4_register_thermal();
> > > + r8a73a4_register_dmac();
> > > }
> > >
> > > void __init r8a73a4_init_delay(void)
> > > --
> > > 1.7.2.5
> > >
> >
>
> ---
> Guennadi Liakhovetski, Ph.D.
> Freelance Open-Source Software Developer
> http://www.open-technology.de/
>
Hi Guennadi,
apologies for the long delay.
On Wed, Sep 04, 2013 at 05:55:39PM +0900, Simon Horman wrote:
> On Thu, Aug 29, 2013 at 01:24:31PM +0200, Guennadi Liakhovetski wrote:
> > Hi Simon,
> >
> > On Mon, 26 Aug 2013, Simon Horman wrote:
> >
> > > On Sun, Aug 25, 2013 at 01:06:57PM +0530, Vinod Koul wrote:
> > > > On Fri, Aug 02, 2013 at 04:50:35PM +0200, Guennadi Liakhovetski wrote:
> > > > > In this version of shdma Device Tree support I preserved the DT
> > > > > configuration approach via OF device ID tables from v4, but now it is only
> > > > > used for the DT-mode, the C-version is left untouched. In this series I
> > > > > only include one platform: r8a73a4-based APE6EVM, if accepted, others can
> > > > > be added easily. I also took care not to include mach/*.h headers in
> > > > > driver .c files. To illustrate the use of DT DMA support for MMC DMA on
> > > > > APE6EVM a patch from a previously separate patch series "DMA for MMCIF and
> > > > > SDHI devices in DT mode"
> > > > I have applied all the dma patches, the ARM ones fail for me so should possible
> > > > go thru ARM tree.
> > >
> > > Guennadi, if you need me to queue up any patches please repost them
> > > once their dependencies are available in a stable branch.
> >
> > I've just verified, that the current -next has all DMA and MMCIF
> > prerequisites for the following my patches:
> >
> > ARM: shmobile: armadillo800eva-reference: add MMCIF and SDHI DT nodes
I have responded to v4 of this change.
https://patchwork.kernel.org/patch/2928971/
> > ARM: shmobile: r8a73a4: add a DMAC platform device and clock for it
I have responded to v5 of this change.
https://patchwork.kernel.org/patch/2837970/
> > ARM: shmobile: r8a73a4: add a DT node and a clock alias for the DMAC
I have responded to v5 of this change.
https://patchwork.kernel.org/patch/2837971/
> > ARM: shmobile: ape6evm-reference: enable DMA for the MMC interface
I have responded to v5 of this change.
https://patchwork.kernel.org/patch/2837965/
> > ARM: shmobile: ape6evm: disable MMCIF Command Completion Signal
I have queued v1 of this change for v3.13.
https://patchwork.kernel.org/patch/2825871/
> > ARM: shmobile: ape6evm: add DMA support to MMCIF
I have queued v1 of this change for v3.13.
https://patchwork.kernel.org/patch/2831484/
> > ARM: shmobile: armadillo800eva: disable MMCIF Command Completion Signal
I have queued v1 of this change for v3.13.
https://patchwork.kernel.org/patch/2825874/
> > ARM: shmobile: kzm9g: disable MMCIF Command Completion Signal
I have queued v1 of this change for v3.13.
https://patchwork.kernel.org/patch/2825867/
> > ARM: shmobile: lager: disable MMCIF Command Completion Signal, add CLK_CTRL2
I have queued v1 of this change for v3.13.
https://patchwork.kernel.org/patch/2825865/
> >
> > I can re-send them all to your privetly as an archive, if you like, or you
> > can pick their latest versions from an archive or from patchwork.
>
> Thanks, I can pick them out of patchwork.
On Wed, 25 Sep 2013, Simon Horman wrote:
> On Wed, Sep 25, 2013 at 08:52:17AM +0200, Guennadi Liakhovetski wrote:
> > Hi Simon,
> >
> > Thanks for following up on this.
> >
> > On Wed, 25 Sep 2013, Simon Horman wrote:
> >
> > > On Fri, Aug 02, 2013 at 04:50:40PM +0200, Guennadi Liakhovetski wrote:
> > > > Add a DMAC platform device and clock definitions for it on r8a73a4.
> > > >
> > > > Signed-off-by: Guennadi Liakhovetski <[email protected]>
> > > > ---
> > > >
> > > > Depends on "DMA: shdma: support the new CHCLR register layout"
> > > > https://lkml.org/lkml/2013/7/10/146
> > >
> > > That change seems to be present upstream.
> > >
> > > Does this patch depend on any of the other patches
> > > in this series?
> >
> > I don't think this one does, however, üatches 6 and 7 do. But patches 1-4
> > from this series are already in next, so, the rest can go in too?
>
> Yes, I think there should be a way.
>
> It seems to me that patches 1-4 are present in v3.12-rc1,
> could you confirm that is the case?
Yes, you're right, they're there.
Thanks
Guennadi
> If so it should be straightforward
> for me to queue up patches 6 and 7 (and 5 which seems to already be
> straightforward).
>
>
> >
> > Thanks
> > Guennadi
> >
> > >
> > > >
> > > > arch/arm/mach-shmobile/clock-r8a73a4.c | 4 +-
> > > > arch/arm/mach-shmobile/include/mach/r8a73a4.h | 9 +++
> > > > arch/arm/mach-shmobile/setup-r8a73a4.c | 91 +++++++++++++++++++++++++
> > > > 3 files changed, 103 insertions(+), 1 deletions(-)
> > > >
> > > > diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
> > > > index 8ea5ef6..357b9bc 100644
> > > > --- a/arch/arm/mach-shmobile/clock-r8a73a4.c
> > > > +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
> > > > @@ -504,7 +504,7 @@ static struct clk div6_clks[DIV6_NR] = {
> > > >
> > > > /* MSTP */
> > > > enum {
> > > > - MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
> > > > + MSTP218, MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
> > > > MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
> > > > MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
> > > > MSTP411, MSTP410, MSTP409,
> > > > @@ -519,6 +519,7 @@ static struct clk mstp_clks[MSTP_NR] = {
> > > > [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */
> > > > [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */
> > > > [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */
> > > > + [MSTP218] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC */
> > > > [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */
> > > > [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
> > > > [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
> > > > @@ -578,6 +579,7 @@ static struct clk_lookup lookups[] = {
> > > > CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
> > > > CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
> > > > CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
> > > > + CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
> > > > CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
> > > > CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
> > > > CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
> > > > diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
> > > > index f3a9b70..3a0ea48 100644
> > > > --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
> > > > +++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
> > > > @@ -1,6 +1,15 @@
> > > > #ifndef __ASM_R8A73A4_H__
> > > > #define __ASM_R8A73A4_H__
> > > >
> > > > +/* DMA slave IDs */
> > > > +enum {
> > > > + SHDMA_SLAVE_INVALID,
> > > > + SHDMA_SLAVE_MMCIF0_TX,
> > > > + SHDMA_SLAVE_MMCIF0_RX,
> > > > + SHDMA_SLAVE_MMCIF1_TX,
> > > > + SHDMA_SLAVE_MMCIF1_RX,
> > > > +};
> > > > +
> > > > void r8a73a4_add_standard_devices(void);
> > > > void r8a73a4_add_dt_devices(void);
> > > > void r8a73a4_clock_init(void);
> > > > diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
> > > > index 2ee45d5..ec77059 100644
> > > > --- a/arch/arm/mach-shmobile/setup-r8a73a4.c
> > > > +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
> > > > @@ -22,8 +22,10 @@
> > > > #include <linux/of_platform.h>
> > > > #include <linux/platform_data/irq-renesas-irqc.h>
> > > > #include <linux/serial_sci.h>
> > > > +#include <linux/sh_dma.h>
> > > > #include <linux/sh_timer.h>
> > > > #include <mach/common.h>
> > > > +#include <mach/dma-register.h>
> > > > #include <mach/irqs.h>
> > > > #include <mach/r8a73a4.h>
> > > > #include <asm/mach/arch.h>
> > > > @@ -199,12 +201,101 @@ void __init r8a73a4_add_dt_devices(void)
> > > > r8a7790_register_cmt(10);
> > > > }
> > > >
> > > > +/* DMA */
> > > > +static const struct sh_dmae_slave_config dma_slaves[] = {
> > > > + {
> > > > + .slave_id = SHDMA_SLAVE_MMCIF0_TX,
> > > > + .addr = 0xee200034,
> > > > + .chcr = CHCR_TX(XMIT_SZ_32BIT),
> > > > + .mid_rid = 0xd1,
> > > > + }, {
> > > > + .slave_id = SHDMA_SLAVE_MMCIF0_RX,
> > > > + .addr = 0xee200034,
> > > > + .chcr = CHCR_RX(XMIT_SZ_32BIT),
> > > > + .mid_rid = 0xd2,
> > > > + }, {
> > > > + .slave_id = SHDMA_SLAVE_MMCIF1_TX,
> > > > + .addr = 0xee220034,
> > > > + .chcr = CHCR_TX(XMIT_SZ_32BIT),
> > > > + .mid_rid = 0xe1,
> > > > + }, {
> > > > + .slave_id = SHDMA_SLAVE_MMCIF1_RX,
> > > > + .addr = 0xee220034,
> > > > + .chcr = CHCR_RX(XMIT_SZ_32BIT),
> > > > + .mid_rid = 0xe2,
> > > > + },
> > > > +};
> > > > +
> > > > +#define DMAE_CHANNEL(a, b) \
> > > > + { \
> > > > + .offset = (a) - 0x20, \
> > > > + .dmars = (a) - 0x20 + 0x40, \
> > > > + .chclr_bit = (b), \
> > > > + .chclr_offset = 0x80 - 0x20, \
> > > > + }
> > > > +
> > > > +static const struct sh_dmae_channel dma_channels[] = {
> > > > + DMAE_CHANNEL(0x8000, 0),
> > > > + DMAE_CHANNEL(0x8080, 1),
> > > > + DMAE_CHANNEL(0x8100, 2),
> > > > + DMAE_CHANNEL(0x8180, 3),
> > > > + DMAE_CHANNEL(0x8200, 4),
> > > > + DMAE_CHANNEL(0x8280, 5),
> > > > + DMAE_CHANNEL(0x8300, 6),
> > > > + DMAE_CHANNEL(0x8380, 7),
> > > > + DMAE_CHANNEL(0x8400, 8),
> > > > + DMAE_CHANNEL(0x8480, 9),
> > > > + DMAE_CHANNEL(0x8500, 10),
> > > > + DMAE_CHANNEL(0x8580, 11),
> > > > + DMAE_CHANNEL(0x8600, 12),
> > > > + DMAE_CHANNEL(0x8680, 13),
> > > > + DMAE_CHANNEL(0x8700, 14),
> > > > + DMAE_CHANNEL(0x8780, 15),
> > > > + DMAE_CHANNEL(0x8800, 16),
> > > > + DMAE_CHANNEL(0x8880, 17),
> > > > + DMAE_CHANNEL(0x8900, 18),
> > > > + DMAE_CHANNEL(0x8980, 19),
> > > > +};
> > > > +
> > > > +static const struct sh_dmae_pdata dma_pdata = {
> > > > + .slave = dma_slaves,
> > > > + .slave_num = ARRAY_SIZE(dma_slaves),
> > > > + .channel = dma_channels,
> > > > + .channel_num = ARRAY_SIZE(dma_channels),
> > > > + .ts_low_shift = TS_LOW_SHIFT,
> > > > + .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
> > > > + .ts_high_shift = TS_HI_SHIFT,
> > > > + .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
> > > > + .ts_shift = dma_ts_shift,
> > > > + .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
> > > > + .dmaor_init = DMAOR_DME,
> > > > + .chclr_present = 1,
> > > > + .chclr_bitwise = 1,
> > > > +};
> > > > +
> > > > +static struct resource dma_resources[] = {
> > > > + DEFINE_RES_MEM(0xe6700020, 0x89e0),
> > > > + DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"),
> > > > + {
> > > > + /* IRQ for channels 0-19 */
> > > > + .start = gic_spi(200),
> > > > + .end = gic_spi(219),
> > > > + .flags = IORESOURCE_IRQ,
> > > > + },
> > > > +};
> > > > +
> > > > +#define r8a73a4_register_dmac() \
> > > > + platform_device_register_resndata(&platform_bus, "sh-dma-engine", 0, \
> > > > + dma_resources, ARRAY_SIZE(dma_resources), \
> > > > + &dma_pdata, sizeof(dma_pdata))
> > > > +
> > > > void __init r8a73a4_add_standard_devices(void)
> > > > {
> > > > r8a73a4_add_dt_devices();
> > > > r8a73a4_register_irqc(0);
> > > > r8a73a4_register_irqc(1);
> > > > r8a73a4_register_thermal();
> > > > + r8a73a4_register_dmac();
> > > > }
> > > >
> > > > void __init r8a73a4_init_delay(void)
> > > > --
> > > > 1.7.2.5
> > > >
> > >
> >
> > ---
> > Guennadi Liakhovetski, Ph.D.
> > Freelance Open-Source Software Developer
> > http://www.open-technology.de/
> >
>
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/
On Fri, Aug 02, 2013 at 04:50:42PM +0200, Guennadi Liakhovetski wrote:
> This patch adds DMA slave bindings for the two required DMA channels
> for MMCIF0 to ape6evm-reference.
>
> Signed-off-by: Guennadi Liakhovetski <[email protected]>
Thanks, I have queue this up for v3.13.
> ---
> arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
> index 6797fac..631086a 100644
> --- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
> +++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
> @@ -112,6 +112,9 @@
> vmmc-supply = <&vcc_mmc0>;
> bus-width = <8>;
> non-removable;
> + dmas = <&dmac 0xd1
> + &dmac 0xd2>;
> + dma-names = "tx", "rx";
> pinctrl-names = "default";
> pinctrl-0 = <&mmc0_pins>;
> status = "okay";
> --
> 1.7.2.5
>
On Fri, Aug 02, 2013 at 04:50:41PM +0200, Guennadi Liakhovetski wrote:
> Add a DT node for the only system DMAC instance on r8a73a4. The RT DMAC
> can be added later under the same multiplexer, because they can serve the
> same slaves and use the same MID-RID values. Configuration data is
> supplied to the driver, using a compatibility match string.
Hi Guennadi,
please split this up into two patches.
A DT patch that modifies r8a73a4.dtsi and an SoC patch that modifies
clock-r8a73a4.c.
Thanks.
>
> Signed-off-by: Guennadi Liakhovetski <[email protected]>
> ---
> arch/arm/boot/dts/r8a73a4.dtsi | 43 ++++++++++++++++++++++++++++++++
> arch/arm/mach-shmobile/clock-r8a73a4.c | 1 +
> 2 files changed, 44 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
> index e344b10..3c9c7f2 100644
> --- a/arch/arm/boot/dts/r8a73a4.dtsi
> +++ b/arch/arm/boot/dts/r8a73a4.dtsi
> @@ -78,6 +78,49 @@
> <0 56 4>, <0 57 4>;
> };
>
> + dmac: dma-multiplexer@0 {
> + compatible = "renesas,shdma-mux";
> + #dma-cells = <1>;
> + dma-channels = <20>;
> + dma-requests = <256>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + dma0: dma-controller@e6700020 {
> + compatible = "renesas,shdma-r8a73a4";
> + reg = <0 0xe6700020 0 0x89e0>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 220 4
> + 0 200 4
> + 0 201 4
> + 0 202 4
> + 0 203 4
> + 0 204 4
> + 0 205 4
> + 0 206 4
> + 0 207 4
> + 0 208 4
> + 0 209 4
> + 0 210 4
> + 0 211 4
> + 0 212 4
> + 0 213 4
> + 0 214 4
> + 0 215 4
> + 0 216 4
> + 0 217 4
> + 0 218 4
> + 0 219 4>;
> + interrupt-names = "error",
> + "ch0", "ch1", "ch2", "ch3",
> + "ch4", "ch5", "ch6", "ch7",
> + "ch8", "ch9", "ch10", "ch11",
> + "ch12", "ch13", "ch14", "ch15",
> + "ch16", "ch17", "ch18", "ch19";
> + };
> + };
> +
> thermal@e61f0000 {
> compatible = "renesas,rcar-thermal";
> reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
> diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
> index 357b9bc..74841ed 100644
> --- a/arch/arm/mach-shmobile/clock-r8a73a4.c
> +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
> @@ -580,6 +580,7 @@ static struct clk_lookup lookups[] = {
> CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
> CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
> CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
> + CLKDEV_DEV_ID("e6700020.dma-controller", &mstp_clks[MSTP218]),
> CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
> CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
> CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
> --
> 1.7.2.5
>
On Wed, Sep 25, 2013 at 04:56:42PM +0900, Simon Horman wrote:
> On Fri, Aug 02, 2013 at 04:50:42PM +0200, Guennadi Liakhovetski wrote:
> > This patch adds DMA slave bindings for the two required DMA channels
> > for MMCIF0 to ape6evm-reference.
> >
> > Signed-off-by: Guennadi Liakhovetski <[email protected]>
>
> Thanks, I have queue this up for v3.13.
Scratch that. I was careless and forgot that it depends on 6/7 which
I have asked you to split into two patches.
Please include this patch when you repost 6/7.
>
> > ---
> > arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts | 3 +++
> > 1 files changed, 3 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
> > index 6797fac..631086a 100644
> > --- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
> > +++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
> > @@ -112,6 +112,9 @@
> > vmmc-supply = <&vcc_mmc0>;
> > bus-width = <8>;
> > non-removable;
> > + dmas = <&dmac 0xd1
> > + &dmac 0xd2>;
> > + dma-names = "tx", "rx";
> > pinctrl-names = "default";
> > pinctrl-0 = <&mmc0_pins>;
> > status = "okay";
> > --
> > 1.7.2.5
> >
> --
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