Changes since v2:
* Changed to use supports_64bits_atomics() and replaced the split writes
with lo_hi_writeq()
* Added implementation specific group validation to patch 3
* Dropped shared interrupt patch
* Removed unnecessary filter_enable parameter from ampere module
* Added group validation to ampere module
Changes since v1:
* Rather than creating a completely new driver, implemented as a submodule
of Arm CoreSight PMU driver
* Fixed shared filter handling
Ilkka Koskinen (4):
perf: arm_cspmu: Split 64-bit write to 32-bit writes
perf: arm_cspmu: Support implementation specific filters
perf: arm_cspmu: Support implementation specific validation
perf: arm_cspmu: ampere_cspmu: Add support for Ampere SoC PMU
.../admin-guide/perf/ampere_cspmu.rst | 29 +++
drivers/perf/arm_cspmu/Makefile | 2 +-
drivers/perf/arm_cspmu/ampere_cspmu.c | 243 ++++++++++++++++++
drivers/perf/arm_cspmu/ampere_cspmu.h | 17 ++
drivers/perf/arm_cspmu/arm_cspmu.c | 33 ++-
drivers/perf/arm_cspmu/arm_cspmu.h | 8 +
6 files changed, 327 insertions(+), 5 deletions(-)
create mode 100644 Documentation/admin-guide/perf/ampere_cspmu.rst
create mode 100644 drivers/perf/arm_cspmu/ampere_cspmu.c
create mode 100644 drivers/perf/arm_cspmu/ampere_cspmu.h
--
2.40.1
Split the 64-bit register accesses if 64-bit access is not supported
by the PMU.
Signed-off-by: Ilkka Koskinen <[email protected]>
---
drivers/perf/arm_cspmu/arm_cspmu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c b/drivers/perf/arm_cspmu/arm_cspmu.c
index a3f1c410b417..f8b4a149eb88 100644
--- a/drivers/perf/arm_cspmu/arm_cspmu.c
+++ b/drivers/perf/arm_cspmu/arm_cspmu.c
@@ -702,7 +702,10 @@ static void arm_cspmu_write_counter(struct perf_event *event, u64 val)
if (use_64b_counter_reg(cspmu)) {
offset = counter_offset(sizeof(u64), event->hw.idx);
- writeq(val, cspmu->base1 + offset);
+ if (supports_64bit_atomics(cspmu))
+ writeq(val, cspmu->base1 + offset);
+ else
+ lo_hi_writeq(val, cspmu->base1 + offset);
} else {
offset = counter_offset(sizeof(u32), event->hw.idx);
--
2.40.1
> -----Original Message-----
> From: Ilkka Koskinen <[email protected]>
> Sent: Wednesday, June 7, 2023 3:32 PM
> To: Jonathan Corbet <[email protected]>; Will Deacon <[email protected]>; Mark
> Rutland <[email protected]>; Besar Wicaksono
> <[email protected]>; Suzuki K Poulose <[email protected]>;
> Robin Murphy <[email protected]>
> Cc: [email protected]; [email protected]; linux-arm-
> [email protected]; Ilkka Koskinen <[email protected]>
> Subject: [PATCH v3 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes
>
> External email: Use caution opening links or attachments
>
>
> Split the 64-bit register accesses if 64-bit access is not supported
> by the PMU.
>
> Signed-off-by: Ilkka Koskinen <[email protected]>
> ---
> drivers/perf/arm_cspmu/arm_cspmu.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c
> b/drivers/perf/arm_cspmu/arm_cspmu.c
> index a3f1c410b417..f8b4a149eb88 100644
> --- a/drivers/perf/arm_cspmu/arm_cspmu.c
> +++ b/drivers/perf/arm_cspmu/arm_cspmu.c
> @@ -702,7 +702,10 @@ static void arm_cspmu_write_counter(struct
> perf_event *event, u64 val)
> if (use_64b_counter_reg(cspmu)) {
> offset = counter_offset(sizeof(u64), event->hw.idx);
>
> - writeq(val, cspmu->base1 + offset);
> + if (supports_64bit_atomics(cspmu))
Looks good to me, but this function was recently replaced by
arm_cspmu::has_atomic_dword. Please rebase the patch.
Thanks,
Besar
> + writeq(val, cspmu->base1 + offset);
> + else
> + lo_hi_writeq(val, cspmu->base1 + offset);
> } else {
> offset = counter_offset(sizeof(u32), event->hw.idx);
>
> --
> 2.40.1
Hi Besar,
On Tue, 20 Jun 2023, Besar Wicaksono wrote:
>> -----Original Message-----
>> From: Ilkka Koskinen <[email protected]>
>> Sent: Wednesday, June 7, 2023 3:32 PM
>> To: Jonathan Corbet <[email protected]>; Will Deacon <[email protected]>; Mark
>> Rutland <[email protected]>; Besar Wicaksono
>> <[email protected]>; Suzuki K Poulose <[email protected]>;
>> Robin Murphy <[email protected]>
>> Cc: [email protected]; [email protected]; linux-arm-
>> [email protected]; Ilkka Koskinen <[email protected]>
>> Subject: [PATCH v3 1/4] perf: arm_cspmu: Split 64-bit write to 32-bit writes
>>
>> External email: Use caution opening links or attachments
>>
>>
>> Split the 64-bit register accesses if 64-bit access is not supported
>> by the PMU.
>>
>> Signed-off-by: Ilkka Koskinen <[email protected]>
>> ---
>> drivers/perf/arm_cspmu/arm_cspmu.c | 5 ++++-
>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/perf/arm_cspmu/arm_cspmu.c
>> b/drivers/perf/arm_cspmu/arm_cspmu.c
>> index a3f1c410b417..f8b4a149eb88 100644
>> --- a/drivers/perf/arm_cspmu/arm_cspmu.c
>> +++ b/drivers/perf/arm_cspmu/arm_cspmu.c
>> @@ -702,7 +702,10 @@ static void arm_cspmu_write_counter(struct
>> perf_event *event, u64 val)
>> if (use_64b_counter_reg(cspmu)) {
>> offset = counter_offset(sizeof(u64), event->hw.idx);
>>
>> - writeq(val, cspmu->base1 + offset);
>> + if (supports_64bit_atomics(cspmu))
>
> Looks good to me, but this function was recently replaced by
> arm_cspmu::has_atomic_dword. Please rebase the patch.
Sure, I do that.
Cheers, Ilkka
>
> Thanks,
> Besar
>
>> + writeq(val, cspmu->base1 + offset);
>> + else
>> + lo_hi_writeq(val, cspmu->base1 + offset);
>> } else {
>> offset = counter_offset(sizeof(u32), event->hw.idx);
>>
>> --
>> 2.40.1
>
>