Dear All,
This patchset is a resurrection of the DW PCIe support for the Exynos5433
SoCs posted long time ago here: https://lkml.org/lkml/2016/12/26/6 and
later here: https://lkml.org/lkml/2017/12/21/296 .
In meantime the support for the Exynos5440 SoCs has been completely
dropped from mainline kernel, as those SoCs never reached the market. The
PCIe driver for Exynos5440 variant however has not been removed yet. This
patchset simply reworks it to support the Exynos5433 variant. The lack of
the need to support both variants significantly simplifies the driver
code.
This patchset is based on the following branch:
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git pci-more-dwc-cleanup
Best regards,
Marek Szyprowski
Changelog:
v3:
- rebased onto "[00/13] PCI: dwc: Another round of clean-ups" patchset:
https://patchwork.kernel.org/project/linux-samsung-soc/cover/[email protected]/
- fixed issues pointed by Rob in the driver logic:
* removed DBI_RO_WR_EN register poking
* made driver a standard module
- fixed section mismatch issue
- added "num-viewport = <3>" property to dts and bindings to fix warning
v2: https://lore.kernel.org/linux-samsung-soc/[email protected]/
- fixed issues in dt-bindings pointed by Krzysztof and Rob
v1: https://lore.kernel.org/linux-samsung-soc/[email protected]/
- initial version of this resurrected patchset
Patch summary:
Jaehoon Chung (3):
phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433
PCIe PHY
pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant
arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards
Marek Szyprowski (3):
dt-bindings: pci: drop samsung,exynos5440-pcie binding
dt-bindings: pci: add the samsung,exynos-pcie binding
dt-bindings: phy: add the samsung,exynos-pcie-phy binding
.../bindings/pci/samsung,exynos-pcie.yaml | 119 ++++++
.../bindings/pci/samsung,exynos5440-pcie.txt | 58 ---
.../bindings/phy/samsung,exynos-pcie-phy.yaml | 51 +++
.../boot/dts/exynos/exynos5433-pinctrl.dtsi | 2 +-
.../dts/exynos/exynos5433-tm2-common.dtsi | 24 +-
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 36 ++
drivers/pci/controller/dwc/Kconfig | 10 +-
drivers/pci/controller/dwc/pci-exynos.c | 353 +++++++-----------
drivers/pci/quirks.c | 1 +
drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++---------
10 files changed, 489 insertions(+), 469 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
delete mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
--
2.17.1
From: Jaehoon Chung <[email protected]>
Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY
variant found in the Exynos5433 SoCs.
Signed-off-by: Jaehoon Chung <[email protected]>
[mszyprow: reworked the driver to support only Exynos5433 variant, rebased
onto current kernel code, rewrote commit message]
Signed-off-by: Marek Szyprowski <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Jingoo Han <[email protected]>
---
drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++++++----------------
1 file changed, 112 insertions(+), 192 deletions(-)
diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/phy-exynos-pcie.c
index 7e28b1aea0d1..d91de323dd0e 100644
--- a/drivers/phy/samsung/phy-exynos-pcie.c
+++ b/drivers/phy/samsung/phy-exynos-pcie.c
@@ -4,70 +4,41 @@
*
* Phy provider for PCIe controller on Exynos SoC series
*
- * Copyright (C) 2017 Samsung Electronics Co., Ltd.
+ * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
* Jaehoon Chung <[email protected]>
*/
-#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/iopoll.h>
-#include <linux/init.h>
#include <linux/mfd/syscon.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
#include <linux/regmap.h>
-/* PCIe Purple registers */
-#define PCIE_PHY_GLOBAL_RESET 0x000
-#define PCIE_PHY_COMMON_RESET 0x004
-#define PCIE_PHY_CMN_REG 0x008
-#define PCIE_PHY_MAC_RESET 0x00c
-#define PCIE_PHY_PLL_LOCKED 0x010
-#define PCIE_PHY_TRSVREG_RESET 0x020
-#define PCIE_PHY_TRSV_RESET 0x024
-
-/* PCIe PHY registers */
-#define PCIE_PHY_IMPEDANCE 0x004
-#define PCIE_PHY_PLL_DIV_0 0x008
-#define PCIE_PHY_PLL_BIAS 0x00c
-#define PCIE_PHY_DCC_FEEDBACK 0x014
-#define PCIE_PHY_PLL_DIV_1 0x05c
-#define PCIE_PHY_COMMON_POWER 0x064
-#define PCIE_PHY_COMMON_PD_CMN BIT(3)
-#define PCIE_PHY_TRSV0_EMP_LVL 0x084
-#define PCIE_PHY_TRSV0_DRV_LVL 0x088
-#define PCIE_PHY_TRSV0_RXCDR 0x0ac
-#define PCIE_PHY_TRSV0_POWER 0x0c4
-#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV0_LVCC 0x0dc
-#define PCIE_PHY_TRSV1_EMP_LVL 0x144
-#define PCIE_PHY_TRSV1_RXCDR 0x16c
-#define PCIE_PHY_TRSV1_POWER 0x184
-#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV1_LVCC 0x19c
-#define PCIE_PHY_TRSV2_EMP_LVL 0x204
-#define PCIE_PHY_TRSV2_RXCDR 0x22c
-#define PCIE_PHY_TRSV2_POWER 0x244
-#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV2_LVCC 0x25c
-#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
-#define PCIE_PHY_TRSV3_RXCDR 0x2ec
-#define PCIE_PHY_TRSV3_POWER 0x304
-#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV3_LVCC 0x31c
-
-struct exynos_pcie_phy_data {
- const struct phy_ops *ops;
-};
+#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
+
+/* Sysreg FSYS register offsets and bits for Exynos5433 */
+#define PCIE_EXYNOS5433_PHY_MAC_RESET 0x0208
+#define PCIE_MAC_RESET_MASK 0xFF
+#define PCIE_MAC_RESET BIT(4)
+#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0x1010
+#define PCIE_REFCLK_GATING_EN BIT(0)
+#define PCIE_EXYNOS5433_PHY_COMMON_RESET 0x1020
+#define PCIE_PHY_RESET BIT(0)
+#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0x1040
+#define PCIE_GLOBAL_RESET BIT(0)
+#define PCIE_REFCLK BIT(1)
+#define PCIE_REFCLK_MASK 0x16
+#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5)
+
+/* PMU PCIE PHY isolation control */
+#define EXYNOS5433_PMU_PCIE_PHY_OFFSET 0x730
/* For Exynos pcie phy */
struct exynos_pcie_phy {
- const struct exynos_pcie_phy_data *drv_data;
- void __iomem *phy_base;
- void __iomem *blk_base; /* For exynos5440 */
+ void __iomem *base;
+ struct regmap *pmureg;
+ struct regmap *fsysreg;
};
static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
@@ -75,153 +46,103 @@ static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
writel(val, base + offset);
}
-static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
-{
- return readl(base + offset);
-}
-
-/* For Exynos5440 specific functions */
-static int exynos5440_pcie_phy_init(struct phy *phy)
+/* Exynos5433 specific functions */
+static int exynos5433_pcie_phy_init(struct phy *phy)
{
struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
- /* DCC feedback control off */
- exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
-
- /* set TX/RX impedance */
- exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
-
- /* set 50Mhz PHY clock */
- exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
- exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
-
- /* set TX Differential output for lane 0 */
- exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
-
- /* set TX Pre-emphasis Level Control for lane 0 to minimum */
- exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
-
- /* set RX clock and data recovery bandwidth */
- exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
- exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
- exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
- exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
- exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
-
- /* change TX Pre-emphasis Level Control for lanes */
- exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
- exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
- exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
- exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
-
- /* set LVCC */
- exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
- exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
- exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
- exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
-
- /* pulse for common reset */
- exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
- udelay(500);
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
-
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET,
+ PCIE_PHY_RESET, 1);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET,
+ PCIE_MAC_RESET, 0);
+
+ /* PHY refclk 24MHz */
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
+ PCIE_REFCLK_MASK, PCIE_REFCLK);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
+ PCIE_GLOBAL_RESET, 0);
+
+
+ exynos_pcie_phy_writel(ep->base, 0x11, PCIE_PHY_OFFSET(0x3));
+
+ /* band gap reference on */
+ exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x20));
+ exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x4b));
+
+ /* jitter tunning */
+ exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x4));
+ exynos_pcie_phy_writel(ep->base, 0x02, PCIE_PHY_OFFSET(0x7));
+ exynos_pcie_phy_writel(ep->base, 0x41, PCIE_PHY_OFFSET(0x21));
+ exynos_pcie_phy_writel(ep->base, 0x7F, PCIE_PHY_OFFSET(0x14));
+ exynos_pcie_phy_writel(ep->base, 0xC0, PCIE_PHY_OFFSET(0x15));
+ exynos_pcie_phy_writel(ep->base, 0x61, PCIE_PHY_OFFSET(0x36));
+
+ /* D0 uninit.. */
+ exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x3D));
+
+ /* 24MHz */
+ exynos_pcie_phy_writel(ep->base, 0x94, PCIE_PHY_OFFSET(0x8));
+ exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x9));
+ exynos_pcie_phy_writel(ep->base, 0x93, PCIE_PHY_OFFSET(0xA));
+ exynos_pcie_phy_writel(ep->base, 0x6B, PCIE_PHY_OFFSET(0xC));
+ exynos_pcie_phy_writel(ep->base, 0xA5, PCIE_PHY_OFFSET(0xF));
+ exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x16));
+ exynos_pcie_phy_writel(ep->base, 0xA3, PCIE_PHY_OFFSET(0x17));
+ exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x1A));
+ exynos_pcie_phy_writel(ep->base, 0x71, PCIE_PHY_OFFSET(0x23));
+ exynos_pcie_phy_writel(ep->base, 0x4C, PCIE_PHY_OFFSET(0x24));
+
+ exynos_pcie_phy_writel(ep->base, 0x0E, PCIE_PHY_OFFSET(0x26));
+ exynos_pcie_phy_writel(ep->base, 0x14, PCIE_PHY_OFFSET(0x7));
+ exynos_pcie_phy_writel(ep->base, 0x48, PCIE_PHY_OFFSET(0x43));
+ exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x44));
+ exynos_pcie_phy_writel(ep->base, 0x03, PCIE_PHY_OFFSET(0x45));
+ exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x48));
+ exynos_pcie_phy_writel(ep->base, 0x13, PCIE_PHY_OFFSET(0x54));
+ exynos_pcie_phy_writel(ep->base, 0x04, PCIE_PHY_OFFSET(0x31));
+ exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x32));
+
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET,
+ PCIE_PHY_RESET, 0);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET,
+ PCIE_MAC_RESET_MASK, PCIE_MAC_RESET);
return 0;
}
-static int exynos5440_pcie_phy_power_on(struct phy *phy)
+static int exynos5433_pcie_phy_power_on(struct phy *phy)
{
struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
- u32 val;
-
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
- val &= ~PCIE_PHY_COMMON_PD_CMN;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
- val &= ~PCIE_PHY_TRSV0_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
- val &= ~PCIE_PHY_TRSV1_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
- val &= ~PCIE_PHY_TRSV2_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
- val &= ~PCIE_PHY_TRSV3_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
+ regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,
+ BIT(0), 1);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
+ PCIE_APP_REQ_EXIT_L1_MODE, 0);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,
+ PCIE_REFCLK_GATING_EN, 0);
return 0;
}
-static int exynos5440_pcie_phy_power_off(struct phy *phy)
+static int exynos5433_pcie_phy_power_off(struct phy *phy)
{
struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
- u32 val;
-
- if (readl_poll_timeout(ep->phy_base + PCIE_PHY_PLL_LOCKED, val,
- (val != 0), 1, 500)) {
- dev_err(&phy->dev, "PLL Locked: 0x%x\n", val);
- return -ETIMEDOUT;
- }
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
- val |= PCIE_PHY_COMMON_PD_CMN;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
- val |= PCIE_PHY_TRSV0_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
- val |= PCIE_PHY_TRSV1_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
- val |= PCIE_PHY_TRSV2_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
- val |= PCIE_PHY_TRSV3_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,
+ PCIE_REFCLK_GATING_EN, PCIE_REFCLK_GATING_EN);
+ regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,
+ BIT(0), 0);
return 0;
}
-static int exynos5440_pcie_phy_reset(struct phy *phy)
-{
- struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
-
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
- exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
-
- return 0;
-}
-
-static const struct phy_ops exynos5440_phy_ops = {
- .init = exynos5440_pcie_phy_init,
- .power_on = exynos5440_pcie_phy_power_on,
- .power_off = exynos5440_pcie_phy_power_off,
- .reset = exynos5440_pcie_phy_reset,
+static const struct phy_ops exynos5433_phy_ops = {
+ .init = exynos5433_pcie_phy_init,
+ .power_on = exynos5433_pcie_phy_power_on,
+ .power_off = exynos5433_pcie_phy_power_off,
.owner = THIS_MODULE,
};
-static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
- .ops = &exynos5440_phy_ops,
-};
-
static const struct of_device_id exynos_pcie_phy_match[] = {
{
- .compatible = "samsung,exynos5440-pcie-phy",
- .data = &exynos5440_pcie_phy_data,
+ .compatible = "samsung,exynos5433-pcie-phy",
},
{},
};
@@ -232,30 +153,30 @@ static int exynos_pcie_phy_probe(struct platform_device *pdev)
struct exynos_pcie_phy *exynos_phy;
struct phy *generic_phy;
struct phy_provider *phy_provider;
- struct resource *res;
- const struct exynos_pcie_phy_data *drv_data;
-
- drv_data = of_device_get_match_data(dev);
- if (!drv_data)
- return -ENODEV;
exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
if (!exynos_phy)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- exynos_phy->phy_base = devm_ioremap_resource(dev, res);
- if (IS_ERR(exynos_phy->phy_base))
- return PTR_ERR(exynos_phy->phy_base);
+ exynos_phy->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(exynos_phy->base))
+ return PTR_ERR(exynos_phy->base);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- exynos_phy->blk_base = devm_ioremap_resource(dev, res);
- if (IS_ERR(exynos_phy->blk_base))
- return PTR_ERR(exynos_phy->blk_base);
+ exynos_phy->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "samsung,pmu-syscon");
+ if (IS_ERR(exynos_phy->pmureg)) {
+ dev_err(&pdev->dev, "PMU regmap lookup failed.\n");
+ return PTR_ERR(exynos_phy->pmureg);
+ }
- exynos_phy->drv_data = drv_data;
+ exynos_phy->fsysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "samsung,fsys-sysreg");
+ if (IS_ERR(exynos_phy->fsysreg)) {
+ dev_err(&pdev->dev, "FSYS sysreg regmap lookup failed.\n");
+ return PTR_ERR(exynos_phy->fsysreg);
+ }
- generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
+ generic_phy = devm_phy_create(dev, dev->of_node, &exynos5433_phy_ops);
if (IS_ERR(generic_phy)) {
dev_err(dev, "failed to create PHY\n");
return PTR_ERR(generic_phy);
@@ -275,5 +196,4 @@ static struct platform_driver exynos_pcie_phy_driver = {
.suppress_bind_attrs = true,
}
};
-
builtin_platform_driver(exynos_pcie_phy_driver);
--
2.17.1
From: Jaehoon Chung <[email protected]>
Add the nodes relevant to PCIe PHY and PCIe support. PCIe is used for the
WiFi interface (Broadcom Limited BCM4358 802.11ac Wireless LAN SoC).
Signed-off-by: Jaehoon Chung <[email protected]>
[mszyprow: rewrote commit message, reworked board/generic dts/dtsi split]
Signed-off-by: Marek Szyprowski <[email protected]>
---
.../boot/dts/exynos/exynos5433-pinctrl.dtsi | 2 +-
.../dts/exynos/exynos5433-tm2-common.dtsi | 24 ++++++++++++-
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 36 +++++++++++++++++++
3 files changed, 60 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
index 9df7c65593a1..32a6518517e5 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
@@ -329,7 +329,7 @@
};
pcie_bus: pcie_bus {
- samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
+ samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6";
samsung,pin-function = <EXYNOS_PIN_FUNC_3>;
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index 97a2f0c7c0cf..5ec447f0cf5d 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -968,6 +968,25 @@
bus-width = <4>;
};
+&pcie {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_bus &pcie_wlanen>;
+ vdd10-supply = <&ldo6_reg>;
+ vdd18-supply = <&ldo7_reg>;
+ assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>,
+ <&cmu_top CLK_MOUT_SCLK_PCIE_100>;
+ assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
+ <&cmu_top CLK_MOUT_BUS_PLL_USER>;
+ assigned-clock-rates = <0>, <100000000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&pcie_phy {
+ status = "okay";
+};
+
&ppmu_d0_general {
status = "okay";
events {
@@ -1084,8 +1103,11 @@
pinctrl-names = "default";
pinctrl-0 = <&initial_ese>;
+ pcie_wlanen: pcie-wlanen {
+ PIN(INPUT, gpj2-0, UP, FAST_SR4);
+ };
+
initial_ese: initial-state {
- PIN(INPUT, gpj2-0, DOWN, FAST_SR1);
PIN(INPUT, gpj2-1, DOWN, FAST_SR1);
PIN(INPUT, gpj2-2, DOWN, FAST_SR1);
};
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 0a886bb6c806..1d2442ac432c 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -1029,6 +1029,11 @@
reg = <0x145f0000 0x1038>;
};
+ syscon_fsys: syscon@156f0000 {
+ compatible = "syscon";
+ reg = <0x156f0000 0x1044>;
+ };
+
gsc_0: video-scaler@13c00000 {
compatible = "samsung,exynos5433-gsc";
reg = <0x13c00000 0x1000>;
@@ -1830,6 +1835,37 @@
status = "disabled";
};
};
+
+ pcie_phy: pcie-phy@15680000 {
+ compatible = "samsung,exynos5433-pcie-phy";
+ reg = <0x15680000 0x1000>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ samsung,fsys-sysreg = <&syscon_fsys>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ pcie: pcie@15700000 {
+ compatible = "samsung,exynos5433-pcie";
+ reg = <0x15700000 0x1000>, <0x156b0000 0x1000>,
+ <0x0c000000 0x1000>;
+ reg-names = "dbi", "elbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_fsys CLK_PCIE>,
+ <&cmu_fsys CLK_PCLK_PCIE_PHY>;
+ clock-names = "pcie", "pcie_bus";
+ num-lanes = <1>;
+ num-viewport = <3>;
+ bus-range = <0x00 0xff>;
+ phys = <&pcie_phy>;
+ ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
+ <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
+ status = "disabled";
+ };
};
timer: timer {
--
2.17.1
Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
variant). Based on the text dt-binding posted by Jaehoon Chung.
Signed-off-by: Marek Szyprowski <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/pci/samsung,exynos-pcie.yaml | 119 ++++++++++++++++++
1 file changed, 119 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
new file mode 100644
index 000000000000..1810bf722350
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series PCIe Host Controller Device Tree Bindings
+
+maintainers:
+ - Marek Szyprowski <[email protected]>
+ - Jaehoon Chung <[email protected]>
+
+description: |+
+ Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
+ PCIe IP and thus inherits all the common properties defined in
+ designware-pcie.txt.
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ const: samsung,exynos5433-pcie
+
+ reg:
+ items:
+ - description: Data Bus Interface (DBI) registers.
+ - description: External Local Bus interface (ELBI) registers.
+ - description: PCIe configuration space region.
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: elbi
+ - const: config
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: PCIe bridge clock
+ - description: PCIe bus clock
+
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+
+ phys:
+ maxItems: 1
+
+ vdd10-supply:
+ description:
+ Phandle to a regulator that provides 1.0V power to the PCIe block.
+
+ vdd18-supply:
+ description:
+ Phandle to a regulator that provides 1.8V power to the PCIe block.
+
+ num-lanes:
+ const: 1
+
+ num-viewport:
+ const: 3
+
+required:
+ - reg
+ - reg-names
+ - interrupts
+ - "#address-cells"
+ - "#size-cells"
+ - "#interrupt-cells"
+ - interrupt-map
+ - interrupt-map-mask
+ - ranges
+ - bus-range
+ - device_type
+ - num-lanes
+ - num-viewport
+ - clocks
+ - clock-names
+ - phys
+ - vdd10-supply
+ - vdd18-supply
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/exynos5433.h>
+
+ pcie: pcie@15700000 {
+ compatible = "samsung,exynos5433-pcie";
+ reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>;
+ reg-names = "dbi", "elbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
+ clock-names = "pcie", "pcie_bus";
+ phys = <&pcie_phy>;
+ pinctrl-0 = <&pcie_bus &pcie_wlanen>;
+ pinctrl-names = "default";
+ num-lanes = <1>;
+ num-viewport = <3>;
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
+ <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
+ vdd10-supply = <&ldo6_reg>;
+ vdd18-supply = <&ldo7_reg>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...
--
2.17.1
Add dt-bindings for the Samsung Exynos PCIe PHY controller (Exynos5433
variant). Based on the text dt-binding posted by Jaehoon Chung.
Signed-off-by: Marek Szyprowski <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/phy/samsung,exynos-pcie-phy.yaml | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
new file mode 100644
index 000000000000..ac0af40be52d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung SoC series PCIe PHY Device Tree Bindings
+
+maintainers:
+ - Marek Szyprowski <[email protected]>
+ - Jaehoon Chung <[email protected]>
+
+properties:
+ "#phy-cells":
+ const: 0
+
+ compatible:
+ const: samsung,exynos5433-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ samsung,pmu-syscon:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle for PMU system controller interface, used to
+ control PMU registers bits for PCIe PHY
+
+ samsung,fsys-sysreg:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: phandle for FSYS sysreg interface, used to control
+ sysreg registers bits for PCIe PHY
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - samsung,pmu-syscon
+ - samsung,fsys-sysreg
+
+additionalProperties: false
+
+examples:
+ - |
+ pcie_phy: pcie-phy@15680000 {
+ compatible = "samsung,exynos5433-pcie-phy";
+ reg = <0x15680000 0x1000>;
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ samsung,fsys-sysreg = <&syscon_fsys>;
+ #phy-cells = <0>;
+ };
+...
--
2.17.1
On Thu, Oct 29, 2020 at 02:40:11PM +0100, Marek Szyprowski wrote:
> Dear All,
>
> This patchset is a resurrection of the DW PCIe support for the Exynos5433
> SoCs posted long time ago here: https://lkml.org/lkml/2016/12/26/6 and
> later here: https://lkml.org/lkml/2017/12/21/296 .
>
> In meantime the support for the Exynos5440 SoCs has been completely
> dropped from mainline kernel, as those SoCs never reached the market. The
> PCIe driver for Exynos5440 variant however has not been removed yet. This
> patchset simply reworks it to support the Exynos5433 variant. The lack of
> the need to support both variants significantly simplifies the driver
> code.
>
> This patchset is based on the following branch:
> git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git pci-more-dwc-cleanup
>
> Best regards,
> Marek Szyprowski
>
>
> Changelog:
>
> v3:
> - rebased onto "[00/13] PCI: dwc: Another round of clean-ups" patchset:
> https://patchwork.kernel.org/project/linux-samsung-soc/cover/[email protected]/
> - fixed issues pointed by Rob in the driver logic:
> * removed DBI_RO_WR_EN register poking
> * made driver a standard module
> - fixed section mismatch issue
> - added "num-viewport = <3>" property to dts and bindings to fix warning
>
> v2: https://lore.kernel.org/linux-samsung-soc/[email protected]/
> - fixed issues in dt-bindings pointed by Krzysztof and Rob
>
> v1: https://lore.kernel.org/linux-samsung-soc/[email protected]/
> - initial version of this resurrected patchset
>
>
> Patch summary:
Please follow the subject line convention:
PCI: exynos: Rework to support Exynos5433 variant
arm64: dts: exynos: Add WiFi/PCIe support to TM2(e) boards
dt-bindings: PCI: exynos: Drop samsung,exynos5440-pcie binding
dt-bindings: PCI: exynos: Add samsung,exynos-pcie binding
dt-bindings: phy: exynos: Add samsung,exynos-pcie-phy binding
You can save this trouble by running "git log --oneline" on the file
(or directory, for new files) and copying the style.
> Jaehoon Chung (3):
> phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433
> PCIe PHY
> pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant
> arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards
>
> Marek Szyprowski (3):
> dt-bindings: pci: drop samsung,exynos5440-pcie binding
> dt-bindings: pci: add the samsung,exynos-pcie binding
> dt-bindings: phy: add the samsung,exynos-pcie-phy binding
>
> .../bindings/pci/samsung,exynos-pcie.yaml | 119 ++++++
> .../bindings/pci/samsung,exynos5440-pcie.txt | 58 ---
> .../bindings/phy/samsung,exynos-pcie-phy.yaml | 51 +++
> .../boot/dts/exynos/exynos5433-pinctrl.dtsi | 2 +-
> .../dts/exynos/exynos5433-tm2-common.dtsi | 24 +-
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 36 ++
> drivers/pci/controller/dwc/Kconfig | 10 +-
> drivers/pci/controller/dwc/pci-exynos.c | 353 +++++++-----------
> drivers/pci/quirks.c | 1 +
> drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++---------
> 10 files changed, 489 insertions(+), 469 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
> delete mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
>
> --
> 2.17.1
>
On Thu, Oct 29, 2020 at 02:40:13PM +0100, Marek Szyprowski wrote:
> Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
> variant). Based on the text dt-binding posted by Jaehoon Chung.
>
> Signed-off-by: Marek Szyprowski <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/pci/samsung,exynos-pcie.yaml | 119 ++++++++++++++++++
> 1 file changed, 119 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
> new file mode 100644
> index 000000000000..1810bf722350
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
> @@ -0,0 +1,119 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung SoC series PCIe Host Controller Device Tree Bindings
> +
> +maintainers:
> + - Marek Szyprowski <[email protected]>
> + - Jaehoon Chung <[email protected]>
> +
> +description: |+
> + Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
> + PCIe IP and thus inherits all the common properties defined in
> + designware-pcie.txt.
> +
> +allOf:
> + - $ref: /schemas/pci/pci-bus.yaml#
> +
> +properties:
> + compatible:
> + const: samsung,exynos5433-pcie
> +
> + reg:
> + items:
> + - description: Data Bus Interface (DBI) registers.
> + - description: External Local Bus interface (ELBI) registers.
> + - description: PCIe configuration space region.
> +
> + reg-names:
> + items:
> + - const: dbi
> + - const: elbi
> + - const: config
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: PCIe bridge clock
> + - description: PCIe bus clock
> +
> + clock-names:
> + items:
> + - const: pcie
> + - const: pcie_bus
> +
> + phys:
> + maxItems: 1
> +
> + vdd10-supply:
> + description:
> + Phandle to a regulator that provides 1.0V power to the PCIe block.
> +
> + vdd18-supply:
> + description:
> + Phandle to a regulator that provides 1.8V power to the PCIe block.
> +
> + num-lanes:
> + const: 1
> +
> + num-viewport:
> + const: 3
I'm confused why you need this. This is only used with the iATU except
for keystone. Platforms like Exynos with their own child bus config
space accessors don't have an iATU.
BTW, for cases with an iATU, I'm working on making the number of
viewports runtime detected.
> +
> +required:
> + - reg
> + - reg-names
> + - interrupts
> + - "#address-cells"
> + - "#size-cells"
> + - "#interrupt-cells"
> + - interrupt-map
> + - interrupt-map-mask
> + - ranges
> + - bus-range
> + - device_type
> + - num-lanes
> + - num-viewport
> + - clocks
> + - clock-names
> + - phys
> + - vdd10-supply
> + - vdd18-supply
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/exynos5433.h>
> +
> + pcie: pcie@15700000 {
> + compatible = "samsung,exynos5433-pcie";
> + reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>;
> + reg-names = "dbi", "elbi", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + #interrupt-cells = <1>;
> + device_type = "pci";
> + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
> + clock-names = "pcie", "pcie_bus";
> + phys = <&pcie_phy>;
> + pinctrl-0 = <&pcie_bus &pcie_wlanen>;
> + pinctrl-names = "default";
> + num-lanes = <1>;
> + num-viewport = <3>;
> + bus-range = <0x00 0xff>;
> + ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
> + <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
> + vdd10-supply = <&ldo6_reg>;
> + vdd18-supply = <&ldo7_reg>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +...
> --
> 2.17.1
>
On Thu, 29 Oct 2020 14:40:14 +0100, Marek Szyprowski wrote:
> Add dt-bindings for the Samsung Exynos PCIe PHY controller (Exynos5433
> variant). Based on the text dt-binding posted by Jaehoon Chung.
>
> Signed-off-by: Marek Szyprowski <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/phy/samsung,exynos-pcie-phy.yaml | 51 +++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
>
Reviewed-by: Rob Herring <[email protected]>
Hi Rob,
On 04.11.2020 22:35, Rob Herring wrote:
> On Thu, Oct 29, 2020 at 02:40:13PM +0100, Marek Szyprowski wrote:
>> Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
>> variant). Based on the text dt-binding posted by Jaehoon Chung.
>>
>> Signed-off-by: Marek Szyprowski <[email protected]>
>> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>> ---
>> .../bindings/pci/samsung,exynos-pcie.yaml | 119 ++++++++++++++++++
>> 1 file changed, 119 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
>> ...
>> + num-viewport:
>> + const: 3
> I'm confused why you need this. This is only used with the iATU except
> for keystone. Platforms like Exynos with their own child bus config
> space accessors don't have an iATU.
Frankly I have no idea, I don't know much about the PCI internals. After
rebasing onto your latest DW PCI changes I've noticed a following
warning message:
exynos-pcie 15700000.pcie: Resources exceed number of ATU entries (2)
Here is a complete log:
# dmesg | grep pci
ehci-pci: EHCI PCI platform driver
ohci-pci: OHCI PCI platform driver
exynos-pcie 15700000.pcie: host bridge /soc@0/pcie@15700000 ranges:
exynos-pcie 15700000.pcie: IO 0x000c001000..0x000c010fff ->
0x0000000000
exynos-pcie 15700000.pcie: MEM 0x000c011000..0x000ffffffe ->
0x000c011000
exynos-pcie 15700000.pcie: Resources exceed number of ATU entries (2)
exynos-pcie 15700000.pcie: Link up
exynos-pcie 15700000.pcie: PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [bus 00-ff]
pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
pci_bus 0000:00: root bus resource [mem 0x0c011000-0x0ffffffe]
pci 0000:00:00.0: [144d:a5e3] type 01 class 0x060400
pci 0000:00:00.0: PME# supported from D0 D3hot D3cold
pci 0000:01:00.0: [14e4:43e9] type 00 class 0x028000
pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00007fff 64bit]
pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x003fffff 64bit]
pci 0000:01:00.0: supports D1 D2
pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
pci 0000:00:00.0: BAR 14: assigned [mem 0x0c200000-0x0c7fffff]
pci 0000:01:00.0: BAR 2: assigned [mem 0x0c400000-0x0c7fffff 64bit]
pci 0000:01:00.0: BAR 0: assigned [mem 0x0c200000-0x0c207fff 64bit]
pci 0000:00:00.0: PCI bridge to [bus 01-ff]
pci 0000:00:00.0: bridge window [mem 0x0c200000-0x0c7fffff]
pci 0000:00:00.0: MSI quirk detected; MSI disabled
pcieport 0000:00:00.0: PME: Signaling with IRQ 97
brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac4358-pcie for chip
BCM4358/1
When I've increased the numer of viewports it has gone.
If this is not the proper solution, I will removed it.
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
On Thu, Nov 5, 2020 at 2:33 AM Marek Szyprowski
<[email protected]> wrote:
>
> Hi Rob,
>
> On 04.11.2020 22:35, Rob Herring wrote:
> > On Thu, Oct 29, 2020 at 02:40:13PM +0100, Marek Szyprowski wrote:
> >> Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
> >> variant). Based on the text dt-binding posted by Jaehoon Chung.
> >>
> >> Signed-off-by: Marek Szyprowski <[email protected]>
> >> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> >> ---
> >> .../bindings/pci/samsung,exynos-pcie.yaml | 119 ++++++++++++++++++
> >> 1 file changed, 119 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
>
> >> ...
>
> >> + num-viewport:
> >> + const: 3
> > I'm confused why you need this. This is only used with the iATU except
> > for keystone. Platforms like Exynos with their own child bus config
> > space accessors don't have an iATU.
>
> Frankly I have no idea, I don't know much about the PCI internals.
Sorry, I was confused. It's fine.
Reviewed-by: Rob Herring <[email protected]>
Rob
On 11/5/20, 10:27 AM, Rob Herring wrote:
>
> On Thu, Nov 5, 2020 at 2:33 AM Marek Szyprowski
> <[email protected]> wrote:
> >
> > Hi Rob,
> >
> > On 04.11.2020 22:35, Rob Herring wrote:
> > > On Thu, Oct 29, 2020 at 02:40:13PM +0100, Marek Szyprowski wrote:
> > >> Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
> > >> variant). Based on the text dt-binding posted by Jaehoon Chung.
> > >>
> > >> Signed-off-by: Marek Szyprowski <[email protected]>
> > >> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> > >> ---
> > >> .../bindings/pci/samsung,exynos-pcie.yaml | 119 ++++++++++++++++++
> > >> 1 file changed, 119 insertions(+)
> > >> create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
> >
> > >> ...
> >
> > >> + num-viewport:
> > >> + const: 3
> > > I'm confused why you need this. This is only used with the iATU except
> > > for keystone. Platforms like Exynos with their own child bus config
> > > space accessors don't have an iATU.
> >
> > Frankly I have no idea, I don't know much about the PCI internals.
>
> Sorry, I was confused. It's fine.
I was confused, too. But, as far as I remember, I also think that viewpoint-related
setting was necessary for Exynos PCIe.
Thank you.
Best regards,
Jingoo Han
>
> Reviewed-by: Rob Herring <[email protected]>
>
> Rob
On Thu, Oct 29, 2020 at 02:40:17PM +0100, Marek Szyprowski wrote:
> From: Jaehoon Chung <[email protected]>
>
> Add the nodes relevant to PCIe PHY and PCIe support. PCIe is used for the
> WiFi interface (Broadcom Limited BCM4358 802.11ac Wireless LAN SoC).
>
> Signed-off-by: Jaehoon Chung <[email protected]>
> [mszyprow: rewrote commit message, reworked board/generic dts/dtsi split]
> Signed-off-by: Marek Szyprowski <[email protected]>
> ---
> .../boot/dts/exynos/exynos5433-pinctrl.dtsi | 2 +-
> .../dts/exynos/exynos5433-tm2-common.dtsi | 24 ++++++++++++-
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 36 +++++++++++++++++++
Thanks, applied.
Best regards,
Krzysztof