Dear All,
This patchset is a resurrection of the DW PCIe support for the Exynos5433
SoCs posted long time ago here: https://lkml.org/lkml/2016/12/26/6 and
later here: https://lkml.org/lkml/2017/12/21/296 .
In meantime the support for the Exynos5440 SoCs has been completely
dropped from mainline kernel, as those SoCs never reached the market. The
PCIe driver for Exynos5440 variant however has not been removed yet. This
patchset simply reworks it to support the Exynos5433 variant. The lack of
the need to support both variants significantly simplifies the driver
code.
Best regards,
Marek Szyprowski
v2:
- fixed issues in dt-bindings pointed by Krzysztof and Rob
v1: https://lore.kernel.org/linux-samsung-soc/[email protected]/
- initial version of this resurrected patchset
Patch summary:
Jaehoon Chung (3):
phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433
PCIe PHY
pci: dwc: pci-exynos: rework the driver to support Exynos5433 variant
arm64: dts: exynos: add the WiFi/PCIe support to TM2(e) boards
Marek Szyprowski (3):
dt-bindings: pci: drop samsung,exynos5440-pcie binding
dt-bindings: pci: add the samsung,exynos-pcie binding
dt-bindings: phy: add the samsung,exynos-pcie-phy binding
.../bindings/pci/samsung,exynos-pcie.yaml | 114 ++++++
.../bindings/pci/samsung,exynos5440-pcie.txt | 58 ---
.../bindings/phy/samsung,exynos-pcie-phy.yaml | 51 +++
.../boot/dts/exynos/exynos5433-pinctrl.dtsi | 2 +-
.../dts/exynos/exynos5433-tm2-common.dtsi | 24 +-
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 35 ++
drivers/pci/controller/dwc/Kconfig | 3 +-
drivers/pci/controller/dwc/pci-exynos.c | 358 +++++++-----------
drivers/pci/quirks.c | 1 +
drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++---------
10 files changed, 481 insertions(+), 469 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml
delete mode 100644 Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml
--
2.17.1
From: Jaehoon Chung <[email protected]>
Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY
variant found in the Exynos5433 SoCs.
Signed-off-by: Jaehoon Chung <[email protected]>
[mszyprow: reworked the driver to support only Exynos5433 variant, rebased
onto current kernel code, rewrote commit message]
Signed-off-by: Marek Szyprowski <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++++++----------------
1 file changed, 112 insertions(+), 192 deletions(-)
diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/phy-exynos-pcie.c
index 7e28b1aea0d1..d91de323dd0e 100644
--- a/drivers/phy/samsung/phy-exynos-pcie.c
+++ b/drivers/phy/samsung/phy-exynos-pcie.c
@@ -4,70 +4,41 @@
*
* Phy provider for PCIe controller on Exynos SoC series
*
- * Copyright (C) 2017 Samsung Electronics Co., Ltd.
+ * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
* Jaehoon Chung <[email protected]>
*/
-#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/iopoll.h>
-#include <linux/init.h>
#include <linux/mfd/syscon.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/phy/phy.h>
#include <linux/regmap.h>
-/* PCIe Purple registers */
-#define PCIE_PHY_GLOBAL_RESET 0x000
-#define PCIE_PHY_COMMON_RESET 0x004
-#define PCIE_PHY_CMN_REG 0x008
-#define PCIE_PHY_MAC_RESET 0x00c
-#define PCIE_PHY_PLL_LOCKED 0x010
-#define PCIE_PHY_TRSVREG_RESET 0x020
-#define PCIE_PHY_TRSV_RESET 0x024
-
-/* PCIe PHY registers */
-#define PCIE_PHY_IMPEDANCE 0x004
-#define PCIE_PHY_PLL_DIV_0 0x008
-#define PCIE_PHY_PLL_BIAS 0x00c
-#define PCIE_PHY_DCC_FEEDBACK 0x014
-#define PCIE_PHY_PLL_DIV_1 0x05c
-#define PCIE_PHY_COMMON_POWER 0x064
-#define PCIE_PHY_COMMON_PD_CMN BIT(3)
-#define PCIE_PHY_TRSV0_EMP_LVL 0x084
-#define PCIE_PHY_TRSV0_DRV_LVL 0x088
-#define PCIE_PHY_TRSV0_RXCDR 0x0ac
-#define PCIE_PHY_TRSV0_POWER 0x0c4
-#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV0_LVCC 0x0dc
-#define PCIE_PHY_TRSV1_EMP_LVL 0x144
-#define PCIE_PHY_TRSV1_RXCDR 0x16c
-#define PCIE_PHY_TRSV1_POWER 0x184
-#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV1_LVCC 0x19c
-#define PCIE_PHY_TRSV2_EMP_LVL 0x204
-#define PCIE_PHY_TRSV2_RXCDR 0x22c
-#define PCIE_PHY_TRSV2_POWER 0x244
-#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV2_LVCC 0x25c
-#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
-#define PCIE_PHY_TRSV3_RXCDR 0x2ec
-#define PCIE_PHY_TRSV3_POWER 0x304
-#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV3_LVCC 0x31c
-
-struct exynos_pcie_phy_data {
- const struct phy_ops *ops;
-};
+#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
+
+/* Sysreg FSYS register offsets and bits for Exynos5433 */
+#define PCIE_EXYNOS5433_PHY_MAC_RESET 0x0208
+#define PCIE_MAC_RESET_MASK 0xFF
+#define PCIE_MAC_RESET BIT(4)
+#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0x1010
+#define PCIE_REFCLK_GATING_EN BIT(0)
+#define PCIE_EXYNOS5433_PHY_COMMON_RESET 0x1020
+#define PCIE_PHY_RESET BIT(0)
+#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0x1040
+#define PCIE_GLOBAL_RESET BIT(0)
+#define PCIE_REFCLK BIT(1)
+#define PCIE_REFCLK_MASK 0x16
+#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5)
+
+/* PMU PCIE PHY isolation control */
+#define EXYNOS5433_PMU_PCIE_PHY_OFFSET 0x730
/* For Exynos pcie phy */
struct exynos_pcie_phy {
- const struct exynos_pcie_phy_data *drv_data;
- void __iomem *phy_base;
- void __iomem *blk_base; /* For exynos5440 */
+ void __iomem *base;
+ struct regmap *pmureg;
+ struct regmap *fsysreg;
};
static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
@@ -75,153 +46,103 @@ static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
writel(val, base + offset);
}
-static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
-{
- return readl(base + offset);
-}
-
-/* For Exynos5440 specific functions */
-static int exynos5440_pcie_phy_init(struct phy *phy)
+/* Exynos5433 specific functions */
+static int exynos5433_pcie_phy_init(struct phy *phy)
{
struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
- /* DCC feedback control off */
- exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
-
- /* set TX/RX impedance */
- exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
-
- /* set 50Mhz PHY clock */
- exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
- exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
-
- /* set TX Differential output for lane 0 */
- exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
-
- /* set TX Pre-emphasis Level Control for lane 0 to minimum */
- exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
-
- /* set RX clock and data recovery bandwidth */
- exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
- exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
- exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
- exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
- exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
-
- /* change TX Pre-emphasis Level Control for lanes */
- exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
- exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
- exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
- exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
-
- /* set LVCC */
- exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
- exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
- exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
- exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
-
- /* pulse for common reset */
- exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
- udelay(500);
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
-
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET,
+ PCIE_PHY_RESET, 1);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET,
+ PCIE_MAC_RESET, 0);
+
+ /* PHY refclk 24MHz */
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
+ PCIE_REFCLK_MASK, PCIE_REFCLK);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
+ PCIE_GLOBAL_RESET, 0);
+
+
+ exynos_pcie_phy_writel(ep->base, 0x11, PCIE_PHY_OFFSET(0x3));
+
+ /* band gap reference on */
+ exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x20));
+ exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x4b));
+
+ /* jitter tunning */
+ exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x4));
+ exynos_pcie_phy_writel(ep->base, 0x02, PCIE_PHY_OFFSET(0x7));
+ exynos_pcie_phy_writel(ep->base, 0x41, PCIE_PHY_OFFSET(0x21));
+ exynos_pcie_phy_writel(ep->base, 0x7F, PCIE_PHY_OFFSET(0x14));
+ exynos_pcie_phy_writel(ep->base, 0xC0, PCIE_PHY_OFFSET(0x15));
+ exynos_pcie_phy_writel(ep->base, 0x61, PCIE_PHY_OFFSET(0x36));
+
+ /* D0 uninit.. */
+ exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x3D));
+
+ /* 24MHz */
+ exynos_pcie_phy_writel(ep->base, 0x94, PCIE_PHY_OFFSET(0x8));
+ exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x9));
+ exynos_pcie_phy_writel(ep->base, 0x93, PCIE_PHY_OFFSET(0xA));
+ exynos_pcie_phy_writel(ep->base, 0x6B, PCIE_PHY_OFFSET(0xC));
+ exynos_pcie_phy_writel(ep->base, 0xA5, PCIE_PHY_OFFSET(0xF));
+ exynos_pcie_phy_writel(ep->base, 0x34, PCIE_PHY_OFFSET(0x16));
+ exynos_pcie_phy_writel(ep->base, 0xA3, PCIE_PHY_OFFSET(0x17));
+ exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x1A));
+ exynos_pcie_phy_writel(ep->base, 0x71, PCIE_PHY_OFFSET(0x23));
+ exynos_pcie_phy_writel(ep->base, 0x4C, PCIE_PHY_OFFSET(0x24));
+
+ exynos_pcie_phy_writel(ep->base, 0x0E, PCIE_PHY_OFFSET(0x26));
+ exynos_pcie_phy_writel(ep->base, 0x14, PCIE_PHY_OFFSET(0x7));
+ exynos_pcie_phy_writel(ep->base, 0x48, PCIE_PHY_OFFSET(0x43));
+ exynos_pcie_phy_writel(ep->base, 0x44, PCIE_PHY_OFFSET(0x44));
+ exynos_pcie_phy_writel(ep->base, 0x03, PCIE_PHY_OFFSET(0x45));
+ exynos_pcie_phy_writel(ep->base, 0xA7, PCIE_PHY_OFFSET(0x48));
+ exynos_pcie_phy_writel(ep->base, 0x13, PCIE_PHY_OFFSET(0x54));
+ exynos_pcie_phy_writel(ep->base, 0x04, PCIE_PHY_OFFSET(0x31));
+ exynos_pcie_phy_writel(ep->base, 0, PCIE_PHY_OFFSET(0x32));
+
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_COMMON_RESET,
+ PCIE_PHY_RESET, 0);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_MAC_RESET,
+ PCIE_MAC_RESET_MASK, PCIE_MAC_RESET);
return 0;
}
-static int exynos5440_pcie_phy_power_on(struct phy *phy)
+static int exynos5433_pcie_phy_power_on(struct phy *phy)
{
struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
- u32 val;
-
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
- val &= ~PCIE_PHY_COMMON_PD_CMN;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
- val &= ~PCIE_PHY_TRSV0_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
- val &= ~PCIE_PHY_TRSV1_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
- val &= ~PCIE_PHY_TRSV2_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
- val &= ~PCIE_PHY_TRSV3_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
+ regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,
+ BIT(0), 1);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_GLOBAL_RESET,
+ PCIE_APP_REQ_EXIT_L1_MODE, 0);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,
+ PCIE_REFCLK_GATING_EN, 0);
return 0;
}
-static int exynos5440_pcie_phy_power_off(struct phy *phy)
+static int exynos5433_pcie_phy_power_off(struct phy *phy)
{
struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
- u32 val;
-
- if (readl_poll_timeout(ep->phy_base + PCIE_PHY_PLL_LOCKED, val,
- (val != 0), 1, 500)) {
- dev_err(&phy->dev, "PLL Locked: 0x%x\n", val);
- return -ETIMEDOUT;
- }
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
- val |= PCIE_PHY_COMMON_PD_CMN;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
- val |= PCIE_PHY_TRSV0_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
- val |= PCIE_PHY_TRSV1_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
- val |= PCIE_PHY_TRSV2_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
-
- val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
- val |= PCIE_PHY_TRSV3_PD_TSV;
- exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
+ regmap_update_bits(ep->fsysreg, PCIE_EXYNOS5433_PHY_L1SUB_CM_CON,
+ PCIE_REFCLK_GATING_EN, PCIE_REFCLK_GATING_EN);
+ regmap_update_bits(ep->pmureg, EXYNOS5433_PMU_PCIE_PHY_OFFSET,
+ BIT(0), 0);
return 0;
}
-static int exynos5440_pcie_phy_reset(struct phy *phy)
-{
- struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
-
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
- exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
- exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
-
- return 0;
-}
-
-static const struct phy_ops exynos5440_phy_ops = {
- .init = exynos5440_pcie_phy_init,
- .power_on = exynos5440_pcie_phy_power_on,
- .power_off = exynos5440_pcie_phy_power_off,
- .reset = exynos5440_pcie_phy_reset,
+static const struct phy_ops exynos5433_phy_ops = {
+ .init = exynos5433_pcie_phy_init,
+ .power_on = exynos5433_pcie_phy_power_on,
+ .power_off = exynos5433_pcie_phy_power_off,
.owner = THIS_MODULE,
};
-static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
- .ops = &exynos5440_phy_ops,
-};
-
static const struct of_device_id exynos_pcie_phy_match[] = {
{
- .compatible = "samsung,exynos5440-pcie-phy",
- .data = &exynos5440_pcie_phy_data,
+ .compatible = "samsung,exynos5433-pcie-phy",
},
{},
};
@@ -232,30 +153,30 @@ static int exynos_pcie_phy_probe(struct platform_device *pdev)
struct exynos_pcie_phy *exynos_phy;
struct phy *generic_phy;
struct phy_provider *phy_provider;
- struct resource *res;
- const struct exynos_pcie_phy_data *drv_data;
-
- drv_data = of_device_get_match_data(dev);
- if (!drv_data)
- return -ENODEV;
exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
if (!exynos_phy)
return -ENOMEM;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- exynos_phy->phy_base = devm_ioremap_resource(dev, res);
- if (IS_ERR(exynos_phy->phy_base))
- return PTR_ERR(exynos_phy->phy_base);
+ exynos_phy->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(exynos_phy->base))
+ return PTR_ERR(exynos_phy->base);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- exynos_phy->blk_base = devm_ioremap_resource(dev, res);
- if (IS_ERR(exynos_phy->blk_base))
- return PTR_ERR(exynos_phy->blk_base);
+ exynos_phy->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "samsung,pmu-syscon");
+ if (IS_ERR(exynos_phy->pmureg)) {
+ dev_err(&pdev->dev, "PMU regmap lookup failed.\n");
+ return PTR_ERR(exynos_phy->pmureg);
+ }
- exynos_phy->drv_data = drv_data;
+ exynos_phy->fsysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "samsung,fsys-sysreg");
+ if (IS_ERR(exynos_phy->fsysreg)) {
+ dev_err(&pdev->dev, "FSYS sysreg regmap lookup failed.\n");
+ return PTR_ERR(exynos_phy->fsysreg);
+ }
- generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
+ generic_phy = devm_phy_create(dev, dev->of_node, &exynos5433_phy_ops);
if (IS_ERR(generic_phy)) {
dev_err(dev, "failed to create PHY\n");
return PTR_ERR(generic_phy);
@@ -275,5 +196,4 @@ static struct platform_driver exynos_pcie_phy_driver = {
.suppress_bind_attrs = true,
}
};
-
builtin_platform_driver(exynos_pcie_phy_driver);
--
2.17.1
On 10/23/20, 3:59 AM, Marek Szyprowski wrote:
>
> From: Jaehoon Chung <[email protected]>
>
> Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
> dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY
> variant found in the Exynos5433 SoCs.
>
> Signed-off-by: Jaehoon Chung <[email protected]>
> [mszyprow: reworked the driver to support only Exynos5433 variant, rebased
> onto current kernel code, rewrote commit message]
> Signed-off-by: Marek Szyprowski <[email protected]>
> Acked-by: Krzysztof Kozlowski <[email protected]>
>
Reviewed-by: Jingoo Han <[email protected]>
Best regards,
Jingoo Han
> ---
> drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++++++----------------
> 1 file changed, 112 insertions(+), 192 deletions(-)
[.....]
On Fri, Oct 23, 2020 at 2:58 AM Marek Szyprowski
<[email protected]> wrote:
>
> From: Jaehoon Chung <[email protected]>
>
> Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
> dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY
> variant found in the Exynos5433 SoCs.
>
> Signed-off-by: Jaehoon Chung <[email protected]>
> [mszyprow: reworked the driver to support only Exynos5433 variant, rebased
> onto current kernel code, rewrote commit message]
> Signed-off-by: Marek Szyprowski <[email protected]>
> Acked-by: Krzysztof Kozlowski <[email protected]>
> ---
> drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++++++----------------
> 1 file changed, 112 insertions(+), 192 deletions(-)
>
> diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/phy-exynos-pcie.c
> index 7e28b1aea0d1..d91de323dd0e 100644
> --- a/drivers/phy/samsung/phy-exynos-pcie.c
> +++ b/drivers/phy/samsung/phy-exynos-pcie.c
> @@ -4,70 +4,41 @@
> *
> * Phy provider for PCIe controller on Exynos SoC series
> *
> - * Copyright (C) 2017 Samsung Electronics Co., Ltd.
> + * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
> * Jaehoon Chung <[email protected]>
> */
>
> -#include <linux/delay.h>
> #include <linux/io.h>
> -#include <linux/iopoll.h>
> -#include <linux/init.h>
> #include <linux/mfd/syscon.h>
> -#include <linux/of.h>
> -#include <linux/of_address.h>
> #include <linux/of_platform.h>
> #include <linux/platform_device.h>
> #include <linux/phy/phy.h>
> #include <linux/regmap.h>
>
> -/* PCIe Purple registers */
> -#define PCIE_PHY_GLOBAL_RESET 0x000
> -#define PCIE_PHY_COMMON_RESET 0x004
> -#define PCIE_PHY_CMN_REG 0x008
> -#define PCIE_PHY_MAC_RESET 0x00c
> -#define PCIE_PHY_PLL_LOCKED 0x010
> -#define PCIE_PHY_TRSVREG_RESET 0x020
> -#define PCIE_PHY_TRSV_RESET 0x024
> -
> -/* PCIe PHY registers */
> -#define PCIE_PHY_IMPEDANCE 0x004
> -#define PCIE_PHY_PLL_DIV_0 0x008
> -#define PCIE_PHY_PLL_BIAS 0x00c
> -#define PCIE_PHY_DCC_FEEDBACK 0x014
> -#define PCIE_PHY_PLL_DIV_1 0x05c
> -#define PCIE_PHY_COMMON_POWER 0x064
> -#define PCIE_PHY_COMMON_PD_CMN BIT(3)
> -#define PCIE_PHY_TRSV0_EMP_LVL 0x084
> -#define PCIE_PHY_TRSV0_DRV_LVL 0x088
> -#define PCIE_PHY_TRSV0_RXCDR 0x0ac
> -#define PCIE_PHY_TRSV0_POWER 0x0c4
> -#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
> -#define PCIE_PHY_TRSV0_LVCC 0x0dc
> -#define PCIE_PHY_TRSV1_EMP_LVL 0x144
> -#define PCIE_PHY_TRSV1_RXCDR 0x16c
> -#define PCIE_PHY_TRSV1_POWER 0x184
> -#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
> -#define PCIE_PHY_TRSV1_LVCC 0x19c
> -#define PCIE_PHY_TRSV2_EMP_LVL 0x204
> -#define PCIE_PHY_TRSV2_RXCDR 0x22c
> -#define PCIE_PHY_TRSV2_POWER 0x244
> -#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
> -#define PCIE_PHY_TRSV2_LVCC 0x25c
> -#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
> -#define PCIE_PHY_TRSV3_RXCDR 0x2ec
> -#define PCIE_PHY_TRSV3_POWER 0x304
> -#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
> -#define PCIE_PHY_TRSV3_LVCC 0x31c
> -
> -struct exynos_pcie_phy_data {
> - const struct phy_ops *ops;
> -};
> +#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
> +
> +/* Sysreg FSYS register offsets and bits for Exynos5433 */
> +#define PCIE_EXYNOS5433_PHY_MAC_RESET 0x0208
> +#define PCIE_MAC_RESET_MASK 0xFF
> +#define PCIE_MAC_RESET BIT(4)
> +#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0x1010
> +#define PCIE_REFCLK_GATING_EN BIT(0)
> +#define PCIE_EXYNOS5433_PHY_COMMON_RESET 0x1020
> +#define PCIE_PHY_RESET BIT(0)
> +#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0x1040
> +#define PCIE_GLOBAL_RESET BIT(0)
Resets, why is this block not a reset provider?
> +#define PCIE_REFCLK BIT(1)
> +#define PCIE_REFCLK_MASK 0x16
> +#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5)
Hi Rob,
On 26.10.2020 19:50, Rob Herring wrote:
> On Fri, Oct 23, 2020 at 2:58 AM Marek Szyprowski
> <[email protected]> wrote:
>> From: Jaehoon Chung <[email protected]>
>>
>> Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
>> dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY
>> variant found in the Exynos5433 SoCs.
>>
>> Signed-off-by: Jaehoon Chung <[email protected]>
>> [mszyprow: reworked the driver to support only Exynos5433 variant, rebased
>> onto current kernel code, rewrote commit message]
>> Signed-off-by: Marek Szyprowski <[email protected]>
>> Acked-by: Krzysztof Kozlowski <[email protected]>
>> ---
>> drivers/phy/samsung/phy-exynos-pcie.c | 304 ++++++++++----------------
>> 1 file changed, 112 insertions(+), 192 deletions(-)
>>
>> diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/phy-exynos-pcie.c
>> index 7e28b1aea0d1..d91de323dd0e 100644
>> --- a/drivers/phy/samsung/phy-exynos-pcie.c
>> +++ b/drivers/phy/samsung/phy-exynos-pcie.c
>> @@ -4,70 +4,41 @@
>> *
>> * Phy provider for PCIe controller on Exynos SoC series
>> *
>> - * Copyright (C) 2017 Samsung Electronics Co., Ltd.
>> + * Copyright (C) 2017-2020 Samsung Electronics Co., Ltd.
>> * Jaehoon Chung <[email protected]>
>> */
>>
>> -#include <linux/delay.h>
>> #include <linux/io.h>
>> -#include <linux/iopoll.h>
>> -#include <linux/init.h>
>> #include <linux/mfd/syscon.h>
>> -#include <linux/of.h>
>> -#include <linux/of_address.h>
>> #include <linux/of_platform.h>
>> #include <linux/platform_device.h>
>> #include <linux/phy/phy.h>
>> #include <linux/regmap.h>
>>
>> -/* PCIe Purple registers */
>> -#define PCIE_PHY_GLOBAL_RESET 0x000
>> -#define PCIE_PHY_COMMON_RESET 0x004
>> -#define PCIE_PHY_CMN_REG 0x008
>> -#define PCIE_PHY_MAC_RESET 0x00c
>> -#define PCIE_PHY_PLL_LOCKED 0x010
>> -#define PCIE_PHY_TRSVREG_RESET 0x020
>> -#define PCIE_PHY_TRSV_RESET 0x024
>> -
>> -/* PCIe PHY registers */
>> -#define PCIE_PHY_IMPEDANCE 0x004
>> -#define PCIE_PHY_PLL_DIV_0 0x008
>> -#define PCIE_PHY_PLL_BIAS 0x00c
>> -#define PCIE_PHY_DCC_FEEDBACK 0x014
>> -#define PCIE_PHY_PLL_DIV_1 0x05c
>> -#define PCIE_PHY_COMMON_POWER 0x064
>> -#define PCIE_PHY_COMMON_PD_CMN BIT(3)
>> -#define PCIE_PHY_TRSV0_EMP_LVL 0x084
>> -#define PCIE_PHY_TRSV0_DRV_LVL 0x088
>> -#define PCIE_PHY_TRSV0_RXCDR 0x0ac
>> -#define PCIE_PHY_TRSV0_POWER 0x0c4
>> -#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
>> -#define PCIE_PHY_TRSV0_LVCC 0x0dc
>> -#define PCIE_PHY_TRSV1_EMP_LVL 0x144
>> -#define PCIE_PHY_TRSV1_RXCDR 0x16c
>> -#define PCIE_PHY_TRSV1_POWER 0x184
>> -#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
>> -#define PCIE_PHY_TRSV1_LVCC 0x19c
>> -#define PCIE_PHY_TRSV2_EMP_LVL 0x204
>> -#define PCIE_PHY_TRSV2_RXCDR 0x22c
>> -#define PCIE_PHY_TRSV2_POWER 0x244
>> -#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
>> -#define PCIE_PHY_TRSV2_LVCC 0x25c
>> -#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
>> -#define PCIE_PHY_TRSV3_RXCDR 0x2ec
>> -#define PCIE_PHY_TRSV3_POWER 0x304
>> -#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
>> -#define PCIE_PHY_TRSV3_LVCC 0x31c
>> -
>> -struct exynos_pcie_phy_data {
>> - const struct phy_ops *ops;
>> -};
>> +#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
>> +
>> +/* Sysreg FSYS register offsets and bits for Exynos5433 */
>> +#define PCIE_EXYNOS5433_PHY_MAC_RESET 0x0208
>> +#define PCIE_MAC_RESET_MASK 0xFF
>> +#define PCIE_MAC_RESET BIT(4)
>> +#define PCIE_EXYNOS5433_PHY_L1SUB_CM_CON 0x1010
>> +#define PCIE_REFCLK_GATING_EN BIT(0)
>> +#define PCIE_EXYNOS5433_PHY_COMMON_RESET 0x1020
>> +#define PCIE_PHY_RESET BIT(0)
>> +#define PCIE_EXYNOS5433_PHY_GLOBAL_RESET 0x1040
>> +#define PCIE_GLOBAL_RESET BIT(0)
> Resets, why is this block not a reset provider?
Because most of those registers need to be configured together with the
rest of the PHY registers. IMHO there is no simple "do the reset" logic
there. There is also PHY reference clock configuration there. This phy
driver is already Exynos5433 specific and I see no point in extracting
separate reset driver from it. Other Exynos PHY drivers also access PMU
and SYSREG via the respective regmaps and don't use any kind of reset
drivers.
>> +#define PCIE_REFCLK BIT(1)
>> +#define PCIE_REFCLK_MASK 0x16
>> +#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5)
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland