Hi all,
Unlike on most other Renesas SoCs, the GPIO controller block on RZ/A1
SoCs lack interrupt functionality. While the GPIOs can be routed to the
GIC as pin interrupts, this is of limited use, as the PL390 GIC supports
rising edge and high-level interrupts only.
Fortunately RZ/A1 SoCs contain a small front-end for the GIC, allowing
to use up to 8 external interrupts, with configurable sense select.
Hence this patch series adds DT bindings and a driver for this
front-end, adds a device node for it in the RZ/A1H DTS, and uses it to
enable support for the 3 input switches on the Renesas RSK+RZA1
development board.
I expect this driver to be reusable for RZ/A2, after adding a match
entry with .gic_spi_base = 4.
- Should this information come from DT instead?
- Originally I had interrupts properties in DT to define the mapping
from external interrupts to GIC interrupts (cfr. "renesas,irqc",
which also calls request_irq()), but other similar drivers seem to
hardcode this information in the driver, so I went that route.
Dependencies:
- Patch 3 depends on patch 2,
- Patch 4 can be applied as soon as the DT bindings in patch 1 have
been accepted,
- Patch 5 depends on patch 4.
This has been tested on RSK+RZA1 with evtest and s2ram wake-up.
I have verified proper operation of low-level and rising/falling sense
select, too.
Thanks for your comments!
Geert Uytterhoeven (5):
dt-bindings: interrupt-controller: Add Renesas RZ/A1 Interrupt
Controller
irqchip: Add Renesas RZ/A1 Interrupt Controller driver
soc: renesas: Enable RZ/A1 IRQC on RZ/A1H
ARM: dts: r7s72100: Add IRQC device node
ARM: dts: rskrza1: Add input switches
.../renesas,rza1-irqc.txt | 27 ++
arch/arm/boot/dts/r7s72100-rskrza1.dts | 38 +++
arch/arm/boot/dts/r7s72100.dtsi | 8 +
drivers/irqchip/Kconfig | 4 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-renesas-rza1.c | 238 ++++++++++++++++++
drivers/soc/renesas/Kconfig | 1 +
7 files changed, 317 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
create mode 100644 drivers/irqchip/irq-renesas-rza1.c
--
2.17.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Enable support for the IRQC on RZ/A1H, which is a small front-end to the
GIC. This allows to use up to 8 external interrupts with configurable
sense select.
Signed-off-by: Geert Uytterhoeven <[email protected]>
---
arch/arm/boot/dts/r7s72100.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index 2211f88ede2ad351..27bc7789f5437ef1 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -670,6 +670,14 @@
status = "disabled";
};
+ irqc: interrupt-controller@fcfef800 {
+ compatible = "renesas,r7s72100-irqc",
+ "renesas,rza1-irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0xfcfef800 0x6>;
+ };
+
mtu2: timer@fcff0000 {
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
reg = <0xfcff0000 0x400>;
--
2.17.1
Add DT bindings for the Renesas RZ/A1 Interrupt Controller.
Signed-off-by: Geert Uytterhoeven <[email protected]>
---
.../renesas,rza1-irqc.txt | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
new file mode 100644
index 0000000000000000..0914d3d216c3bdac
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rza1-irqc.txt
@@ -0,0 +1,27 @@
+DT bindings for the Renesas RZ/A1 Interrupt Controller
+
+The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas
+RZ/A1 SoCs:
+ - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI
+ interrupts,
+ - NMI edge select.
+
+Required properties:
+ - compatible: Must be "renesas,<soctype>-irqc", and "renesas,rza1-irqc" as
+ fallback.
+ Examples with soctypes are:
+ - "renesas,r7s72100-irqc" (RZ/A1H)
+ - #interrupt-cells: Must be 2 (an interrupt index and flags, as defined
+ in interrupts.txt in this directory)
+ - interrupt-controller: Marks the device as an interrupt controller
+ - reg: Base address and length of the memory resource used by the interrupt
+ controller
+
+Example:
+
+ irqc: interrupt-controller@fcfef800 {
+ compatible = "renesas,r7s72100-irqc", "renesas,rza1-irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0xfcfef800 0x6>;
+ };
--
2.17.1
Auto-enable the RZ/A1 Interrupt Controller when configuring a kernel
with support for RZ/A1H SoCs.
This is similar to how interrupt controllers for other Renesas SoCs are
enabled.
Signed-off-by: Geert Uytterhoeven <[email protected]>
---
drivers/soc/renesas/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 68bfca6f20ddf8a7..1448b6dbcdb20bae 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -57,6 +57,7 @@ config ARCH_R7S72100
bool "RZ/A1H (R7S72100)"
select PM
select PM_GENERIC_DOMAINS
+ select RENESAS_RZA1_IRQC
select SYS_SUPPORTS_SH_MTU2
select RENESAS_OSTM
--
2.17.1
Add support for input switches SW1-3 on the Renesas RZ/A1 RSK+RZA1
development board.
Note that this uses the IRQ interrupts, as the RZ/A1 GPIO controller
does not include interrupt support.
Signed-off-by: Geert Uytterhoeven <[email protected]>
---
v2:
- Use rza1-irqc instead of gic.
---
arch/arm/boot/dts/r7s72100-rskrza1.dts | 38 ++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts
index ff24301dc1be54de..99acfe4fe11aaed9 100644
--- a/arch/arm/boot/dts/r7s72100-rskrza1.dts
+++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "r7s72100.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
/ {
@@ -28,6 +29,37 @@
reg = <0x08000000 0x02000000>;
};
+ keyboard {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&keyboard_pins>;
+
+ key-1 {
+ interrupt-parent = <&irqc>;
+ interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_1>;
+ label = "SW1";
+ wakeup-source;
+ };
+
+ key-2 {
+ interrupt-parent = <&irqc>;
+ interrupts = <2 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_2>;
+ label = "SW2";
+ wakeup-source;
+ };
+
+ key-3 {
+ interrupt-parent = <&irqc>;
+ interrupts = <5 IRQ_TYPE_EDGE_BOTH>;
+ linux,code = <KEY_3>;
+ label = "SW3";
+ wakeup-source;
+ };
+ };
+
lbsc {
#address-cells = <1>;
#size-cells = <1>;
@@ -101,6 +133,12 @@
<RZA1_PINMUX(1, 7, 1)>; /* RIIC3SDA */
};
+ keyboard_pins: keyboard {
+ pinmux = <RZA1_PINMUX(1, 9, 3)>, /* IRQ3 */
+ <RZA1_PINMUX(1, 8, 3)>, /* IRQ2 */
+ <RZA1_PINMUX(1, 11, 3)>; /* IRQ5 */
+ };
+
/* Serial Console */
scif2_pins: serial2 {
pinmux = <RZA1_PINMUX(3, 0, 6)>, /* TxD2 */
--
2.17.1
Hi Geert,
Thanks for this patch!
I've been hacking this support into the standard GIC driver in our BSPs
for years now. :o
On Mon, Apr 29, 2019, Geert Uytterhoeven wrote:
> I expect this driver to be reusable for RZ/A2, after adding a match
> entry with .gic_spi_base = 4.
Yes, the same IP block is in RZ/A2.
So with that said, should we call this driver irq-renesas-rza1.c or just
irq-renesas-rza.c?
It doesn't really matter to me.
For an RZ/A3, we might just use the same IP again.
Side note, I've seen this interrupt pin HW in some older SH4A devices
(like SH7724 and SH7757). So it's been around for a while.
Chris
Hi Chris,
On Mon, Apr 29, 2019 at 2:21 PM Chris Brandt <[email protected]> wrote:
> I've been hacking this support into the standard GIC driver in our BSPs
> for years now. :o
Yeah, and having that patch in your tree breaks all other GICs, as
I found out the hard way ;-)
> On Mon, Apr 29, 2019, Geert Uytterhoeven wrote:
> > I expect this driver to be reusable for RZ/A2, after adding a match
> > entry with .gic_spi_base = 4.
>
> Yes, the same IP block is in RZ/A2.
>
> So with that said, should we call this driver irq-renesas-rza1.c or just
> irq-renesas-rza.c?
> It doesn't really matter to me.
> For an RZ/A3, we might just use the same IP again.
I've learned to be reluctant to put too many wildcards in names, as it may
start to bite in the future. For driver names, it's not that bad (they can
be changed), but for DT, it's a no-go.
So for RZ/A2, I think it's best to use
compatible = "renesas,r7s9210-irqc", "renesas,rza1-irqc";
renesas,gic-spi-base = <4>;
(adding "renesas,gic-spi-base = <0>" to r7s72100.dtsi as I speak).
> Side note, I've seen this interrupt pin HW in some older SH4A devices
> (like SH7724 and SH7757). So it's been around for a while.
Right:
arch/sh/kernel/cpu/sh4a/setup-sh7343.c: { 0xa4140024, 0, 8, /* INTREQ00 */
arch/sh/kernel/cpu/sh4a/setup-sh7366.c: { 0xa4140024, 0, 8, /* INTREQ00 */
arch/sh/kernel/cpu/sh4a/setup-sh7722.c: { 0xa4140024, 0, 8, /* INTREQ00 */
arch/sh/kernel/cpu/sh4a/setup-sh7723.c: { 0xa4140024, 0, 8, /* INTREQ00 */
arch/sh/kernel/cpu/sh4a/setup-sh7724.c: { 0xa4140024, 0, 8, /* INTREQ00 */
However, according to the sh7724 documentation, the register set is
slightly different, as is its sense configuration (no support for both
edges, but support for high-level interrupts).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Mon, Apr 29, 2019 at 11:36:29AM +0200, Geert Uytterhoeven wrote:
> Auto-enable the RZ/A1 Interrupt Controller when configuring a kernel
> with support for RZ/A1H SoCs.
>
> This is similar to how interrupt controllers for other Renesas SoCs are
> enabled.
>
> Signed-off-by: Geert Uytterhoeven <[email protected]>
Thanks Geert,
this is fine by me but other parts of the series need respinning.
Reviewed-by: Simon Horman <[email protected]>
> ---
> drivers/soc/renesas/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
> index 68bfca6f20ddf8a7..1448b6dbcdb20bae 100644
> --- a/drivers/soc/renesas/Kconfig
> +++ b/drivers/soc/renesas/Kconfig
> @@ -57,6 +57,7 @@ config ARCH_R7S72100
> bool "RZ/A1H (R7S72100)"
> select PM
> select PM_GENERIC_DOMAINS
> + select RENESAS_RZA1_IRQC
> select SYS_SUPPORTS_SH_MTU2
> select RENESAS_OSTM
>
> --
> 2.17.1
>
On Mon, Apr 29, 2019 at 11:36:30AM +0200, Geert Uytterhoeven wrote:
> Enable support for the IRQC on RZ/A1H, which is a small front-end to the
> GIC. This allows to use up to 8 external interrupts with configurable
> sense select.
>
> Signed-off-by: Geert Uytterhoeven <[email protected]>
Thanks Geert,
this is fine by me but other parts of the series need respinning.
Reviewed-by: Simon Horman <[email protected]>
Hi Geert,
On Mon, Apr 29, 2019, Geert Uytterhoeven wrote:
> On Mon, Apr 29, 2019 at 2:21 PM Chris Brandt <[email protected]>
> wrote:
> > I've been hacking this support into the standard GIC driver in our BSPs
> > for years now. :o
>
> Yeah, and having that patch in your tree breaks all other GICs, as
> I found out the hard way ;-)
I never said it was a good hack :)
> So for RZ/A2, I think it's best to use
>
> compatible = "renesas,r7s9210-irqc", "renesas,rza1-irqc";
> renesas,gic-spi-base = <4>;
That seems to make sense. It's specific to r7s9210 (RZ/A2), but
compatible with the original version which was for rza1. It explains the
history.
> > Side note, I've seen this interrupt pin HW in some older SH4A devices
> > (like SH7724 and SH7757). So it's been around for a while.
>
> Right:
>
> arch/sh/kernel/cpu/sh4a/setup-sh7343.c: { 0xa4140024, 0, 8, /*
> INTREQ00 */
> arch/sh/kernel/cpu/sh4a/setup-sh7366.c: { 0xa4140024, 0, 8, /*
> INTREQ00 */
> arch/sh/kernel/cpu/sh4a/setup-sh7722.c: { 0xa4140024, 0, 8, /*
> INTREQ00 */
> arch/sh/kernel/cpu/sh4a/setup-sh7723.c: { 0xa4140024, 0, 8, /*
> INTREQ00 */
> arch/sh/kernel/cpu/sh4a/setup-sh7724.c: { 0xa4140024, 0, 8, /*
> INTREQ00 */
>
> However, according to the sh7724 documentation, the register set is
> slightly different, as is its sense configuration (no support for both
> edges, but support for high-level interrupts).
If I remember correctly, I think the design engineers can choose the
sense as they wire it up internally. The ones in the SH7757 were chosen
based on a specific use case. So far, the ones chosen for the RZ/A1 seem to
make everyone happy, so I assume we'll keep them that way.
Chris