2019-10-19 08:23:05

by Rasmus Villemoes

Subject: [PATCH 0/7] towards QE support on ARM

There have been several attempts in the past few years to allow
building the QUICC engine drivers for platforms other than PPC. This
is (the beginning of) yet another attempt. I hope I can get someone to
pick up these relatively trivial patches (I _think_ they shouldn't
change functionality at all), and then I'll continue slowly working
towards removing the PPC32 dependency for CONFIG_QUICC_ENGINE.

Tested on an MPC8309-derived board.

Rasmus Villemoes (7):
soc: fsl: qe: remove space-before-tab
soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs
soc: fsl: qe: avoid ppc-specific io accessors
soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic
serial: make SERIAL_QE depend on PPC32
serial: ucc_uart.c: explicitly include asm/cpm.h
soc/fsl/qe/qe.h: remove include of asm/cpm.h

drivers/soc/fsl/qe/gpio.c | 30 ++++++++--------
drivers/soc/fsl/qe/qe.c | 44 +++++++++++------------
drivers/soc/fsl/qe/qe_ic.c | 8 ++---
drivers/soc/fsl/qe/qe_ic.h | 2 +-
drivers/soc/fsl/qe/qe_io.c | 40 ++++++++++-----------
drivers/soc/fsl/qe/qe_tdm.c | 8 ++---
drivers/soc/fsl/qe/ucc.c | 12 +++----
drivers/soc/fsl/qe/ucc_fast.c | 66 ++++++++++++++++++-----------------
drivers/soc/fsl/qe/ucc_slow.c | 38 ++++++++++----------
drivers/soc/fsl/qe/usb.c | 2 +-
drivers/tty/serial/Kconfig | 1 +
drivers/tty/serial/ucc_uart.c | 1 +
include/soc/fsl/qe/qe.h | 1 -
13 files changed, 126 insertions(+), 127 deletions(-)

--
2.20.1

2019-10-19 08:23:21

by Rasmus Villemoes

Subject: [PATCH 4/7] soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic

In preparation for allowing QE to be built for architectures other
than ppc, use the generic readx_poll_timeout_atomic() helper from
iopoll.h rather than the ppc-only spin_event_timeout().

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 60bf047001be..d18b25a685ca 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -22,6 +22,7 @@
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/ioport.h>
+#include <linux/iopoll.h>
#include <linux/crc32.h>
#include <linux/mod_devicetable.h>
#include <linux/of_platform.h>
@@ -108,7 +109,8 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
{
unsigned long flags;
u8 mcn_shift = 0, dev_shift = 0;
- u32 ret;
+ u32 val;
+ int ret;

spin_lock_irqsave(&qe_lock, flags);
if (cmd == QE_RESET) {
@@ -135,13 +137,12 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
}

/* wait for the QE_CR_FLG to clear */
- ret = spin_event_timeout((ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
- 100, 0);
- /* On timeout (e.g. failure), the expression will be false (ret == 0),
- otherwise it will be true (ret == 1). */
+ ret = readx_poll_timeout_atomic(ioread32be, &qe_immr->cp.cecr, val, (val & QE_CR_FLG) == 0,
+ 0, 100);
+ /* On timeout, ret is -ETIMEDOUT, otherwise it will be 0. */
spin_unlock_irqrestore(&qe_lock, flags);

- return ret == 1;
+ return ret == 0;
}
EXPORT_SYMBOL(qe_issue_cmd);

--
2.20.1

2019-10-19 08:23:30

by Rasmus Villemoes

Subject: [PATCH 6/7] serial: ucc_uart.c: explicitly include asm/cpm.h

This driver uses #defines from asm/cpm.h, so instead of relying on
some other header pulling that in, do that explicitly.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/tty/serial/ucc_uart.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index a0555ae2b1ef..e2c998badf81 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -33,6 +33,7 @@

#include <linux/firmware.h>
#include <asm/reg.h>
+#include <asm/cpm.h>

/*
* The GUMR flag for Soft UART. This would normally be defined in qe.h,
--
2.20.1

2019-10-19 08:24:35

by Rasmus Villemoes

Subject: [PATCH 1/7] soc: fsl: qe: remove space-before-tab

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 417df7e19281..6fcbfad408de 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -378,8 +378,8 @@ static int qe_sdma_init(void)
}

out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
- out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
- (0x1 << QE_SDMR_CEN_SHIFT)));
+ out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
+ (0x1 << QE_SDMR_CEN_SHIFT)));

return 0;
}
--
2.20.1

2019-10-19 08:24:40

by Rasmus Villemoes

Subject: [PATCH 2/7] soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs

The actual io accessors (e.g. in_be32) implicitly add a volatile
qualifier to their address argument. Remove volatile from the struct
definition and the qe_ic_(read/write) helpers, in preparation for
switching from the ppc-specific io accessors to generic ones.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe_ic.c | 4 ++--
drivers/soc/fsl/qe/qe_ic.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 9bac546998d3..9694569dcc76 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -171,12 +171,12 @@ static struct qe_ic_info qe_ic_info[] = {
},
};

-static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
+static inline u32 qe_ic_read(__be32 __iomem * base, unsigned int reg)
{
return in_be32(base + (reg >> 2));
}

-static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
+static inline void qe_ic_write(__be32 __iomem * base, unsigned int reg,
u32 value)
{
out_be32(base + (reg >> 2), value);
diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h
index 08c695672a03..9420378d9b6b 100644
--- a/drivers/soc/fsl/qe/qe_ic.h
+++ b/drivers/soc/fsl/qe/qe_ic.h
@@ -72,7 +72,7 @@

struct qe_ic {
/* Control registers offset */
- volatile u32 __iomem *regs;
+ u32 __iomem *regs;

/* The remapper for this QEIC */
struct irq_domain *irqhost;
--
2.20.1

2019-10-19 08:24:41

by Rasmus Villemoes

Subject: [PATCH 5/7] serial: make SERIAL_QE depend on PPC32

Currently SERIAL_QE depends on QUICC_ENGINE, which in turn depends on
PPC32, so this doesn't add any extra dependency. However, the QUICC
Engine IP block also exists on some arm boards, so this serves as
preparation for removing the PPC32 dependency from QUICC_ENGINE and
build the QE support in drivers/soc/fsl/qe, while preventing
allmodconfig/randconfig failures due to SERIAL_QE not being supported
yet.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/tty/serial/Kconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 67a9eb3f94ce..78246f535809 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1056,6 +1056,7 @@ config SERIAL_LANTIQ
config SERIAL_QE
tristate "Freescale QUICC Engine serial port support"
depends on QUICC_ENGINE
+ depends on PPC32
select SERIAL_CORE
select FW_LOADER
help
--
2.20.1

2019-10-19 08:25:25

by Rasmus Villemoes

Subject: [PATCH 3/7] soc: fsl: qe: avoid ppc-specific io accessors

In preparation for allowing to build QE support for architectures
other than PPC, replace the ppc-specific io accessors. Done via

$ spatch --sp-file io.cocci --in-place drivers/soc/fsl/qe/

where io.cocci is

@@
expression addr, val;
@@
- out_be32(addr, val)
+ iowrite32be(val, addr)

@@
expression addr;
@@
- in_be32(addr)
+ ioread32be(addr)

@@
expression addr, val;
@@
- out_be16(addr, val)
+ iowrite16be(val, addr)

@@
expression addr;
@@
- in_be16(addr)
+ ioread16be(addr)

@@
expression addr, clr, set;
@@
- clrsetbits_be32(addr, clr, set)
+ qe_clrsetbits32(addr, clr, set)

@@
expression addr, clr, set;
@@
- clrsetbits_be16(addr, clr, set)
+ qe_clrsetbits16(addr, clr, set)

@@
expression addr, clr, set;
@@
- clrsetbits8(addr, clr, set)
+ qe_clrsetbits8(addr, clr, set)

@@
expression addr, set;
@@
- setbits32(addr, set)
+ qe_setbits32(addr, set)

@@
expression addr, set;
@@
- setbits16(addr, set)
+ qe_setbits16(addr, set)

@@
expression addr, set;
@@
- setbits8(addr, set)
+ qe_setbits8(addr, set)

@@
expression addr, clr;
@@
- clrbits32(addr, clr)
+ qe_clrbits32(addr, clr)

@@
expression addr, clr;
@@
- clrbits16(addr, clr)
+ qe_clrbits16(addr, clr)

@@
expression addr, clr;
@@
- clrbits8(addr, clr)
+ qe_clrbits8(addr, clr)

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/gpio.c | 30 ++++++++--------
drivers/soc/fsl/qe/qe.c | 35 +++++++++----------
drivers/soc/fsl/qe/qe_ic.c | 4 +--
drivers/soc/fsl/qe/qe_io.c | 40 ++++++++++-----------
drivers/soc/fsl/qe/qe_tdm.c | 8 ++---
drivers/soc/fsl/qe/ucc.c | 12 +++----
drivers/soc/fsl/qe/ucc_fast.c | 66 ++++++++++++++++++-----------------
drivers/soc/fsl/qe/ucc_slow.c | 38 ++++++++++----------
drivers/soc/fsl/qe/usb.c | 2 +-
9 files changed, 116 insertions(+), 119 deletions(-)

diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
index f0c29ed8f0ff..949a35ac253c 100644
--- a/drivers/soc/fsl/qe/gpio.c
+++ b/drivers/soc/fsl/qe/gpio.c
@@ -41,13 +41,13 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
container_of(mm_gc, struct qe_gpio_chip, mm_gc);
struct qe_pio_regs __iomem *regs = mm_gc->regs;

- qe_gc->cpdata = in_be32(&regs->cpdata);
+ qe_gc->cpdata = ioread32be(&regs->cpdata);
qe_gc->saved_regs.cpdata = qe_gc->cpdata;
- qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
- qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
- qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
- qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
- qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
+ qe_gc->saved_regs.cpdir1 = ioread32be(&regs->cpdir1);
+ qe_gc->saved_regs.cpdir2 = ioread32be(&regs->cpdir2);
+ qe_gc->saved_regs.cppar1 = ioread32be(&regs->cppar1);
+ qe_gc->saved_regs.cppar2 = ioread32be(&regs->cppar2);
+ qe_gc->saved_regs.cpodr = ioread32be(&regs->cpodr);
}

static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
@@ -56,7 +56,7 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
struct qe_pio_regs __iomem *regs = mm_gc->regs;
u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);

- return !!(in_be32(&regs->cpdata) & pin_mask);
+ return !!(ioread32be(&regs->cpdata) & pin_mask);
}

static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
@@ -74,7 +74,7 @@ static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
else
qe_gc->cpdata &= ~pin_mask;

- out_be32(&regs->cpdata, qe_gc->cpdata);
+ iowrite32be(qe_gc->cpdata, &regs->cpdata);

spin_unlock_irqrestore(&qe_gc->lock, flags);
}
@@ -101,7 +101,7 @@ static void qe_gpio_set_multiple(struct gpio_chip *gc,
}
}

- out_be32(&regs->cpdata, qe_gc->cpdata);
+ iowrite32be(qe_gc->cpdata, &regs->cpdata);

spin_unlock_irqrestore(&qe_gc->lock, flags);
}
@@ -255,11 +255,11 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)
spin_lock_irqsave(&qe_gc->lock, flags);

if (second_reg) {
- clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
- clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
+ qe_clrsetbits32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
+ qe_clrsetbits32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
} else {
- clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
- clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
+ qe_clrsetbits32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
+ qe_clrsetbits32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
}

if (sregs->cpdata & mask1)
@@ -267,8 +267,8 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)
else
qe_gc->cpdata &= ~mask1;

- out_be32(&regs->cpdata, qe_gc->cpdata);
- clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
+ iowrite32be(qe_gc->cpdata, &regs->cpdata);
+ qe_clrsetbits32(&regs->cpodr, mask1, sregs->cpodr & mask1);

spin_unlock_irqrestore(&qe_gc->lock, flags);
}
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 6fcbfad408de..60bf047001be 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -112,7 +112,7 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)

spin_lock_irqsave(&qe_lock, flags);
if (cmd == QE_RESET) {
- out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
+ iowrite32be((u32)(cmd | QE_CR_FLG), &qe_immr->cp.cecr);
} else {
if (cmd == QE_ASSIGN_PAGE) {
/* Here device is the SNUM, not sub-block */
@@ -129,15 +129,14 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
}

- out_be32(&qe_immr->cp.cecdr, cmd_input);
- out_be32(&qe_immr->cp.cecr,
- (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
- mcn_protocol << mcn_shift));
+ iowrite32be(cmd_input, &qe_immr->cp.cecdr);
+ iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) | (u32)mcn_protocol << mcn_shift),
+ &qe_immr->cp.cecr);
}

/* wait for the QE_CR_FLG to clear */
- ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
- 100, 0);
+ ret = spin_event_timeout((ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
+ 100, 0);
/* On timeout (e.g. failure), the expression will be false (ret == 0),
otherwise it will be true (ret == 1). */
spin_unlock_irqrestore(&qe_lock, flags);
@@ -230,7 +229,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
QE_BRGC_ENABLE | div16;

- out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
+ iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);

return 0;
}
@@ -377,9 +376,9 @@ static int qe_sdma_init(void)
return -ENOMEM;
}

- out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
- out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
- (0x1 << QE_SDMR_CEN_SHIFT)));
+ iowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK, &sdma->sdebcr);
+ iowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),
+ &sdma->sdmr);

return 0;
}
@@ -417,14 +416,14 @@ static void qe_upload_microcode(const void *base,
"uploading microcode '%s'\n", ucode->id);

/* Use auto-increment */
- out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
- QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
+ iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR,
+ &qe_immr->iram.iadd);

for (i = 0; i < be32_to_cpu(ucode->count); i++)
- out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
+ iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);

/* Set I-RAM Ready Register */
- out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));
+ iowrite32be(be32_to_cpu(QE_IRAM_READY), &qe_immr->iram.iready);
}

/*
@@ -509,7 +508,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
* If the microcode calls for it, split the I-RAM.
*/
if (!firmware->split)
- setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
+ qe_setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);

if (firmware->soc.model)
printk(KERN_INFO
@@ -543,11 +542,11 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
u32 trap = be32_to_cpu(ucode->traps[j]);

if (trap)
- out_be32(&qe_immr->rsp[i].tibcr[j], trap);
+ iowrite32be(trap, &qe_immr->rsp[i].tibcr[j]);
}

/* Enable traps */
- out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
+ iowrite32be(be32_to_cpu(ucode->eccr), &qe_immr->rsp[i].eccr);
}

qe_firmware_uploaded = 1;
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 9694569dcc76..504ede10b978 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -173,13 +173,13 @@ static struct qe_ic_info qe_ic_info[] = {

static inline u32 qe_ic_read(__be32 __iomem * base, unsigned int reg)
{
- return in_be32(base + (reg >> 2));
+ return ioread32be(base + (reg >> 2));
}

static inline void qe_ic_write(__be32 __iomem * base, unsigned int reg,
u32 value)
{
- out_be32(base + (reg >> 2), value);
+ iowrite32be(value, base + (reg >> 2));
}

static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c
index 3657e296a8a2..776a2c9361e1 100644
--- a/drivers/soc/fsl/qe/qe_io.c
+++ b/drivers/soc/fsl/qe/qe_io.c
@@ -57,16 +57,16 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));

/* Set open drain, if required */
- tmp_val = in_be32(&par_io->cpodr);
+ tmp_val = ioread32be(&par_io->cpodr);
if (open_drain)
- out_be32(&par_io->cpodr, pin_mask1bit | tmp_val);
+ iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);
else
- out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val);
+ iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);

/* define direction */
tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
- in_be32(&par_io->cpdir2) :
- in_be32(&par_io->cpdir1);
+ ioread32be(&par_io->cpdir2) :
+ ioread32be(&par_io->cpdir1);

/* get all bits mask for 2 bit per port */
pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
@@ -78,34 +78,30 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,

/* clear and set 2 bits mask */
if (pin > (QE_PIO_PINS / 2) - 1) {
- out_be32(&par_io->cpdir2,
- ~pin_mask2bits & tmp_val);
+ iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io->cpdir2, new_mask2bits | tmp_val);
+ iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);
} else {
- out_be32(&par_io->cpdir1,
- ~pin_mask2bits & tmp_val);
+ iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io->cpdir1, new_mask2bits | tmp_val);
+ iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);
}
/* define pin assignment */
tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
- in_be32(&par_io->cppar2) :
- in_be32(&par_io->cppar1);
+ ioread32be(&par_io->cppar2) :
+ ioread32be(&par_io->cppar1);

new_mask2bits = (u32) (assignment << (QE_PIO_PINS -
(pin % (QE_PIO_PINS / 2) + 1) * 2));
/* clear and set 2 bits mask */
if (pin > (QE_PIO_PINS / 2) - 1) {
- out_be32(&par_io->cppar2,
- ~pin_mask2bits & tmp_val);
+ iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io->cppar2, new_mask2bits | tmp_val);
+ iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);
} else {
- out_be32(&par_io->cppar1,
- ~pin_mask2bits & tmp_val);
+ iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io->cppar1, new_mask2bits | tmp_val);
+ iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);
}
}
EXPORT_SYMBOL(__par_io_config_pin);
@@ -133,12 +129,12 @@ int par_io_data_set(u8 port, u8 pin, u8 val)
/* calculate pin location */
pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));

- tmp_val = in_be32(&par_io[port].cpdata);
+ tmp_val = ioread32be(&par_io[port].cpdata);

if (val == 0) /* clear */
- out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val);
+ iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);
else /* set */
- out_be32(&par_io[port].cpdata, pin_mask | tmp_val);
+ iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);

return 0;
}
diff --git a/drivers/soc/fsl/qe/qe_tdm.c b/drivers/soc/fsl/qe/qe_tdm.c
index e37ebc3be661..e7b1c8e3d229 100644
--- a/drivers/soc/fsl/qe/qe_tdm.c
+++ b/drivers/soc/fsl/qe/qe_tdm.c
@@ -169,10 +169,10 @@ void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)
&siram[siram_entry_id * 32 + 0x200 + i]);
}

- setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
- SIR_LAST);
- setbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],
- SIR_LAST);
+ qe_setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
+ SIR_LAST);
+ qe_setbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],
+ SIR_LAST);

/* Set SIxMR register */
sixmr = SIMR_SAD(siram_entry_id);
diff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c
index 024d239ac1e1..82f06578ceac 100644
--- a/drivers/soc/fsl/qe/ucc.c
+++ b/drivers/soc/fsl/qe/ucc.c
@@ -35,8 +35,8 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
return -EINVAL;

spin_lock_irqsave(&cmxgcr_lock, flags);
- clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
- ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
+ qe_clrsetbits32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
+ ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
spin_unlock_irqrestore(&cmxgcr_lock, flags);

return 0;
@@ -109,9 +109,9 @@ int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);

if (set)
- setbits32(cmxucr, mask << shift);
+ qe_setbits32(cmxucr, mask << shift);
else
- clrbits32(cmxucr, mask << shift);
+ qe_clrbits32(cmxucr, mask << shift);

return 0;
}
@@ -207,8 +207,8 @@ int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
if (mode == COMM_DIR_RX)
shift += 4;

- clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
- clock_bits << shift);
+ qe_clrsetbits32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
+ clock_bits << shift);

return 0;
}
diff --git a/drivers/soc/fsl/qe/ucc_fast.c b/drivers/soc/fsl/qe/ucc_fast.c
index af4d80e38521..7fcb1d767a8f 100644
--- a/drivers/soc/fsl/qe/ucc_fast.c
+++ b/drivers/soc/fsl/qe/ucc_fast.c
@@ -29,39 +29,39 @@ void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);

printk(KERN_INFO "gumr : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
+ &uccf->uf_regs->gumr, ioread32be(&uccf->uf_regs->gumr));
printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
+ &uccf->uf_regs->upsmr, ioread32be(&uccf->uf_regs->upsmr));
printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
+ &uccf->uf_regs->utodr, ioread16be(&uccf->uf_regs->utodr));
printk(KERN_INFO "udsr : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
+ &uccf->uf_regs->udsr, ioread16be(&uccf->uf_regs->udsr));
printk(KERN_INFO "ucce : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
+ &uccf->uf_regs->ucce, ioread32be(&uccf->uf_regs->ucce));
printk(KERN_INFO "uccm : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
+ &uccf->uf_regs->uccm, ioread32be(&uccf->uf_regs->uccm));
printk(KERN_INFO "uccs : addr=0x%p, val=0x%02x\n",
&uccf->uf_regs->uccs, in_8(&uccf->uf_regs->uccs));
printk(KERN_INFO "urfb : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
+ &uccf->uf_regs->urfb, ioread32be(&uccf->uf_regs->urfb));
printk(KERN_INFO "urfs : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
+ &uccf->uf_regs->urfs, ioread16be(&uccf->uf_regs->urfs));
printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
+ &uccf->uf_regs->urfet, ioread16be(&uccf->uf_regs->urfet));
printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset));
+ &uccf->uf_regs->urfset, ioread16be(&uccf->uf_regs->urfset));
printk(KERN_INFO "utfb : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
+ &uccf->uf_regs->utfb, ioread32be(&uccf->uf_regs->utfb));
printk(KERN_INFO "utfs : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
+ &uccf->uf_regs->utfs, ioread16be(&uccf->uf_regs->utfs));
printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
+ &uccf->uf_regs->utfet, ioread16be(&uccf->uf_regs->utfet));
printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
+ &uccf->uf_regs->utftt, ioread16be(&uccf->uf_regs->utftt));
printk(KERN_INFO "utpt : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
+ &uccf->uf_regs->utpt, ioread16be(&uccf->uf_regs->utpt));
printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
+ &uccf->uf_regs->urtry, ioread32be(&uccf->uf_regs->urtry));
printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",
&uccf->uf_regs->guemr, in_8(&uccf->uf_regs->guemr));
}
@@ -85,7 +85,7 @@ EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock);

void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
{
- out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
+ iowrite16be(UCC_FAST_TOD, &uccf->uf_regs->utodr);
}
EXPORT_SYMBOL(ucc_fast_transmit_on_demand);

@@ -97,7 +97,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
uf_regs = uccf->uf_regs;

/* Enable reception and/or transmission on this UCC. */
- gumr = in_be32(&uf_regs->gumr);
+ gumr = ioread32be(&uf_regs->gumr);
if (mode & COMM_DIR_TX) {
gumr |= UCC_FAST_GUMR_ENT;
uccf->enabled_tx = 1;
@@ -106,7 +106,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
gumr |= UCC_FAST_GUMR_ENR;
uccf->enabled_rx = 1;
}
- out_be32(&uf_regs->gumr, gumr);
+ iowrite32be(gumr, &uf_regs->gumr);
}
EXPORT_SYMBOL(ucc_fast_enable);

@@ -118,7 +118,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
uf_regs = uccf->uf_regs;

/* Disable reception and/or transmission on this UCC. */
- gumr = in_be32(&uf_regs->gumr);
+ gumr = ioread32be(&uf_regs->gumr);
if (mode & COMM_DIR_TX) {
gumr &= ~UCC_FAST_GUMR_ENT;
uccf->enabled_tx = 0;
@@ -127,7 +127,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
gumr &= ~UCC_FAST_GUMR_ENR;
uccf->enabled_rx = 0;
}
- out_be32(&uf_regs->gumr, gumr);
+ iowrite32be(gumr, &uf_regs->gumr);
}
EXPORT_SYMBOL(ucc_fast_disable);

@@ -259,7 +259,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
gumr |= uf_info->tenc;
gumr |= uf_info->tcrc;
gumr |= uf_info->mode;
- out_be32(&uf_regs->gumr, gumr);
+ iowrite32be(gumr, &uf_regs->gumr);

/* Allocate memory for Tx Virtual Fifo */
uccf->ucc_fast_tx_virtual_fifo_base_offset =
@@ -286,15 +286,17 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
}

/* Set Virtual Fifo registers */
- out_be16(&uf_regs->urfs, uf_info->urfs);
- out_be16(&uf_regs->urfet, uf_info->urfet);
- out_be16(&uf_regs->urfset, uf_info->urfset);
- out_be16(&uf_regs->utfs, uf_info->utfs);
- out_be16(&uf_regs->utfet, uf_info->utfet);
- out_be16(&uf_regs->utftt, uf_info->utftt);
+ iowrite16be(uf_info->urfs, &uf_regs->urfs);
+ iowrite16be(uf_info->urfet, &uf_regs->urfet);
+ iowrite16be(uf_info->urfset, &uf_regs->urfset);
+ iowrite16be(uf_info->utfs, &uf_regs->utfs);
+ iowrite16be(uf_info->utfet, &uf_regs->utfet);
+ iowrite16be(uf_info->utftt, &uf_regs->utftt);
/* utfb, urfb are offsets from MURAM base */
- out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);
- out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);
+ iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset,
+ &uf_regs->utfb);
+ iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset,
+ &uf_regs->urfb);

/* Mux clocking */
/* Grant Support */
@@ -362,14 +364,14 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
}

/* Set interrupt mask register at UCC level. */
- out_be32(&uf_regs->uccm, uf_info->uccm_mask);
+ iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);

/* First, clear anything pending at UCC level,
* otherwise, old garbage may come through
* as soon as the dam is opened. */

/* Writing '1' clears */
- out_be32(&uf_regs->ucce, 0xffffffff);
+ iowrite32be(0xffffffff, &uf_regs->ucce);

*uccf_ret = uccf;
return 0;
diff --git a/drivers/soc/fsl/qe/ucc_slow.c b/drivers/soc/fsl/qe/ucc_slow.c
index 34f0ec3a63b5..74213f8b361c 100644
--- a/drivers/soc/fsl/qe/ucc_slow.c
+++ b/drivers/soc/fsl/qe/ucc_slow.c
@@ -78,7 +78,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
us_regs = uccs->us_regs;

/* Enable reception and/or transmission on this UCC. */
- gumr_l = in_be32(&us_regs->gumr_l);
+ gumr_l = ioread32be(&us_regs->gumr_l);
if (mode & COMM_DIR_TX) {
gumr_l |= UCC_SLOW_GUMR_L_ENT;
uccs->enabled_tx = 1;
@@ -87,7 +87,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
gumr_l |= UCC_SLOW_GUMR_L_ENR;
uccs->enabled_rx = 1;
}
- out_be32(&us_regs->gumr_l, gumr_l);
+ iowrite32be(gumr_l, &us_regs->gumr_l);
}
EXPORT_SYMBOL(ucc_slow_enable);

@@ -99,7 +99,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
us_regs = uccs->us_regs;

/* Disable reception and/or transmission on this UCC. */
- gumr_l = in_be32(&us_regs->gumr_l);
+ gumr_l = ioread32be(&us_regs->gumr_l);
if (mode & COMM_DIR_TX) {
gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
uccs->enabled_tx = 0;
@@ -108,7 +108,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
uccs->enabled_rx = 0;
}
- out_be32(&us_regs->gumr_l, gumr_l);
+ iowrite32be(gumr_l, &us_regs->gumr_l);
}
EXPORT_SYMBOL(ucc_slow_disable);

@@ -198,7 +198,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
return ret;
}

- out_be16(&uccs->us_pram->mrblr, us_info->max_rx_buf_length);
+ iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr);

INIT_LIST_HEAD(&uccs->confQ);

@@ -228,27 +228,27 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) {
/* clear bd buffer */
- out_be32(&bd->buf, 0);
+ iowrite32be(0, &bd->buf);
/* set bd status and length */
- out_be32((u32 *) bd, 0);
+ iowrite32be(0, (u32 *)bd);
bd++;
}
/* for last BD set Wrap bit */
- out_be32(&bd->buf, 0);
- out_be32((u32 *) bd, cpu_to_be32(T_W));
+ iowrite32be(0, &bd->buf);
+ iowrite32be(cpu_to_be32(T_W), (u32 *)bd);

/* Init Rx bds */
bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {
/* set bd status and length */
- out_be32((u32*)bd, 0);
+ iowrite32be(0, (u32 *)bd);
/* clear bd buffer */
- out_be32(&bd->buf, 0);
+ iowrite32be(0, &bd->buf);
bd++;
}
/* for last BD set Wrap bit */
- out_be32((u32*)bd, cpu_to_be32(R_W));
- out_be32(&bd->buf, 0);
+ iowrite32be(cpu_to_be32(R_W), (u32 *)bd);
+ iowrite32be(0, &bd->buf);

/* Set GUMR (For more details see the hardware spec.). */
/* gumr_h */
@@ -269,7 +269,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
gumr |= UCC_SLOW_GUMR_H_TXSY;
if (us_info->rtsm)
gumr |= UCC_SLOW_GUMR_H_RTSM;
- out_be32(&us_regs->gumr_h, gumr);
+ iowrite32be(gumr, &us_regs->gumr_h);

/* gumr_l */
gumr = us_info->tdcr | us_info->rdcr | us_info->tenc | us_info->renc |
@@ -282,7 +282,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
gumr |= UCC_SLOW_GUMR_L_TINV;
if (us_info->tend)
gumr |= UCC_SLOW_GUMR_L_TEND;
- out_be32(&us_regs->gumr_l, gumr);
+ iowrite32be(gumr, &us_regs->gumr_l);

/* Function code registers */

@@ -292,8 +292,8 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
uccs->us_pram->rbmr = UCC_BMR_BO_BE;

/* rbase, tbase are offsets from MURAM base */
- out_be16(&uccs->us_pram->rbase, uccs->rx_base_offset);
- out_be16(&uccs->us_pram->tbase, uccs->tx_base_offset);
+ iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase);
+ iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase);

/* Mux clocking */
/* Grant Support */
@@ -323,14 +323,14 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
}

/* Set interrupt mask register at UCC level. */
- out_be16(&us_regs->uccm, us_info->uccm_mask);
+ iowrite16be(us_info->uccm_mask, &us_regs->uccm);

/* First, clear anything pending at UCC level,
* otherwise, old garbage may come through
* as soon as the dam is opened. */

/* Writing '1' clears */
- out_be16(&us_regs->ucce, 0xffff);
+ iowrite16be(0xffff, &us_regs->ucce);

/* Issue QE Init command */
if (us_info->init_tx && us_info->init_rx)
diff --git a/drivers/soc/fsl/qe/usb.c b/drivers/soc/fsl/qe/usb.c
index 32d8269fa692..59b326e924dc 100644
--- a/drivers/soc/fsl/qe/usb.c
+++ b/drivers/soc/fsl/qe/usb.c
@@ -43,7 +43,7 @@ int qe_usb_clock_set(enum qe_clock clk, int rate)

spin_lock_irqsave(&cmxgcr_lock, flags);

- clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);
+ qe_clrsetbits32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);

spin_unlock_irqrestore(&cmxgcr_lock, flags);

--
2.20.1

2019-10-19 08:25:32

by Rasmus Villemoes

Subject: [PATCH 7/7] soc/fsl/qe/qe.h: remove include of asm/cpm.h

asm/cpm.h only exists on PPC, so this prevents use of this header on
other platforms. Drivers that need asm/cpm.h (and are thus inherently
PPC-specific) must include that explicitly.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
include/soc/fsl/qe/qe.h | 1 -
1 file changed, 1 deletion(-)

diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index c1036d16ed03..3768c226490e 100644
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -17,7 +17,6 @@
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/err.h>
-#include <asm/cpm.h>
#include <soc/fsl/qe/immap_qe.h>
#include <linux/of.h>
#include <linux/of_address.h>
--
2.20.1

2019-10-19 08:25:44

by Christophe Leroy

Subject: Re: [PATCH 1/7] soc: fsl: qe: remove space-before-tab

Le 18/10/2019 à 14:52, Rasmus Villemoes a écrit :
> Signed-off-by: Rasmus Villemoes <[email protected]>
> ---
> drivers/soc/fsl/qe/qe.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
> index 417df7e19281..6fcbfad408de 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -378,8 +378,8 @@ static int qe_sdma_init(void)
> }
>
> out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
> - out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
> - (0x1 << QE_SDMR_CEN_SHIFT)));
> + out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
> + (0x1 << QE_SDMR_CEN_SHIFT)));

Could you also align the second line properly ?

Christophe

>
> return 0;
> }
>

2019-10-19 08:26:00

by Christophe Leroy

Subject: Re: [PATCH 2/7] soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs

Le 18/10/2019 à 14:52, Rasmus Villemoes a écrit :
> The actual io accessors (e.g. in_be32) implicitly add a volatile
> qualifier to their address argument. Remove volatile from the struct
> definition and the qe_ic_(read/write) helpers, in preparation for
> switching from the ppc-specific io accessors to generic ones.
>
> Signed-off-by: Rasmus Villemoes <[email protected]>
> ---
> drivers/soc/fsl/qe/qe_ic.c | 4 ++--
> drivers/soc/fsl/qe/qe_ic.h | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
> index 9bac546998d3..9694569dcc76 100644
> --- a/drivers/soc/fsl/qe/qe_ic.c
> +++ b/drivers/soc/fsl/qe/qe_ic.c
> @@ -171,12 +171,12 @@ static struct qe_ic_info qe_ic_info[] = {
> },
> };
>
> -static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
> +static inline u32 qe_ic_read(__be32 __iomem * base, unsigned int reg)

No space between '*' and 'base' please

> {
> return in_be32(base + (reg >> 2));
> }
>
> -static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
> +static inline void qe_ic_write(__be32 __iomem * base, unsigned int reg,

same

> u32 value)
> {
> out_be32(base + (reg >> 2), value);
> diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h
> index 08c695672a03..9420378d9b6b 100644
> --- a/drivers/soc/fsl/qe/qe_ic.h
> +++ b/drivers/soc/fsl/qe/qe_ic.h
> @@ -72,7 +72,7 @@
>
> struct qe_ic {
> /* Control registers offset */
> - volatile u32 __iomem *regs;
> + u32 __iomem *regs;
>
> /* The remapper for this QEIC */
> struct irq_domain *irqhost;
>

Christophe

2019-10-19 08:39:18

by Christoph Hellwig

Subject: Re: [PATCH 4/7] soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic

On Fri, Oct 18, 2019 at 02:52:31PM +0200, Rasmus Villemoes wrote:
> /* wait for the QE_CR_FLG to clear */
> - ret = spin_event_timeout((ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
> - 100, 0);
> - /* On timeout (e.g. failure), the expression will be false (ret == 0),
> - otherwise it will be true (ret == 1). */
> + ret = readx_poll_timeout_atomic(ioread32be, &qe_immr->cp.cecr, val, (val & QE_CR_FLG) == 0,

This creates an overly long line.

Btw, given how few users of spin_event_timeout we have it might be good
idea to just kill it entirely.

2019-10-19 09:14:10

by Leo Li

Subject: RE: [PATCH 0/7] towards QE support on ARM

> -----Original Message-----
> From: Rasmus Villemoes <[email protected]>
> Sent: Friday, October 18, 2019 7:52 AM
> To: Qiang Zhao <[email protected]>; Leo Li <[email protected]>; Greg
> Kroah-Hartman <[email protected]>; Jiri Slaby
> <[email protected]>; Timur Tabi <[email protected]>; linuxppc-
> [email protected]; [email protected]; linux-
> [email protected]; [email protected]
> Cc: Rasmus Villemoes <[email protected]>
> Subject: [PATCH 0/7] towards QE support on ARM
>
> There have been several attempts in the past few years to allow building the
> QUICC engine drivers for platforms other than PPC. This is (the beginning of)
> yet another attempt. I hope I can get someone to pick up these relatively
> trivial patches (I _think_ they shouldn't change functionality at all), and then
> I'll continue slowly working towards removing the PPC32 dependency for
> CONFIG_QUICC_ENGINE.

Hi Rasmus,

I don't fully understand the motivation of this work. As far as I know the QUICC ENGINE is only used on PowerPC based SoCs. Can you give an example on how is it used on ARM system?

>
> Tested on an MPC8309-derived board.

MPC8309 is also PPC based.

>
> Rasmus Villemoes (7):
> soc: fsl: qe: remove space-before-tab
> soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs
> soc: fsl: qe: avoid ppc-specific io accessors
> soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic
> serial: make SERIAL_QE depend on PPC32
> serial: ucc_uart.c: explicitly include asm/cpm.h
> soc/fsl/qe/qe.h: remove include of asm/cpm.h
>
> drivers/soc/fsl/qe/gpio.c | 30 ++++++++--------
> drivers/soc/fsl/qe/qe.c | 44 +++++++++++------------
> drivers/soc/fsl/qe/qe_ic.c | 8 ++---
> drivers/soc/fsl/qe/qe_ic.h | 2 +-
> drivers/soc/fsl/qe/qe_io.c | 40 ++++++++++-----------
> drivers/soc/fsl/qe/qe_tdm.c | 8 ++---
> drivers/soc/fsl/qe/ucc.c | 12 +++----
> drivers/soc/fsl/qe/ucc_fast.c | 66 ++++++++++++++++++-----------------
> drivers/soc/fsl/qe/ucc_slow.c | 38 ++++++++++----------
> drivers/soc/fsl/qe/usb.c | 2 +-
> drivers/tty/serial/Kconfig | 1 +
> drivers/tty/serial/ucc_uart.c | 1 +
> include/soc/fsl/qe/qe.h | 1 -
> 13 files changed, 126 insertions(+), 127 deletions(-)
>
> --
> 2.20.1

2019-10-19 09:17:14

by Rasmus Villemoes

Subject: Re: [PATCH 0/7] towards QE support on ARM

On 18/10/2019 22.16, Leo Li wrote:
>
>>
>> There have been several attempts in the past few years to allow building the
>> QUICC engine drivers for platforms other than PPC. This is (the beginning of)
>> yet another attempt. I hope I can get someone to pick up these relatively
>> trivial patches (I _think_ they shouldn't change functionality at all), and then
>> I'll continue slowly working towards removing the PPC32 dependency for
>> CONFIG_QUICC_ENGINE.
>
> Hi Rasmus,
>
> I don't fully understand the motivation of this work. As far as I know the QUICC ENGINE is only used on PowerPC based SoCs.

Hm, you're not the Leo Li that participated in this thread
<https://lore.kernel.org/lkml/AM3PR04MB11857AE8D2B0BE56121B97D391C90@AM3PR04MB1185.eurprd04.prod.outlook.com/T/#u>?


Can you give an example on how is it used on ARM system?

LS1021A, for example, which is the one I'm aiming for getting fully
supported in mainline.
<https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/qoriq-layerscape-1021a-dual-core-communications-processor-with-lcd-controller:LS1021A>

The forks at https://github.com/qoriq-open-source/linux.git have various
degrees of support (grep for commits saying stuff like "remove PPCisms"
- some versions can be found on
<https://lore.kernel.org/lkml/?q=remove+ppcisms>). Our current kernel is
based on commits from the now-vanished 4.1 branch, and unfortunately at
least the 4.14 branch (LSDK-18.06-V4.14) trivially doesn't build on ARM,
despite the PPC32 dependency having been removed from CONFIG_QUICC_ENGINE.

>>
>> Tested on an MPC8309-derived board.
>
> MPC8309 is also PPC based.

True, of course. This is just some first few steps, and I'm not claiming
that this is sufficient to make the QE drivers build on ARM yet. But I
have a customer with both mpc8309-based and ls1021a-based platforms, and
they want to run the same, as-close-to-mainline-as-possible, kernel on
both. So I will take a piecemeal approach, and try to make sure I don't
break the ppc boards in the process (just building and booting one board
is of course not sufficient, but better than nothing). Once I get to
actually build some of the QE drivers for ARM, I'll of course also test
them.

Rasmus

2019-10-19 09:22:36

by Leo Li

Subject: Re: [PATCH 0/7] towards QE support on ARM

On Fri, Oct 18, 2019 at 3:54 PM Rasmus Villemoes
<[email protected]> wrote:
>
> On 18/10/2019 22.16, Leo Li wrote:
> >
> >>
> >> There have been several attempts in the past few years to allow building the
> >> QUICC engine drivers for platforms other than PPC. This is (the beginning of)
> >> yet another attempt. I hope I can get someone to pick up these relatively
> >> trivial patches (I _think_ they shouldn't change functionality at all), and then
> >> I'll continue slowly working towards removing the PPC32 dependency for
> >> CONFIG_QUICC_ENGINE.
> >
> > Hi Rasmus,
> >
> > I don't fully understand the motivation of this work. As far as I know the QUICC ENGINE is only used on PowerPC based SoCs.
>
> Hm, you're not the Leo Li that participated in this thread
> <https://lore.kernel.org/lkml/AM3PR04MB11857AE8D2B0BE56121B97D391C90@AM3PR04MB1185.eurprd04.prod.outlook.com/T/#u>?

Oops, I totally forgot about this discussion which is just three years
ago. :) The QE-HDLC on LS1021a is kind of a special case.

>
>
> Can you give an example on how is it used on ARM system?
>
> LS1021A, for example, which is the one I'm aiming for getting fully
> supported in mainline.
> <https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/qoriq-layerscape-1021a-dual-core-communications-processor-with-lcd-controller:LS1021A>
>
> The forks at https://github.com/qoriq-open-source/linux.git have various
> degrees of support (grep for commits saying stuff like "remove PPCisms"
> - some versions can be found on
> <https://lore.kernel.org/lkml/?q=remove+ppcisms>). Our current kernel is
> based on commits from the now-vanished 4.1 branch, and unfortunately at
> least the 4.14 branch (LSDK-18.06-V4.14) trivially doesn't build on ARM,
> despite the PPC32 dependency having been removed from CONFIG_QUICC_ENGINE.

Can you try the 4.14 branch from a newer LSDK release? LS1021a should
be supported platform on LSDK. If it is broken, something is wrong.

>
> >>
> >> Tested on an MPC8309-derived board.
> >
> > MPC8309 is also PPC based.
>
> True, of course. This is just some first few steps, and I'm not claiming
> that this is sufficient to make the QE drivers build on ARM yet. But I
> have a customer with both mpc8309-based and ls1021a-based platforms, and
> they want to run the same, as-close-to-mainline-as-possible, kernel on
> both. So I will take a piecemeal approach, and try to make sure I don't
> break the ppc boards in the process (just building and booting one board
> is of course not sufficient, but better than nothing). Once I get to
> actually build some of the QE drivers for ARM, I'll of course also test
> them.

Understood. Zhao Qiang also maintains some patches similar to your
patchset and I think they are tested on ARM. But the review of these
patches from last submission didn't finish. It looks like your
patches are better divided but not really verified on ARM. Zhao
Qiang's patches are tested but maybe need some final touch for
cleaning up. I will let you guys decide what is the best approach to
make this upstreamed.

Regards,
Leo

2019-10-21 08:47:39

by Rasmus Villemoes

Subject: Re: [PATCH 0/7] towards QE support on ARM

On 18/10/2019 23.52, Li Yang wrote:
> On Fri, Oct 18, 2019 at 3:54 PM Rasmus Villemoes
> <[email protected]> wrote:
>>
>> On 18/10/2019 22.16, Leo Li wrote:
>>>
>>>>
>>>> There have been several attempts in the past few years to allow building the
>>>> QUICC engine drivers for platforms other than PPC. This is (the beginning of)
>>>> yet another attempt. I hope I can get someone to pick up these relatively
>>>> trivial patches (I _think_ they shouldn't change functionality at all), and then
>>>> I'll continue slowly working towards removing the PPC32 dependency for
>>>> CONFIG_QUICC_ENGINE.
>>>
>>> Hi Rasmus,
>>>
>>> I don't fully understand the motivation of this work. As far as I know the QUICC ENGINE is only used on PowerPC based SoCs.
>>
>> Hm, you're not the Leo Li that participated in this thread
>> <https://lore.kernel.org/lkml/AM3PR04MB11857AE8D2B0BE56121B97D391C90@AM3PR04MB1185.eurprd04.prod.outlook.com/T/#u>?
>
> Oops, I totally forgot about this discussion which is just three years
> ago. :) The QE-HDLC on LS1021a is kind of a special case.
>
>>
>>
>> Can you give an example on how is it used on ARM system?
>>
>> LS1021A, for example, which is the one I'm aiming for getting fully
>> supported in mainline.
>> <https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/qoriq-layerscape-1021a-dual-core-communications-processor-with-lcd-controller:LS1021A>
>>
>> The forks at https://github.com/qoriq-open-source/linux.git have various
>> degrees of support (grep for commits saying stuff like "remove PPCisms"
>> - some versions can be found on
>> <https://lore.kernel.org/lkml/?q=remove+ppcisms>). Our current kernel is
>> based on commits from the now-vanished 4.1 branch, and unfortunately at
>> least the 4.14 branch (LSDK-18.06-V4.14) trivially doesn't build on ARM,
>> despite the PPC32 dependency having been removed from CONFIG_QUICC_ENGINE.
>
> Can you try the 4.14 branch from a newer LSDK release? LS1021a should
> be supported platform on LSDK. If it is broken, something is wrong.

What newer release? LSDK-18.06-V4.14 is the latest -V4.14 tag at
https://github.com/qoriq-open-source/linux.git, and identical to the
linux-4.14 branch. And despite commit 4c33e2d0576b removing the PPC32
dependency from QUICC_ENGINE, it clearly hasn't been built on arm, since
back around v4.12, mainline's qe.c grew a call to pvr_version_is which
is ppc-only. So from that I sort of assumed that NXP had dropped trying
to support the LS1021A even in their own kernels.

In any case, we have zero interest in running an NXP kernel. Maybe I
should clarify what I meant by "based on commits from" above: We're
currently running a mainline 4.14 kernel on LS1021A, with a few patches
inspired from the NXP 4.1 branch applied on top - but also with some
manual fixes for e.g. the pvr_version_is() issue. Now we want to move
that to a 4.19-based kernel (so that it aligns with our MPC8309 platform).

>> This is just some first few steps, and I'm not claiming
>> that this is sufficient to make the QE drivers build on ARM yet. But I
>> have a customer with both mpc8309-based and ls1021a-based platforms, and
>> they want to run the same, as-close-to-mainline-as-possible, kernel on
>> both. So I will take a piecemeal approach, and try to make sure I don't
>> break the ppc boards in the process (just building and booting one board
>> is of course not sufficient, but better than nothing). Once I get to
>> actually build some of the QE drivers for ARM, I'll of course also test
>> them.
>
> Understood. Zhao Qiang also maintains some patches similar to your
> patchset and I think they are tested on ARM. But the review of these
> patches from last submission didn't finish. It looks like your
> patches are better divided but not really verified on ARM. Zhao
> Qiang's patches are tested but maybe need some final touch for
> cleaning up. I will let you guys decide what is the best approach to
> make this upstreamed.

Yes, as I said, I wanted to try a fresh approach since Zhao
Qiang's patches seemed to be getting nowhere. Splitting the patches into
smaller pieces is definitely part of that - for example, the completely
trivial whitespace fix in patch 1 is to make sure the later coccinelle
generated patch is precisely that (i.e., a later respin can just rerun
the coccinelle script, with zero manual fixups). I also want to avoid
mixing the ppcism cleanups with other things (e.g. replacing some
of_get_property() by of_property_read_u32()). And the "testing on ARM"
part comes once I get to actually building on ARM. But there's not much
point doing all that unless there's some indication that this can be
applied to some tree that actually feeds into Linus', which is why I
started with a few trivial patches and precisely to start this discussion.

Rasmus

2019-10-21 22:15:55

by Leo Li

Subject: Re: [PATCH 0/7] towards QE support on ARM

On Mon, Oct 21, 2019 at 3:46 AM Rasmus Villemoes
<[email protected]> wrote:
>
> On 18/10/2019 23.52, Li Yang wrote:
> > On Fri, Oct 18, 2019 at 3:54 PM Rasmus Villemoes
> > <[email protected]> wrote:
> >>
> >> On 18/10/2019 22.16, Leo Li wrote:
> >>>
> >>>>
> >>>> There have been several attempts in the past few years to allow building the
> >>>> QUICC engine drivers for platforms other than PPC. This is (the beginning of)
> >>>> yet another attempt. I hope I can get someone to pick up these relatively
> >>>> trivial patches (I _think_ they shouldn't change functionality at all), and then
> >>>> I'll continue slowly working towards removing the PPC32 dependency for
> >>>> CONFIG_QUICC_ENGINE.
> >>>
> >>> Hi Rasmus,
> >>>
> >>> I don't fully understand the motivation of this work. As far as I know the QUICC ENGINE is only used on PowerPC based SoCs.
> >>
> >> Hm, you're not the Leo Li that participated in this thread
> >> <https://lore.kernel.org/lkml/AM3PR04MB11857AE8D2B0BE56121B97D391C90@AM3PR04MB1185.eurprd04.prod.outlook.com/T/#u>?
> >
> > Oops, I totally forgot about this discussion which is just three years
> > ago. :) The QE-HDLC on LS1021a is kind of a special case.
> >
> >>
> >>
> >> Can you give an example on how is it used on ARM system?
> >>
> >> LS1021A, for example, which is the one I'm aiming for getting fully
> >> supported in mainline.
> >> <https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/qoriq-layerscape-1021a-dual-core-communications-processor-with-lcd-controller:LS1021A>
> >>
> >> The forks at https://github.com/qoriq-open-source/linux.git have various
> >> degrees of support (grep for commits saying stuff like "remove PPCisms"
> >> - some versions can be found on
> >> <https://lore.kernel.org/lkml/?q=remove+ppcisms>). Our current kernel is
> >> based on commits from the now-vanished 4.1 branch, and unfortunately at
> >> least the 4.14 branch (LSDK-18.06-V4.14) trivially doesn't build on ARM,
> >> despite the PPC32 dependency having been removed from CONFIG_QUICC_ENGINE.
> >
> > Can you try the 4.14 branch from a newer LSDK release? LS1021a should
> > be supported platform on LSDK. If it is broken, something is wrong.
>
> What newer release? LSDK-18.06-V4.14 is the latest -V4.14 tag at
> https://github.com/qoriq-open-source/linux.git, and identical to the

That tree has been abandoned for a while, we probably should state
that in the github. The latest tree can be found at
https://source.codeaurora.org/external/qoriq/qoriq-components/linux/

> linux-4.14 branch. And despite commit 4c33e2d0576b removing the PPC32
> dependency from QUICC_ENGINE, it clearly hasn't been built on arm, since
> back around v4.12, mainline's qe.c grew a call to pvr_version_is which
> is ppc-only. So from that I sort of assumed that NXP had dropped trying
> to support the LS1021A even in their own kernels.
>
> In any case, we have zero interest in running an NXP kernel. Maybe I
> should clarify what I meant by "based on commits from" above: We're
> currently running a mainline 4.14 kernel on LS1021A, with a few patches
> inspired from the NXP 4.1 branch applied on top - but also with some
> manual fixes for e.g. the pvr_version_is() issue. Now we want to move
> that to a 4.19-based kernel (so that it aligns with our MPC8309 platform).

We also provide 4.19 based kernel in the codeaurora repo. I think it
will be helpful to reuse patches there if you want to make your own
tree.

>
> >> This is just some first few steps, and I'm not claiming
> >> that this is sufficient to make the QE drivers build on ARM yet. But I
> >> have a customer with both mpc8309-based and ls1021a-based platforms, and
> >> they want to run the same, as-close-to-mainline-as-possible, kernel on
> >> both. So I will take a piecemeal approach, and try to make sure I don't
> >> break the ppc boards in the process (just building and booting one board
> >> is of course not sufficient, but better than nothing). Once I get to
> >> actually build some of the QE drivers for ARM, I'll of course also test
> >> them.
> >
> > Understood. Zhao Qiang also maintains some patches similar to your
> > patchset and I think they are tested on ARM. But the review of these
> > patches from last submission didn't finish. It looks like your
> > patches are better divided but not really verified on ARM. Zhao
> > Qiang's patches are tested but maybe need some final touch for
> > cleaning up. I will let you guys decide what is the best approach to
> > make this upstreamed.
>
> Yes, as I said, I wanted to try a fresh approach since Zhao
> Qiang's patches seemed to be getting nowhere. Splitting the patches into
> smaller pieces is definitely part of that - for example, the completely
> trivial whitespace fix in patch 1 is to make sure the later coccinelle
> generated patch is precisely that (i.e., a later respin can just rerun
> the coccinelle script, with zero manual fixups). I also want to avoid
> mixing the ppcism cleanups with other things (e.g. replacing some
> of_get_property() by of_property_read_u32()). And the "testing on ARM"
> part comes once I get to actually building on ARM. But there's not much
> point doing all that unless there's some indication that this can be
> applied to some tree that actually feeds into Linus', which is why I
> started with a few trivial patches and precisely to start this discussion.

Right. I'm really interested in getting this applied to my tree and
make it upstream. Zhao Qiang, can you help to review Rasmus's patches
and comment?

Regards,
Leo

2019-10-22 02:25:05

by Zhao Qiang

Subject: RE: [PATCH 0/7] towards QE support on ARM

On Mon, Oct 22, 2019 at 6:11 AM Leo Li wrote
> -----Original Message-----
> From: Li Yang <[email protected]>
> Sent: 2019年10月22日 6:11
> To: Rasmus Villemoes <[email protected]>
> Cc: Timur Tabi <[email protected]>; Greg Kroah-Hartman
> <[email protected]>; [email protected];
> [email protected]; Jiri Slaby <[email protected]>;
> [email protected]; [email protected]; Qiang
> Zhao <[email protected]>
> Subject: Re: [PATCH 0/7] towards QE support on ARM
>
> On Mon, Oct 21, 2019 at 3:46 AM Rasmus Villemoes
> <[email protected]> wrote:
> >
> > On 18/10/2019 23.52, Li Yang wrote:
> > > On Fri, Oct 18, 2019 at 3:54 PM Rasmus Villemoes
> > > <[email protected]> wrote:
> > >>
> > >> On 18/10/2019 22.16, Leo Li wrote:
> > >>>
> > >>>>
> > >>>> There have been several attempts in the past few years to allow
> > >>>> building the QUICC engine drivers for platforms other than PPC.
> > >>>> This is (the beginning of) yet another attempt. I hope I can get
> > >>>> someone to pick up these relatively trivial patches (I _think_
> > >>>> they shouldn't change functionality at all), and then I'll
> > >>>> continue slowly working towards removing the PPC32 dependency for
> CONFIG_QUICC_ENGINE.
> > >>>
> > >>> Hi Rasmus,
> > >>>
> > >>> I don't fully understand the motivation of this work. As far as I know
> the QUICC ENGINE is only used on PowerPC based SoCs.
> > >>
> > >> Hm, you're not the Leo Li that participated in this thread
> > >>
> <https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ke
> rnel.org%2Flkml%2FAM3PR04MB11857AE8D2B0BE56121B97D391C90%40A
> M3PR04MB1185.eurprd04.prod.outlook.com%2FT%2F%23u&amp;data=02%7
> C01%7Cqiang.zhao%40nxp.com%7C1ba8c50c2db14b22bef608d756739d82%
> 7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6370729268771788
> 75&amp;sdata=k4zM75OczXwZF%2Br9ec4RxiVR2a%2F8GhSZmK70JYddIck%3
> D&amp;reserved=0>?
> > >
> > > Oops, I totally forgot about this discussion which is just three
> > > years ago. :) The QE-HDLC on LS1021a is kind of a special case.
> > >
> > >>
> > >>
> > >> Can you give an example on how is it used on ARM system?
> > >>
> > >> LS1021A, for example, which is the one I'm aiming for getting fully
> > >> supported in mainline.
> > >> <https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> > >>
> http://www.nxp.com%2Fproducts%2Fprocessors-and-microcontrollers%2Farm-proc
> > >> essors%2Flayerscape-communication-process%2Fqoriq-layerscape-1021a-
> > >>
> dual-core-communications-processor-with-lcd-controller%3ALS1021A&am
> > >>
> p;data=02%7C01%7Cqiang.zhao%40nxp.com%7C1ba8c50c2db14b22bef608d
> 7567
> > >>
> 39d82%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6370729268
> 771788
> > >>
> 75&amp;sdata=vqPYSZqEv6vCEIxJshLuA4gngh9J4IsFAQrTwJKMjm4%3D&amp;r
> es
> > >> erved=0>
> > >>
> > >> The forks at
> > >>
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.
> com%2Fqoriq-open-source%2Flinux.git&amp;data=02%7C01%7Cqiang.zhao%
> 40nxp.com%7C1ba8c50c2db14b22bef608d756739d82%7C686ea1d3bc2b4c6
> fa92cd99c5c301635%7C0%7C0%7C637072926877178875&amp;sdata=v4eG
> 4KqGTWQkQHp%2FYg2OHCKITLWaOgH64JYpY%2B1LilA%3D&amp;reserved=0
> have various degrees of support (grep for commits saying stuff like "remove
> PPCisms"
> > >> - some versions can be found on
> > >> <https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> > >>
> lore.kernel.org%2Flkml%2F%3Fq%3Dremove%2Bppcisms&amp;data=02%7C0
> 1%7
> > >>
> Cqiang.zhao%40nxp.com%7C1ba8c50c2db14b22bef608d756739d82%7C686e
> a1d3
> > >>
> bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637072926877178875&amp;sdat
> a=i2WdKNHLV68a1mTOMQ%2FoMr0y5ee8edS07xq61M8%2BvPU%3D&amp;r
> eserved=0>). Our current kernel is based on commits from the now-vanished
> 4.1 branch, and unfortunately at least the 4.14 branch (LSDK-18.06-V4.14)
> trivially doesn't build on ARM, despite the PPC32 dependency having been
> removed from CONFIG_QUICC_ENGINE.
> > >
> > > Can you try the 4.14 branch from a newer LSDK release? LS1021a
> > > should be supported platform on LSDK. If it is broken, something is
> wrong.
> >
> > What newer release? LSDK-18.06-V4.14 is the latest -V4.14 tag at
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgith
> >
> ub.com%2Fqoriq-open-source%2Flinux.git&amp;data=02%7C01%7Cqiang.zha
> o%4
> >
> 0nxp.com%7C1ba8c50c2db14b22bef608d756739d82%7C686ea1d3bc2b4c6f
> a92cd99c
> >
> 5c301635%7C0%7C0%7C637072926877188868&amp;sdata=vdm4qPoTzfIpXL
> mRrv17EW
> > noxG3n91qELMGqvRh9we4%3D&amp;reserved=0, and identical to the
>
> That tree has been abandoned for a while, we probably should state that in the
> github. The latest tree can be found at
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fsource.
> codeaurora.org%2Fexternal%2Fqoriq%2Fqoriq-components%2Flinux%2F&amp
> ;data=02%7C01%7Cqiang.zhao%40nxp.com%7C1ba8c50c2db14b22bef608d7
> 56739d82%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6370729
> 26877188868&amp;sdata=NooBFUWnceTG2OF24pCuP0AYgKfr0Df%2BtrcCY6
> X6Dog%3D&amp;reserved=0
>
> > linux-4.14 branch. And despite commit 4c33e2d0576b removing the PPC32
> > dependency from QUICC_ENGINE, it clearly hasn't been built on arm,
> > since back around v4.12, mainline's qe.c grew a call to pvr_version_is
> > which is ppc-only. So from that I sort of assumed that NXP had dropped
> > trying to support the LS1021A even in their own kernels.
> >
> > In any case, we have zero interest in running an NXP kernel. Maybe I
> > should clarify what I meant by "based on commits from" above: We're
> > currently running a mainline 4.14 kernel on LS1021A, with a few
> > patches inspired from the NXP 4.1 branch applied on top - but also
> > with some manual fixes for e.g. the pvr_version_is() issue. Now we
> > want to move that to a 4.19-based kernel (so that it aligns with our
> MPC8309 platform).
>
> We also provide 4.19 based kernel in the codeaurora repo. I think it will be
> helpful to reuse patches there if you want to make your own tree.
>
> >
> > >> This is just some first few steps, and I'm not claiming that this
> > >> is sufficient to make the QE drivers build on ARM yet. But I have a
> > >> customer with both mpc8309-based and ls1021a-based platforms, and
> > >> they want to run the same, as-close-to-mainline-as-possible, kernel
> > >> on both. So I will take a piecemeal approach, and try to make sure
> > >> I don't break the ppc boards in the process (just building and
> > >> booting one board is of course not sufficient, but better than
> > >> nothing). Once I get to actually build some of the QE drivers for
> > >> ARM, I'll of course also test them.
> > >
> > > Understood. Zhao Qiang also maintains some patches similar to your
> > > patchset and I think they are tested on ARM. But the review of
> > > these patches from last submission didn't finish. It looks like
> > > your patches are better divided but not really verified on ARM.
> > > Zhao Qiang's patches are tested but maybe need some final touch for
> > > cleaning up. I will let you guys decide what is the best approach
> > > to make this upstreamed.
> >
> > Yes, as I said, I wanted to try a fresh approach since Zhao Qiang's
> > patches seemed to be getting nowhere. Splitting the patches into
> > smaller pieces is definitely part of that - for example, the
> > completely trivial whitespace fix in patch 1 is to make sure the later
> > coccinelle generated patch is precisely that (i.e., a later respin can
> > just rerun the coccinelle script, with zero manual fixups). I also
> > want to avoid mixing the ppcism cleanups with other things (e.g.
> > replacing some
> > of_get_property() by of_property_read_u32()). And the "testing on ARM"
> > part comes once I get to actually building on ARM. But there's not
> > much point doing all that unless there's some indication that this can
> > be applied to some tree that actually feeds into Linus', which is why
> > I started with a few trivial patches and precisely to start this discussion.
>
> Right. I'm really interested in getting this applied to my tree and make it
> upstream. Zhao Qiang, can you help to review Rasmus's patches and
> comment?

As you know, I maintained a similar patchset removing PPC, and someone told me qe_ic should moved into drivers/irqchip/.
I also thought qe_ic is a interrupt control driver, should be moved into dir irqchip.

Regards,
Qiang

2019-10-22 10:13:29

by Rasmus Villemoes

Subject: Re: [PATCH 0/7] towards QE support on ARM

On 22/10/2019 00.11, Li Yang wrote:
> On Mon, Oct 21, 2019 at 3:46 AM Rasmus Villemoes
> <[email protected]> wrote:
>>

>>> Can you try the 4.14 branch from a newer LSDK release? LS1021a should
>>> be supported platform on LSDK. If it is broken, something is wrong.
>>
>> What newer release? LSDK-18.06-V4.14 is the latest -V4.14 tag at
>> https://github.com/qoriq-open-source/linux.git, and identical to the
>
> That tree has been abandoned for a while, we probably should state
> that in the github. The latest tree can be found at
> https://source.codeaurora.org/external/qoriq/qoriq-components/linux/

Ah. FYI, googling "LSDK" gives https://lsdk.github.io as one of the
first hits, and (apart from itself being a github url) that says on the
front page "Disaggregated components of LSDK are available in github.".
But yes, navigating to the Components tab and from there to lsdk linux
one does get directed at codeaurora.

>> In any case, we have zero interest in running an NXP kernel. Maybe I
>> should clarify what I meant by "based on commits from" above: We're
>> currently running a mainline 4.14 kernel on LS1021A, with a few patches
>> inspired from the NXP 4.1 branch applied on top - but also with some
>> manual fixes for e.g. the pvr_version_is() issue. Now we want to move
>> that to a 4.19-based kernel (so that it aligns with our MPC8309 platform).
>
> We also provide 4.19 based kernel in the codeaurora repo. I think it
> will be helpful to reuse patches there if you want to make your own
> tree.

Again, we don't want to run off an NXP kernel, we want to get the
necessary pieces upstream. For now, we have to live with a patched 4.19
kernel, but hopefully by the time we switch to 5.x (for some x >= 5) we
don't need to supply anything other than our own .dts and defconfig.

>> Yes, as I said, I wanted to try a fresh approach since Zhao
>> Qiang's patches seemed to be getting nowhere. Splitting the patches into
>> smaller pieces is definitely part of that - for example, the completely
>> trivial whitespace fix in patch 1 is to make sure the later coccinelle
>> generated patch is precisely that (i.e., a later respin can just rerun
>> the coccinelle script, with zero manual fixups). I also want to avoid
>> mixing the ppcism cleanups with other things (e.g. replacing some
>> of_get_property() by of_property_read_u32()). And the "testing on ARM"
>> part comes once I get to actually building on ARM. But there's not much
>> point doing all that unless there's some indication that this can be
>> applied to some tree that actually feeds into Linus', which is why I
>> started with a few trivial patches and precisely to start this discussion.
>
> Right. I'm really interested in getting this applied to my tree and
> make it upstream. Zhao Qiang, can you help to review Rasmus's patches
> and comment?

Thanks, this is exactly what I was hoping for. Even just getting these
first rather trivial patches (in that they don't attempt to build for
ARM, or change functionality at all for PPC) merged for 5.5 would reduce
the amount of out-of-tree patches that we (and NXP for that matter)
would have to carry. I'll take the above as a go-ahead for me to try to
post more patches working towards enabling some of the QE drivers for ARM.

Rasmus

2019-10-22 13:05:22

by Rasmus Villemoes

Subject: Re: [PATCH 0/7] towards QE support on ARM

On 22/10/2019 04.24, Qiang Zhao wrote:
> On Mon, Oct 22, 2019 at 6:11 AM Leo Li wrote

>> Right. I'm really interested in getting this applied to my tree and make it
>> upstream. Zhao Qiang, can you help to review Rasmus's patches and
>> comment?
>
> As you know, I maintained a similar patchset removing PPC, and someone told me qe_ic should moved into drivers/irqchip/.
> I also thought qe_ic is a interrupt control driver, should be moved into dir irqchip.

Yes, and I also plan to do that at some point. However, that's
orthogonal to making the driver build on ARM, so I don't want to mix the
two. Making it usable on ARM is my/our priority currently.

I'd appreciate your input on my patches.

Rasmus

2019-10-22 16:52:19

by Christophe Leroy

Subject: Re: [PATCH 3/7] soc: fsl: qe: avoid ppc-specific io accessors

On 10/18/2019 12:52 PM, Rasmus Villemoes wrote:
> In preparation for allowing to build QE support for architectures
> other than PPC, replace the ppc-specific io accessors. Done via
>

This patch is not transparent in terms of performance, functions get
changed significantly.

Before the patch:

00000330 <ucc_fast_enable>:
330: 81 43 00 04 lwz r10,4(r3)
334: 7c 00 04 ac hwsync
338: 81 2a 00 00 lwz r9,0(r10)
33c: 0c 09 00 00 twi 0,r9,0
340: 4c 00 01 2c isync
344: 70 88 00 02 andi. r8,r4,2
348: 41 82 00 10 beq 358 <ucc_fast_enable+0x28>
34c: 39 00 00 01 li r8,1
350: 91 03 00 10 stw r8,16(r3)
354: 61 29 00 10 ori r9,r9,16
358: 70 88 00 01 andi. r8,r4,1
35c: 41 82 00 10 beq 36c <ucc_fast_enable+0x3c>
360: 39 00 00 01 li r8,1
364: 91 03 00 14 stw r8,20(r3)
368: 61 29 00 20 ori r9,r9,32
36c: 7c 00 04 ac hwsync
370: 91 2a 00 00 stw r9,0(r10)
374: 4e 80 00 20 blr

After the patch:

0000030c <ucc_fast_enable>:
30c: 94 21 ff e0 stwu r1,-32(r1)
310: 7c 08 02 a6 mflr r0
314: bf a1 00 14 stmw r29,20(r1)
318: 7c 9f 23 78 mr r31,r4
31c: 90 01 00 24 stw r0,36(r1)
320: 7c 7e 1b 78 mr r30,r3
324: 83 a3 00 04 lwz r29,4(r3)
328: 7f a3 eb 78 mr r3,r29
32c: 48 00 00 01 bl 32c <ucc_fast_enable+0x20>
32c: R_PPC_REL24 ioread32be
330: 73 e9 00 02 andi. r9,r31,2
334: 41 82 00 10 beq 344 <ucc_fast_enable+0x38>
338: 39 20 00 01 li r9,1
33c: 91 3e 00 10 stw r9,16(r30)
340: 60 63 00 10 ori r3,r3,16
344: 73 e9 00 01 andi. r9,r31,1
348: 41 82 00 10 beq 358 <ucc_fast_enable+0x4c>
34c: 39 20 00 01 li r9,1
350: 91 3e 00 14 stw r9,20(r30)
354: 60 63 00 20 ori r3,r3,32
358: 80 01 00 24 lwz r0,36(r1)
35c: 7f a4 eb 78 mr r4,r29
360: bb a1 00 14 lmw r29,20(r1)
364: 7c 08 03 a6 mtlr r0
368: 38 21 00 20 addi r1,r1,32
36c: 48 00 00 00 b 36c <ucc_fast_enable+0x60>
36c: R_PPC_REL24 iowrite32be


Christophe

2019-10-22 16:52:52

by Christophe Leroy

Subject: Re: [PATCH 0/7] towards QE support on ARM

On 10/18/2019 12:52 PM, Rasmus Villemoes wrote:
> There have been several attempts in the past few years to allow
> building the QUICC engine drivers for platforms other than PPC. This
> is (the beginning of) yet another attempt. I hope I can get someone to
> pick up these relatively trivial patches (I _think_ they shouldn't
> change functionality at all), and then I'll continue slowly working
> towards removing the PPC32 dependency for CONFIG_QUICC_ENGINE.
>
> Tested on an MPC8309-derived board.
>
> Rasmus Villemoes (7):
> soc: fsl: qe: remove space-before-tab
> soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs
> soc: fsl: qe: avoid ppc-specific io accessors
> soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic
> serial: make SERIAL_QE depend on PPC32
> serial: ucc_uart.c: explicitly include asm/cpm.h
> soc/fsl/qe/qe.h: remove include of asm/cpm.h

Please copy the entire series to linuxppc-dev list. We are missing 5/7
and 7/7 (see
https://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=137048)

Christophe

>
> drivers/soc/fsl/qe/gpio.c | 30 ++++++++--------
> drivers/soc/fsl/qe/qe.c | 44 +++++++++++------------
> drivers/soc/fsl/qe/qe_ic.c | 8 ++---
> drivers/soc/fsl/qe/qe_ic.h | 2 +-
> drivers/soc/fsl/qe/qe_io.c | 40 ++++++++++-----------
> drivers/soc/fsl/qe/qe_tdm.c | 8 ++---
> drivers/soc/fsl/qe/ucc.c | 12 +++----
> drivers/soc/fsl/qe/ucc_fast.c | 66 ++++++++++++++++++-----------------
> drivers/soc/fsl/qe/ucc_slow.c | 38 ++++++++++----------
> drivers/soc/fsl/qe/usb.c | 2 +-
> drivers/tty/serial/Kconfig | 1 +
> drivers/tty/serial/ucc_uart.c | 1 +
> include/soc/fsl/qe/qe.h | 1 -
> 13 files changed, 126 insertions(+), 127 deletions(-)
>

2019-10-23 03:58:03

by Zhao Qiang

Subject: RE: [PATCH 0/7] towards QE support on ARM

On 22/10/2019 18:18, Rasmus Villemoes <[email protected]> wrote:
> -----Original Message-----
> From: Rasmus Villemoes <[email protected]>
> Sent: 2019年10月22日 18:18
> To: Qiang Zhao <[email protected]>; Leo Li <[email protected]>
> Cc: Timur Tabi <[email protected]>; Greg Kroah-Hartman
> <[email protected]>; [email protected];
> [email protected]; Jiri Slaby <[email protected]>;
> [email protected]; [email protected]
> Subject: Re: [PATCH 0/7] towards QE support on ARM
>
> On 22/10/2019 04.24, Qiang Zhao wrote:
> > On Mon, Oct 22, 2019 at 6:11 AM Leo Li wrote
>
> >> Right. I'm really interested in getting this applied to my tree and
> >> make it upstream. Zhao Qiang, can you help to review Rasmus's
> >> patches and comment?
> >
> > As you know, I maintained a similar patchset removing PPC, and someone
> told me qe_ic should moved into drivers/irqchip/.
> > I also thought qe_ic is a interrupt control driver, should be moved into dir
> irqchip.
>
> Yes, and I also plan to do that at some point. However, that's orthogonal to
> making the driver build on ARM, so I don't want to mix the two. Making it
> usable on ARM is my/our priority currently.
>
> I'd appreciate your input on my patches.

Yes, we can put this patchset in first place, ensure it can build and work on ARM, then push another patchset to move qe_ic.

Best Regards,
Qiang

2019-10-23 07:10:33

by Rasmus Villemoes

Subject: Re: [PATCH 3/7] soc: fsl: qe: avoid ppc-specific io accessors

On 22/10/2019 17.01, Christophe Leroy wrote:
>
>
> On 10/18/2019 12:52 PM, Rasmus Villemoes wrote:
>> In preparation for allowing to build QE support for architectures
>> other than PPC, replace the ppc-specific io accessors. Done via
>>
>
> This patch is not transparent in terms of performance, functions get
> changed significantly.
>
> Before the patch:
>
> 00000330 <ucc_fast_enable>:
>  330:    81 43 00 04     lwz     r10,4(r3)
>  334:    7c 00 04 ac     hwsync
>  338:    81 2a 00 00     lwz     r9,0(r10)
>  33c:    0c 09 00 00     twi     0,r9,0
>  340:    4c 00 01 2c     isync
>  344:    70 88 00 02     andi.   r8,r4,2
>  348:    41 82 00 10     beq     358 <ucc_fast_enable+0x28>
>  34c:    39 00 00 01     li      r8,1
>  350:    91 03 00 10     stw     r8,16(r3)
>  354:    61 29 00 10     ori     r9,r9,16
>  358:    70 88 00 01     andi.   r8,r4,1
>  35c:    41 82 00 10     beq     36c <ucc_fast_enable+0x3c>
>  360:    39 00 00 01     li      r8,1
>  364:    91 03 00 14     stw     r8,20(r3)
>  368:    61 29 00 20     ori     r9,r9,32
>  36c:    7c 00 04 ac     hwsync
>  370:    91 2a 00 00     stw     r9,0(r10)
>  374:    4e 80 00 20     blr
>
> After the patch:
>
> 0000030c <ucc_fast_enable>:
>  30c:    94 21 ff e0     stwu    r1,-32(r1)
>  310:    7c 08 02 a6     mflr    r0
>  314:    bf a1 00 14     stmw    r29,20(r1)
>  318:    7c 9f 23 78     mr      r31,r4
>  31c:    90 01 00 24     stw     r0,36(r1)
>  320:    7c 7e 1b 78     mr      r30,r3
>  324:    83 a3 00 04     lwz     r29,4(r3)
>  328:    7f a3 eb 78     mr      r3,r29
>  32c:    48 00 00 01     bl      32c <ucc_fast_enable+0x20>
>             32c: R_PPC_REL24    ioread32be
>  330:    73 e9 00 02     andi.   r9,r31,2
>  334:    41 82 00 10     beq     344 <ucc_fast_enable+0x38>
>  338:    39 20 00 01     li      r9,1
>  33c:    91 3e 00 10     stw     r9,16(r30)
>  340:    60 63 00 10     ori     r3,r3,16
>  344:    73 e9 00 01     andi.   r9,r31,1
>  348:    41 82 00 10     beq     358 <ucc_fast_enable+0x4c>
>  34c:    39 20 00 01     li      r9,1
>  350:    91 3e 00 14     stw     r9,20(r30)
>  354:    60 63 00 20     ori     r3,r3,32
>  358:    80 01 00 24     lwz     r0,36(r1)
>  35c:    7f a4 eb 78     mr      r4,r29
>  360:    bb a1 00 14     lmw     r29,20(r1)
>  364:    7c 08 03 a6     mtlr    r0
>  368:    38 21 00 20     addi    r1,r1,32
>  36c:    48 00 00 00     b       36c <ucc_fast_enable+0x60>
>             36c: R_PPC_REL24    iowrite32be

True. Do you know why powerpc uses out-of-line versions of these
accessors when !PPC_INDIRECT_PIO, i.e. at least all of PPC32? It's quite
a bit beyond the scope of this series, but I'd expect moving most if not
all of arch/powerpc/kernel/iomap.c into asm/io.h (guarded by
!defined(CONFIG_PPC_INDIRECT_PIO) of course) as static inlines would
benefit all ppc32 users of iowrite32 and friends.

Is there some other primitive available that (a) is defined on all
architectures (or at least both ppc and arm) and (b) expands to good
code in both/all cases?

Note that a few uses of the the iowrite32be accessors has already
appeared in the qe code with the introduction of the qe_clrsetbits()
helpers in bb8b2062af.

Rasmus

2019-10-24 23:09:52

by Rasmus Villemoes

Subject: Re: [PATCH 4/7] soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic

On 18/10/2019 18.08, Christoph Hellwig wrote:
> On Fri, Oct 18, 2019 at 02:52:31PM +0200, Rasmus Villemoes wrote:
>> /* wait for the QE_CR_FLG to clear */
>> - ret = spin_event_timeout((ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
>> - 100, 0);
>> - /* On timeout (e.g. failure), the expression will be false (ret == 0),
>> - otherwise it will be true (ret == 1). */
>> + ret = readx_poll_timeout_atomic(ioread32be, &qe_immr->cp.cecr, val, (val & QE_CR_FLG) == 0,
>
> This creates an overly long line.

Yeah, readx_poll_timeout_atomic is a mouthful, and then one also has to
put in the name of the accessor... I'll wrap it when I respin the
series, thanks.

> Btw, given how few users of spin_event_timeout we have it might be good
> idea to just kill it entirely.

Maybe. That's for the ppc folks to comment on; the iopoll.h helpers are
not completely equivalent (because obviously they don't read tbl
directly). Maybe the generic versions should be taught
spin_begin/spin_end/spin_cpu_relax so at least that part would be
drop-in replacement.

Rasmus

2019-10-25 19:02:08

by Leo Li

Subject: Re: [PATCH 0/7] towards QE support on ARM

On Tue, Oct 22, 2019 at 9:54 PM Qiang Zhao <[email protected]> wrote:
>
> On 22/10/2019 18:18, Rasmus Villemoes <[email protected]> wrote:
> > -----Original Message-----
> > From: Rasmus Villemoes <[email protected]>
> > Sent: 2019年10月22日 18:18
> > To: Qiang Zhao <[email protected]>; Leo Li <[email protected]>
> > Cc: Timur Tabi <[email protected]>; Greg Kroah-Hartman
> > <[email protected]>; [email protected];
> > [email protected]; Jiri Slaby <[email protected]>;
> > [email protected]; [email protected]
> > Subject: Re: [PATCH 0/7] towards QE support on ARM
> >
> > On 22/10/2019 04.24, Qiang Zhao wrote:
> > > On Mon, Oct 22, 2019 at 6:11 AM Leo Li wrote
> >
> > >> Right. I'm really interested in getting this applied to my tree and
> > >> make it upstream. Zhao Qiang, can you help to review Rasmus's
> > >> patches and comment?
> > >
> > > As you know, I maintained a similar patchset removing PPC, and someone
> > told me qe_ic should moved into drivers/irqchip/.
> > > I also thought qe_ic is a interrupt control driver, should be moved into dir
> > irqchip.
> >
> > Yes, and I also plan to do that at some point. However, that's orthogonal to
> > making the driver build on ARM, so I don't want to mix the two. Making it
> > usable on ARM is my/our priority currently.
> >
> > I'd appreciate your input on my patches.
>
> Yes, we can put this patchset in first place, ensure it can build and work on ARM, then push another patchset to move qe_ic.

Right. I would only accept a patch series that can really build and
work on ARM. At least the current out-of-tree patches can make it
work on ARM. If we accept partial changes, there is no way to make it
work on the latest kernel on ARM then.

Regards,
Leo

2019-10-25 20:09:27

by Rasmus Villemoes

Subject: [PATCH v2 00/23] QUICC Engine support on ARM

There have been several attempts in the past few years to allow
building the QUICC engine drivers for platforms other than PPC. This
is yet another attempt.

In v2, I've fixed a few style issues. But more importantly, it now
contains enough to actually remove the PPC32 dependency from
CONFIG_QUICC_ENGINE, so that's what the last patch does.

I haven't found a way to address Christophe's concern over the
performance impact of using the (on powerpc) out-of-line iowrite32be
instead of out_be32. I could of course introduce some qe_ prefixed
helpers (similar to the already added qe_clrsetbits ones) and make
their definition dependent on PPC32 or not, but that seems to be a bit
ugly.

Rasmus Villemoes (23):
soc: fsl: qe: remove space-before-tab
soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs
soc: fsl: qe: avoid ppc-specific io accessors
soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic
soc: fsl: qe: qe.c: guard use of pvr_version_is() with CONFIG_PPC32
soc: fsl: qe: avoid tail comments in qe_ic.h
soc: fsl: qe: merge qe_ic.h into qe_ic.c
soc: fsl: qe: drop unneeded #includes
soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c
soc: fsl: qe: use qe_ic_cascade_{low,high}_mpic also on 83xx
soc: fsl: qe: rename qe_ic_cascade_low_mpic -> qe_ic_cascade_low
soc: fsl: qe: drop assign-only high_active in qe_ic_init
soc: fsl: qe: remove pointless sysfs registration in qe_ic.c
soc: fsl: qe: move calls of qe_ic_init out of arch/powerpc/
powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQ
powerpc/85xx: remove mostly pointless mpc85xx_qe_init()
soc: fsl: qe: make qe_ic_cascade_* static
soc: fsl: qe: remove unused qe_ic_set_* functions
net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32
serial: make SERIAL_QE depend on PPC32
serial: ucc_uart.c: explicitly include asm/cpm.h
soc/fsl/qe/qe.h: remove include of asm/cpm.h
soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE

arch/powerpc/platforms/83xx/km83xx.c | 3 +-
arch/powerpc/platforms/83xx/misc.c | 23 --
arch/powerpc/platforms/83xx/mpc832x_mds.c | 3 +-
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 3 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c | 3 +-
arch/powerpc/platforms/83xx/mpc836x_rdk.c | 3 +-
arch/powerpc/platforms/83xx/mpc83xx.h | 7 -
arch/powerpc/platforms/85xx/common.c | 23 --
arch/powerpc/platforms/85xx/corenet_generic.c | 12 -
arch/powerpc/platforms/85xx/mpc85xx.h | 2 -
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 28 --
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 18 --
arch/powerpc/platforms/85xx/twr_p102x.c | 16 -
drivers/net/ethernet/freescale/Kconfig | 1 +
drivers/soc/fsl/qe/Kconfig | 2 +-
drivers/soc/fsl/qe/gpio.c | 30 +-
drivers/soc/fsl/qe/qe.c | 59 ++--
drivers/soc/fsl/qe/qe_ic.c | 289 ++++++++++--------
drivers/soc/fsl/qe/qe_ic.h | 99 ------
drivers/soc/fsl/qe/qe_io.c | 42 ++-
drivers/soc/fsl/qe/qe_tdm.c | 8 +-
drivers/soc/fsl/qe/ucc.c | 16 +-
drivers/soc/fsl/qe/ucc_fast.c | 70 ++---
drivers/soc/fsl/qe/ucc_slow.c | 38 +--
drivers/soc/fsl/qe/usb.c | 2 +-
drivers/tty/serial/Kconfig | 1 +
drivers/tty/serial/ucc_uart.c | 1 +
include/soc/fsl/qe/qe.h | 1 -
include/soc/fsl/qe/qe_ic.h | 69 -----
29 files changed, 299 insertions(+), 573 deletions(-)
delete mode 100644 drivers/soc/fsl/qe/qe_ic.h

--
2.23.0

2019-10-25 20:09:44

by Rasmus Villemoes

Subject: [PATCH v2 02/23] soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs

The actual io accessors (e.g. in_be32) implicitly add a volatile
qualifier to their address argument. Remove volatile from the struct
definition and the qe_ic_(read/write) helpers, in preparation for
switching from the ppc-specific io accessors to generic ones.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe_ic.c | 4 ++--
drivers/soc/fsl/qe/qe_ic.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 9bac546998d3..791adcd121d1 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -171,12 +171,12 @@ static struct qe_ic_info qe_ic_info[] = {
},
};

-static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
+static inline u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)
{
return in_be32(base + (reg >> 2));
}

-static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
+static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg,
u32 value)
{
out_be32(base + (reg >> 2), value);
diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h
index 08c695672a03..9420378d9b6b 100644
--- a/drivers/soc/fsl/qe/qe_ic.h
+++ b/drivers/soc/fsl/qe/qe_ic.h
@@ -72,7 +72,7 @@

struct qe_ic {
/* Control registers offset */
- volatile u32 __iomem *regs;
+ u32 __iomem *regs;

/* The remapper for this QEIC */
struct irq_domain *irqhost;
--
2.23.0

2019-10-25 20:09:55

by Rasmus Villemoes

Subject: [PATCH v2 21/23] serial: ucc_uart.c: explicitly include asm/cpm.h

This driver uses #defines from asm/cpm.h, so instead of relying on
some other header pulling that in, do that explicitly.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/tty/serial/ucc_uart.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index a0555ae2b1ef..e2c998badf81 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -33,6 +33,7 @@

#include <linux/firmware.h>
#include <asm/reg.h>
+#include <asm/cpm.h>

/*
* The GUMR flag for Soft UART. This would normally be defined in qe.h,
--
2.23.0

2019-10-25 20:10:10

by Rasmus Villemoes

Subject: [PATCH v2 20/23] serial: make SERIAL_QE depend on PPC32

Currently SERIAL_QE depends on QUICC_ENGINE, which in turn depends on
PPC32, so this doesn't add any extra dependency. However, the QUICC
Engine IP block also exists on some arm boards, so this serves as
preparation for removing the PPC32 dependency from QUICC_ENGINE and
build the QE support in drivers/soc/fsl/qe, while preventing
allmodconfig/randconfig failures due to SERIAL_QE not being supported
yet.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/tty/serial/Kconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 67a9eb3f94ce..78246f535809 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1056,6 +1056,7 @@ config SERIAL_LANTIQ
config SERIAL_QE
tristate "Freescale QUICC Engine serial port support"
depends on QUICC_ENGINE
+ depends on PPC32
select SERIAL_CORE
select FW_LOADER
help
--
2.23.0

2019-10-25 20:10:17

by Rasmus Villemoes

Subject: [PATCH v2 05/23] soc: fsl: qe: qe.c: guard use of pvr_version_is() with CONFIG_PPC32

Commit e5c5c8d23fef (soc/fsl/qe: only apply QE_General4 workaround on
affected SoCs) introduced use of pvr_version_is(), saying

The QE_General4 workaround is only valid for the MPC832x and MPC836x
SoCs. The other SoCs that embed a QUICC engine are not affected by this
hardware bug and thus can use the computed divisors (this was
successfully tested on the T1040).

I'm reading the above as saying that the errata does not apply to the
ARM-based SOCs with QUICC engine. In any case, use of pvr_version_is()
must be guarded by CONFIG_PPC32 before we can remove the PPC32
dependency from CONFIG_QUICC_ENGINE, so introduce qe_general4_errata()
to keep the necessary #ifdeffery localized to a trivial helper.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index bcdec37b25ca..0ddf83d8e3ce 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -197,6 +197,14 @@ EXPORT_SYMBOL(qe_get_brg_clk);
#define PVR_VER_836x 0x8083
#define PVR_VER_832x 0x8084

+static bool qe_general4_errata(void)
+{
+#ifdef CONFIG_PPC32
+ return pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x);
+#endif
+ return false;
+}
+
/* Program the BRG to the given sampling rate and multiplier
*
* @brg: the BRG, QE_BRG1 - QE_BRG16
@@ -223,7 +231,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
/* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
that the BRG divisor must be even if you're not using divide-by-16
mode. */
- if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
+ if (qe_general4_errata())
if (!div16 && (divisor & 1) && (divisor > 3))
divisor++;

--
2.23.0

2019-10-25 20:10:58

by Rasmus Villemoes

Subject: [PATCH v2 09/23] soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c

These functions are only ever called through a function pointer, and
therefore it makes no sense for them to be "static inline" - gcc has
no choice but to emit a copy in each translation unit that takes the
address of one of these (currently various platform code under
arch/powerpc/). So move them into qe_ic.c and leave ordinary extern
declarations in the header file.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe_ic.c | 58 +++++++++++++++++++++++++++++++++++
include/soc/fsl/qe/qe_ic.h | 62 +++-----------------------------------
2 files changed, 63 insertions(+), 57 deletions(-)

diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 7b1870d2866a..a847b2672e90 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -402,6 +402,64 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
return irq_linear_revmap(qe_ic->irqhost, irq);
}

+void qe_ic_cascade_low_ipic(struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
+ unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+}
+
+void qe_ic_cascade_high_ipic(struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
+ unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+}
+
+void qe_ic_cascade_low_mpic(struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
+ unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+
+ chip->irq_eoi(&desc->irq_data);
+}
+
+void qe_ic_cascade_high_mpic(struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
+ unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+
+ chip->irq_eoi(&desc->irq_data);
+}
+
+void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
+ unsigned int cascade_irq;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+
+ cascade_irq = qe_ic_get_high_irq(qe_ic);
+ if (cascade_irq == NO_IRQ)
+ cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+
+ chip->irq_eoi(&desc->irq_data);
+}
+
void __init qe_ic_init(struct device_node *node, unsigned int flags,
void (*low_handler)(struct irq_desc *desc),
void (*high_handler)(struct irq_desc *desc))
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index 714a9b890d8d..f3492eb13052 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -74,62 +74,10 @@ void qe_ic_set_highest_priority(unsigned int virq, int high);
int qe_ic_set_priority(unsigned int virq, unsigned int priority);
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);

-static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-}
-
-static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-}
-
-static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
- struct irq_chip *chip = irq_desc_get_chip(desc);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-
- chip->irq_eoi(&desc->irq_data);
-}
-
-static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
- struct irq_chip *chip = irq_desc_get_chip(desc);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-
- chip->irq_eoi(&desc->irq_data);
-}
-
-static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq;
- struct irq_chip *chip = irq_desc_get_chip(desc);
-
- cascade_irq = qe_ic_get_high_irq(qe_ic);
- if (cascade_irq == NO_IRQ)
- cascade_irq = qe_ic_get_low_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-
- chip->irq_eoi(&desc->irq_data);
-}
+void qe_ic_cascade_low_ipic(struct irq_desc *desc);
+void qe_ic_cascade_high_ipic(struct irq_desc *desc);
+void qe_ic_cascade_low_mpic(struct irq_desc *desc);
+void qe_ic_cascade_high_mpic(struct irq_desc *desc);
+void qe_ic_cascade_muxed_mpic(struct irq_desc *desc);

#endif /* _ASM_POWERPC_QE_IC_H */
--
2.23.0

2019-10-25 20:10:58

by Rasmus Villemoes

Subject: [PATCH v2 15/23] powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQ

This is now exactly the same as mpc83xx_ipic_init_IRQ, so just use
that directly.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
arch/powerpc/platforms/83xx/km83xx.c | 2 +-
arch/powerpc/platforms/83xx/misc.c | 7 -------
arch/powerpc/platforms/83xx/mpc832x_mds.c | 2 +-
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 2 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +-
arch/powerpc/platforms/83xx/mpc836x_rdk.c | 2 +-
arch/powerpc/platforms/83xx/mpc83xx.h | 5 -----
7 files changed, 5 insertions(+), 17 deletions(-)

diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
index 5c6227f7bc37..3d89569e9e71 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -177,7 +177,7 @@ define_machine(mpc83xx_km) {
.name = "mpc83xx-km-platform",
.probe = mpc83xx_km_probe,
.setup_arch = mpc83xx_km_setup_arch,
- .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
+ .init_IRQ = mpc83xx_ipic_init_IRQ,
.get_irq = ipic_get_irq,
.restart = mpc83xx_restart,
.time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c
index 6935a5b9fbd1..1d8306eb2958 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -88,13 +88,6 @@ void __init mpc83xx_ipic_init_IRQ(void)
ipic_set_default_priority();
}

-#ifdef CONFIG_QUICC_ENGINE
-void __init mpc83xx_ipic_and_qe_init_IRQ(void)
-{
- mpc83xx_ipic_init_IRQ();
-}
-#endif /* CONFIG_QUICC_ENGINE */
-
static const struct of_device_id of_bus_ids[] __initconst = {
{ .type = "soc", },
{ .compatible = "soc", },
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index 1c73af104d19..6fa5402ebf20 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -101,7 +101,7 @@ define_machine(mpc832x_mds) {
.name = "MPC832x MDS",
.probe = mpc832x_sys_probe,
.setup_arch = mpc832x_sys_setup_arch,
- .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
+ .init_IRQ = mpc83xx_ipic_init_IRQ,
.get_irq = ipic_get_irq,
.restart = mpc83xx_restart,
.time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index 87f68ca06255..622c625d5ce4 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -219,7 +219,7 @@ define_machine(mpc832x_rdb) {
.name = "MPC832x RDB",
.probe = mpc832x_rdb_probe,
.setup_arch = mpc832x_rdb_setup_arch,
- .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
+ .init_IRQ = mpc83xx_ipic_init_IRQ,
.get_irq = ipic_get_irq,
.restart = mpc83xx_restart,
.time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 5b484da9533e..219a83ab6c00 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -208,7 +208,7 @@ define_machine(mpc836x_mds) {
.name = "MPC836x MDS",
.probe = mpc836x_mds_probe,
.setup_arch = mpc836x_mds_setup_arch,
- .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
+ .init_IRQ = mpc83xx_ipic_init_IRQ,
.get_irq = ipic_get_irq,
.restart = mpc83xx_restart,
.time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
index b7119e443920..b4aac2cde849 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
@@ -41,7 +41,7 @@ define_machine(mpc836x_rdk) {
.name = "MPC836x RDK",
.probe = mpc836x_rdk_probe,
.setup_arch = mpc836x_rdk_setup_arch,
- .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
+ .init_IRQ = mpc83xx_ipic_init_IRQ,
.get_irq = ipic_get_irq,
.restart = mpc83xx_restart,
.time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index d343f6ce2599..f37d04332fc7 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -72,11 +72,6 @@ extern int mpc837x_usb_cfg(void);
extern int mpc834x_usb_cfg(void);
extern int mpc831x_usb_cfg(void);
extern void mpc83xx_ipic_init_IRQ(void);
-#ifdef CONFIG_QUICC_ENGINE
-extern void mpc83xx_ipic_and_qe_init_IRQ(void);
-#else
-#define mpc83xx_ipic_and_qe_init_IRQ mpc83xx_ipic_init_IRQ
-#endif /* CONFIG_QUICC_ENGINE */

#ifdef CONFIG_PCI
extern void mpc83xx_setup_pci(void);
--
2.23.0

2019-10-25 20:11:01

by Rasmus Villemoes

Subject: [PATCH v2 03/23] soc: fsl: qe: avoid ppc-specific io accessors

In preparation for allowing to build QE support for architectures
other than PPC, replace the ppc-specific io accessors. Done via

$ spatch --sp-file io.cocci --in-place drivers/soc/fsl/qe/

where io.cocci is

@@
expression addr, val;
@@
- out_be32(addr, val)
+ iowrite32be(val, addr)

@@
expression addr;
@@
- in_be32(addr)
+ ioread32be(addr)

@@
expression addr, val;
@@
- out_be16(addr, val)
+ iowrite16be(val, addr)

@@
expression addr;
@@
- in_be16(addr)
+ ioread16be(addr)

@@
expression addr, val;
@@
- out_8(addr, val)
+ iowrite8(val, addr)

@@
expression addr;
@@
- in_8(addr)
+ ioread8(addr)

@@
expression addr, clr, set;
@@
- clrsetbits_be32(addr, clr, set)
+ qe_clrsetbits32(addr, clr, set)

@@
expression addr, clr, set;
@@
- clrsetbits_be16(addr, clr, set)
+ qe_clrsetbits16(addr, clr, set)

@@
expression addr, clr, set;
@@
- clrsetbits_8(addr, clr, set)
+ qe_clrsetbits8(addr, clr, set)

@@
expression addr, set;
@@
- setbits32(addr, set)
+ qe_setbits32(addr, set)

@@
expression addr, set;
@@
- setbits16(addr, set)
+ qe_setbits16(addr, set)

@@
expression addr, set;
@@
- setbits8(addr, set)
+ qe_setbits8(addr, set)

@@
expression addr, clr;
@@
- clrbits32(addr, clr)
+ qe_clrbits32(addr, clr)

@@
expression addr, clr;
@@
- clrbits16(addr, clr)
+ qe_clrbits16(addr, clr)

@@
expression addr, clr;
@@
- clrbits8(addr, clr)
+ qe_clrbits8(addr, clr)

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/gpio.c | 30 +++++++--------
drivers/soc/fsl/qe/qe.c | 35 +++++++++---------
drivers/soc/fsl/qe/qe_ic.c | 4 +-
drivers/soc/fsl/qe/qe_io.c | 40 +++++++++-----------
drivers/soc/fsl/qe/qe_tdm.c | 8 ++--
drivers/soc/fsl/qe/ucc.c | 16 ++++----
drivers/soc/fsl/qe/ucc_fast.c | 70 ++++++++++++++++++-----------------
drivers/soc/fsl/qe/ucc_slow.c | 38 +++++++++----------
drivers/soc/fsl/qe/usb.c | 2 +-
9 files changed, 120 insertions(+), 123 deletions(-)

diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
index f0c29ed8f0ff..949a35ac253c 100644
--- a/drivers/soc/fsl/qe/gpio.c
+++ b/drivers/soc/fsl/qe/gpio.c
@@ -41,13 +41,13 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
container_of(mm_gc, struct qe_gpio_chip, mm_gc);
struct qe_pio_regs __iomem *regs = mm_gc->regs;

- qe_gc->cpdata = in_be32(&regs->cpdata);
+ qe_gc->cpdata = ioread32be(&regs->cpdata);
qe_gc->saved_regs.cpdata = qe_gc->cpdata;
- qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
- qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
- qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
- qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
- qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
+ qe_gc->saved_regs.cpdir1 = ioread32be(&regs->cpdir1);
+ qe_gc->saved_regs.cpdir2 = ioread32be(&regs->cpdir2);
+ qe_gc->saved_regs.cppar1 = ioread32be(&regs->cppar1);
+ qe_gc->saved_regs.cppar2 = ioread32be(&regs->cppar2);
+ qe_gc->saved_regs.cpodr = ioread32be(&regs->cpodr);
}

static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
@@ -56,7 +56,7 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
struct qe_pio_regs __iomem *regs = mm_gc->regs;
u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);

- return !!(in_be32(&regs->cpdata) & pin_mask);
+ return !!(ioread32be(&regs->cpdata) & pin_mask);
}

static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
@@ -74,7 +74,7 @@ static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
else
qe_gc->cpdata &= ~pin_mask;

- out_be32(&regs->cpdata, qe_gc->cpdata);
+ iowrite32be(qe_gc->cpdata, &regs->cpdata);

spin_unlock_irqrestore(&qe_gc->lock, flags);
}
@@ -101,7 +101,7 @@ static void qe_gpio_set_multiple(struct gpio_chip *gc,
}
}

- out_be32(&regs->cpdata, qe_gc->cpdata);
+ iowrite32be(qe_gc->cpdata, &regs->cpdata);

spin_unlock_irqrestore(&qe_gc->lock, flags);
}
@@ -255,11 +255,11 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)
spin_lock_irqsave(&qe_gc->lock, flags);

if (second_reg) {
- clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
- clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
+ qe_clrsetbits32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
+ qe_clrsetbits32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
} else {
- clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
- clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
+ qe_clrsetbits32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
+ qe_clrsetbits32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
}

if (sregs->cpdata & mask1)
@@ -267,8 +267,8 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)
else
qe_gc->cpdata &= ~mask1;

- out_be32(&regs->cpdata, qe_gc->cpdata);
- clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
+ iowrite32be(qe_gc->cpdata, &regs->cpdata);
+ qe_clrsetbits32(&regs->cpodr, mask1, sregs->cpodr & mask1);

spin_unlock_irqrestore(&qe_gc->lock, flags);
}
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 2a0e6e642776..60bf047001be 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -112,7 +112,7 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)

spin_lock_irqsave(&qe_lock, flags);
if (cmd == QE_RESET) {
- out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
+ iowrite32be((u32)(cmd | QE_CR_FLG), &qe_immr->cp.cecr);
} else {
if (cmd == QE_ASSIGN_PAGE) {
/* Here device is the SNUM, not sub-block */
@@ -129,15 +129,14 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
}

- out_be32(&qe_immr->cp.cecdr, cmd_input);
- out_be32(&qe_immr->cp.cecr,
- (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
- mcn_protocol << mcn_shift));
+ iowrite32be(cmd_input, &qe_immr->cp.cecdr);
+ iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) | (u32)mcn_protocol << mcn_shift),
+ &qe_immr->cp.cecr);
}

/* wait for the QE_CR_FLG to clear */
- ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
- 100, 0);
+ ret = spin_event_timeout((ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
+ 100, 0);
/* On timeout (e.g. failure), the expression will be false (ret == 0),
otherwise it will be true (ret == 1). */
spin_unlock_irqrestore(&qe_lock, flags);
@@ -230,7 +229,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
QE_BRGC_ENABLE | div16;

- out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
+ iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);

return 0;
}
@@ -377,9 +376,9 @@ static int qe_sdma_init(void)
return -ENOMEM;
}

- out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
- out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
- (0x1 << QE_SDMR_CEN_SHIFT)));
+ iowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK, &sdma->sdebcr);
+ iowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),
+ &sdma->sdmr);

return 0;
}
@@ -417,14 +416,14 @@ static void qe_upload_microcode(const void *base,
"uploading microcode '%s'\n", ucode->id);

/* Use auto-increment */
- out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
- QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
+ iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR,
+ &qe_immr->iram.iadd);

for (i = 0; i < be32_to_cpu(ucode->count); i++)
- out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
+ iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);

/* Set I-RAM Ready Register */
- out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));
+ iowrite32be(be32_to_cpu(QE_IRAM_READY), &qe_immr->iram.iready);
}

/*
@@ -509,7 +508,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
* If the microcode calls for it, split the I-RAM.
*/
if (!firmware->split)
- setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
+ qe_setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);

if (firmware->soc.model)
printk(KERN_INFO
@@ -543,11 +542,11 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
u32 trap = be32_to_cpu(ucode->traps[j]);

if (trap)
- out_be32(&qe_immr->rsp[i].tibcr[j], trap);
+ iowrite32be(trap, &qe_immr->rsp[i].tibcr[j]);
}

/* Enable traps */
- out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
+ iowrite32be(be32_to_cpu(ucode->eccr), &qe_immr->rsp[i].eccr);
}

qe_firmware_uploaded = 1;
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 791adcd121d1..d420492b4c23 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -173,13 +173,13 @@ static struct qe_ic_info qe_ic_info[] = {

static inline u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)
{
- return in_be32(base + (reg >> 2));
+ return ioread32be(base + (reg >> 2));
}

static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg,
u32 value)
{
- out_be32(base + (reg >> 2), value);
+ iowrite32be(value, base + (reg >> 2));
}

static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c
index 3657e296a8a2..776a2c9361e1 100644
--- a/drivers/soc/fsl/qe/qe_io.c
+++ b/drivers/soc/fsl/qe/qe_io.c
@@ -57,16 +57,16 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));

/* Set open drain, if required */
- tmp_val = in_be32(&par_io->cpodr);
+ tmp_val = ioread32be(&par_io->cpodr);
if (open_drain)
- out_be32(&par_io->cpodr, pin_mask1bit | tmp_val);
+ iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);
else
- out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val);
+ iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);

/* define direction */
tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
- in_be32(&par_io->cpdir2) :
- in_be32(&par_io->cpdir1);
+ ioread32be(&par_io->cpdir2) :
+ ioread32be(&par_io->cpdir1);

/* get all bits mask for 2 bit per port */
pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
@@ -78,34 +78,30 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,

/* clear and set 2 bits mask */
if (pin > (QE_PIO_PINS / 2) - 1) {
- out_be32(&par_io->cpdir2,
- ~pin_mask2bits & tmp_val);
+ iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io->cpdir2, new_mask2bits | tmp_val);
+ iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);
} else {
- out_be32(&par_io->cpdir1,
- ~pin_mask2bits & tmp_val);
+ iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io->cpdir1, new_mask2bits | tmp_val);
+ iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);
}
/* define pin assignment */
tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
- in_be32(&par_io->cppar2) :
- in_be32(&par_io->cppar1);
+ ioread32be(&par_io->cppar2) :
+ ioread32be(&par_io->cppar1);

new_mask2bits = (u32) (assignment << (QE_PIO_PINS -
(pin % (QE_PIO_PINS / 2) + 1) * 2));
/* clear and set 2 bits mask */
if (pin > (QE_PIO_PINS / 2) - 1) {
- out_be32(&par_io->cppar2,
- ~pin_mask2bits & tmp_val);
+ iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io->cppar2, new_mask2bits | tmp_val);
+ iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);
} else {
- out_be32(&par_io->cppar1,
- ~pin_mask2bits & tmp_val);
+ iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io->cppar1, new_mask2bits | tmp_val);
+ iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);
}
}
EXPORT_SYMBOL(__par_io_config_pin);
@@ -133,12 +129,12 @@ int par_io_data_set(u8 port, u8 pin, u8 val)
/* calculate pin location */
pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));

- tmp_val = in_be32(&par_io[port].cpdata);
+ tmp_val = ioread32be(&par_io[port].cpdata);

if (val == 0) /* clear */
- out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val);
+ iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);
else /* set */
- out_be32(&par_io[port].cpdata, pin_mask | tmp_val);
+ iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);

return 0;
}
diff --git a/drivers/soc/fsl/qe/qe_tdm.c b/drivers/soc/fsl/qe/qe_tdm.c
index e37ebc3be661..e7b1c8e3d229 100644
--- a/drivers/soc/fsl/qe/qe_tdm.c
+++ b/drivers/soc/fsl/qe/qe_tdm.c
@@ -169,10 +169,10 @@ void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)
&siram[siram_entry_id * 32 + 0x200 + i]);
}

- setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
- SIR_LAST);
- setbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],
- SIR_LAST);
+ qe_setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
+ SIR_LAST);
+ qe_setbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],
+ SIR_LAST);

/* Set SIxMR register */
sixmr = SIMR_SAD(siram_entry_id);
diff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c
index 024d239ac1e1..583d6b5aaf5c 100644
--- a/drivers/soc/fsl/qe/ucc.c
+++ b/drivers/soc/fsl/qe/ucc.c
@@ -35,8 +35,8 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
return -EINVAL;

spin_lock_irqsave(&cmxgcr_lock, flags);
- clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
- ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
+ qe_clrsetbits32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
+ ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
spin_unlock_irqrestore(&cmxgcr_lock, flags);

return 0;
@@ -80,8 +80,8 @@ int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
return -EINVAL;
}

- clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
- UCC_GUEMR_SET_RESERVED3 | speed);
+ qe_clrsetbits8(guemr, UCC_GUEMR_MODE_MASK,
+ UCC_GUEMR_SET_RESERVED3 | speed);

return 0;
}
@@ -109,9 +109,9 @@ int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);

if (set)
- setbits32(cmxucr, mask << shift);
+ qe_setbits32(cmxucr, mask << shift);
else
- clrbits32(cmxucr, mask << shift);
+ qe_clrbits32(cmxucr, mask << shift);

return 0;
}
@@ -207,8 +207,8 @@ int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
if (mode == COMM_DIR_RX)
shift += 4;

- clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
- clock_bits << shift);
+ qe_clrsetbits32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
+ clock_bits << shift);

return 0;
}
diff --git a/drivers/soc/fsl/qe/ucc_fast.c b/drivers/soc/fsl/qe/ucc_fast.c
index af4d80e38521..bda5222aadf3 100644
--- a/drivers/soc/fsl/qe/ucc_fast.c
+++ b/drivers/soc/fsl/qe/ucc_fast.c
@@ -29,41 +29,41 @@ void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);

printk(KERN_INFO "gumr : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
+ &uccf->uf_regs->gumr, ioread32be(&uccf->uf_regs->gumr));
printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
+ &uccf->uf_regs->upsmr, ioread32be(&uccf->uf_regs->upsmr));
printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
+ &uccf->uf_regs->utodr, ioread16be(&uccf->uf_regs->utodr));
printk(KERN_INFO "udsr : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
+ &uccf->uf_regs->udsr, ioread16be(&uccf->uf_regs->udsr));
printk(KERN_INFO "ucce : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
+ &uccf->uf_regs->ucce, ioread32be(&uccf->uf_regs->ucce));
printk(KERN_INFO "uccm : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
+ &uccf->uf_regs->uccm, ioread32be(&uccf->uf_regs->uccm));
printk(KERN_INFO "uccs : addr=0x%p, val=0x%02x\n",
- &uccf->uf_regs->uccs, in_8(&uccf->uf_regs->uccs));
+ &uccf->uf_regs->uccs, ioread8(&uccf->uf_regs->uccs));
printk(KERN_INFO "urfb : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
+ &uccf->uf_regs->urfb, ioread32be(&uccf->uf_regs->urfb));
printk(KERN_INFO "urfs : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
+ &uccf->uf_regs->urfs, ioread16be(&uccf->uf_regs->urfs));
printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
+ &uccf->uf_regs->urfet, ioread16be(&uccf->uf_regs->urfet));
printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset));
+ &uccf->uf_regs->urfset, ioread16be(&uccf->uf_regs->urfset));
printk(KERN_INFO "utfb : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
+ &uccf->uf_regs->utfb, ioread32be(&uccf->uf_regs->utfb));
printk(KERN_INFO "utfs : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
+ &uccf->uf_regs->utfs, ioread16be(&uccf->uf_regs->utfs));
printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
+ &uccf->uf_regs->utfet, ioread16be(&uccf->uf_regs->utfet));
printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
+ &uccf->uf_regs->utftt, ioread16be(&uccf->uf_regs->utftt));
printk(KERN_INFO "utpt : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
+ &uccf->uf_regs->utpt, ioread16be(&uccf->uf_regs->utpt));
printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
+ &uccf->uf_regs->urtry, ioread32be(&uccf->uf_regs->urtry));
printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",
- &uccf->uf_regs->guemr, in_8(&uccf->uf_regs->guemr));
+ &uccf->uf_regs->guemr, ioread8(&uccf->uf_regs->guemr));
}
EXPORT_SYMBOL(ucc_fast_dump_regs);

@@ -85,7 +85,7 @@ EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock);

void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
{
- out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
+ iowrite16be(UCC_FAST_TOD, &uccf->uf_regs->utodr);
}
EXPORT_SYMBOL(ucc_fast_transmit_on_demand);

@@ -97,7 +97,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
uf_regs = uccf->uf_regs;

/* Enable reception and/or transmission on this UCC. */
- gumr = in_be32(&uf_regs->gumr);
+ gumr = ioread32be(&uf_regs->gumr);
if (mode & COMM_DIR_TX) {
gumr |= UCC_FAST_GUMR_ENT;
uccf->enabled_tx = 1;
@@ -106,7 +106,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
gumr |= UCC_FAST_GUMR_ENR;
uccf->enabled_rx = 1;
}
- out_be32(&uf_regs->gumr, gumr);
+ iowrite32be(gumr, &uf_regs->gumr);
}
EXPORT_SYMBOL(ucc_fast_enable);

@@ -118,7 +118,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
uf_regs = uccf->uf_regs;

/* Disable reception and/or transmission on this UCC. */
- gumr = in_be32(&uf_regs->gumr);
+ gumr = ioread32be(&uf_regs->gumr);
if (mode & COMM_DIR_TX) {
gumr &= ~UCC_FAST_GUMR_ENT;
uccf->enabled_tx = 0;
@@ -127,7 +127,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
gumr &= ~UCC_FAST_GUMR_ENR;
uccf->enabled_rx = 0;
}
- out_be32(&uf_regs->gumr, gumr);
+ iowrite32be(gumr, &uf_regs->gumr);
}
EXPORT_SYMBOL(ucc_fast_disable);

@@ -259,7 +259,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
gumr |= uf_info->tenc;
gumr |= uf_info->tcrc;
gumr |= uf_info->mode;
- out_be32(&uf_regs->gumr, gumr);
+ iowrite32be(gumr, &uf_regs->gumr);

/* Allocate memory for Tx Virtual Fifo */
uccf->ucc_fast_tx_virtual_fifo_base_offset =
@@ -286,15 +286,17 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
}

/* Set Virtual Fifo registers */
- out_be16(&uf_regs->urfs, uf_info->urfs);
- out_be16(&uf_regs->urfet, uf_info->urfet);
- out_be16(&uf_regs->urfset, uf_info->urfset);
- out_be16(&uf_regs->utfs, uf_info->utfs);
- out_be16(&uf_regs->utfet, uf_info->utfet);
- out_be16(&uf_regs->utftt, uf_info->utftt);
+ iowrite16be(uf_info->urfs, &uf_regs->urfs);
+ iowrite16be(uf_info->urfet, &uf_regs->urfet);
+ iowrite16be(uf_info->urfset, &uf_regs->urfset);
+ iowrite16be(uf_info->utfs, &uf_regs->utfs);
+ iowrite16be(uf_info->utfet, &uf_regs->utfet);
+ iowrite16be(uf_info->utftt, &uf_regs->utftt);
/* utfb, urfb are offsets from MURAM base */
- out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);
- out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);
+ iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset,
+ &uf_regs->utfb);
+ iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset,
+ &uf_regs->urfb);

/* Mux clocking */
/* Grant Support */
@@ -362,14 +364,14 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
}

/* Set interrupt mask register at UCC level. */
- out_be32(&uf_regs->uccm, uf_info->uccm_mask);
+ iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);

/* First, clear anything pending at UCC level,
* otherwise, old garbage may come through
* as soon as the dam is opened. */

/* Writing '1' clears */
- out_be32(&uf_regs->ucce, 0xffffffff);
+ iowrite32be(0xffffffff, &uf_regs->ucce);

*uccf_ret = uccf;
return 0;
diff --git a/drivers/soc/fsl/qe/ucc_slow.c b/drivers/soc/fsl/qe/ucc_slow.c
index 34f0ec3a63b5..74213f8b361c 100644
--- a/drivers/soc/fsl/qe/ucc_slow.c
+++ b/drivers/soc/fsl/qe/ucc_slow.c
@@ -78,7 +78,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
us_regs = uccs->us_regs;

/* Enable reception and/or transmission on this UCC. */
- gumr_l = in_be32(&us_regs->gumr_l);
+ gumr_l = ioread32be(&us_regs->gumr_l);
if (mode & COMM_DIR_TX) {
gumr_l |= UCC_SLOW_GUMR_L_ENT;
uccs->enabled_tx = 1;
@@ -87,7 +87,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
gumr_l |= UCC_SLOW_GUMR_L_ENR;
uccs->enabled_rx = 1;
}
- out_be32(&us_regs->gumr_l, gumr_l);
+ iowrite32be(gumr_l, &us_regs->gumr_l);
}
EXPORT_SYMBOL(ucc_slow_enable);

@@ -99,7 +99,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
us_regs = uccs->us_regs;

/* Disable reception and/or transmission on this UCC. */
- gumr_l = in_be32(&us_regs->gumr_l);
+ gumr_l = ioread32be(&us_regs->gumr_l);
if (mode & COMM_DIR_TX) {
gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
uccs->enabled_tx = 0;
@@ -108,7 +108,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
uccs->enabled_rx = 0;
}
- out_be32(&us_regs->gumr_l, gumr_l);
+ iowrite32be(gumr_l, &us_regs->gumr_l);
}
EXPORT_SYMBOL(ucc_slow_disable);

@@ -198,7 +198,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
return ret;
}

- out_be16(&uccs->us_pram->mrblr, us_info->max_rx_buf_length);
+ iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr);

INIT_LIST_HEAD(&uccs->confQ);

@@ -228,27 +228,27 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) {
/* clear bd buffer */
- out_be32(&bd->buf, 0);
+ iowrite32be(0, &bd->buf);
/* set bd status and length */
- out_be32((u32 *) bd, 0);
+ iowrite32be(0, (u32 *)bd);
bd++;
}
/* for last BD set Wrap bit */
- out_be32(&bd->buf, 0);
- out_be32((u32 *) bd, cpu_to_be32(T_W));
+ iowrite32be(0, &bd->buf);
+ iowrite32be(cpu_to_be32(T_W), (u32 *)bd);

/* Init Rx bds */
bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {
/* set bd status and length */
- out_be32((u32*)bd, 0);
+ iowrite32be(0, (u32 *)bd);
/* clear bd buffer */
- out_be32(&bd->buf, 0);
+ iowrite32be(0, &bd->buf);
bd++;
}
/* for last BD set Wrap bit */
- out_be32((u32*)bd, cpu_to_be32(R_W));
- out_be32(&bd->buf, 0);
+ iowrite32be(cpu_to_be32(R_W), (u32 *)bd);
+ iowrite32be(0, &bd->buf);

/* Set GUMR (For more details see the hardware spec.). */
/* gumr_h */
@@ -269,7 +269,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
gumr |= UCC_SLOW_GUMR_H_TXSY;
if (us_info->rtsm)
gumr |= UCC_SLOW_GUMR_H_RTSM;
- out_be32(&us_regs->gumr_h, gumr);
+ iowrite32be(gumr, &us_regs->gumr_h);

/* gumr_l */
gumr = us_info->tdcr | us_info->rdcr | us_info->tenc | us_info->renc |
@@ -282,7 +282,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
gumr |= UCC_SLOW_GUMR_L_TINV;
if (us_info->tend)
gumr |= UCC_SLOW_GUMR_L_TEND;
- out_be32(&us_regs->gumr_l, gumr);
+ iowrite32be(gumr, &us_regs->gumr_l);

/* Function code registers */

@@ -292,8 +292,8 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
uccs->us_pram->rbmr = UCC_BMR_BO_BE;

/* rbase, tbase are offsets from MURAM base */
- out_be16(&uccs->us_pram->rbase, uccs->rx_base_offset);
- out_be16(&uccs->us_pram->tbase, uccs->tx_base_offset);
+ iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase);
+ iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase);

/* Mux clocking */
/* Grant Support */
@@ -323,14 +323,14 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
}

/* Set interrupt mask register at UCC level. */
- out_be16(&us_regs->uccm, us_info->uccm_mask);
+ iowrite16be(us_info->uccm_mask, &us_regs->uccm);

/* First, clear anything pending at UCC level,
* otherwise, old garbage may come through
* as soon as the dam is opened. */

/* Writing '1' clears */
- out_be16(&us_regs->ucce, 0xffff);
+ iowrite16be(0xffff, &us_regs->ucce);

/* Issue QE Init command */
if (us_info->init_tx && us_info->init_rx)
diff --git a/drivers/soc/fsl/qe/usb.c b/drivers/soc/fsl/qe/usb.c
index 32d8269fa692..59b326e924dc 100644
--- a/drivers/soc/fsl/qe/usb.c
+++ b/drivers/soc/fsl/qe/usb.c
@@ -43,7 +43,7 @@ int qe_usb_clock_set(enum qe_clock clk, int rate)

spin_lock_irqsave(&cmxgcr_lock, flags);

- clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);
+ qe_clrsetbits32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);

spin_unlock_irqrestore(&cmxgcr_lock, flags);

--
2.23.0

2019-10-25 20:11:22

by Rasmus Villemoes

Subject: [PATCH v2 16/23] powerpc/85xx: remove mostly pointless mpc85xx_qe_init()

Since commit 302c059f2e7b (QE: use subsys_initcall to init qe),
mpc85xx_qe_init() has done nothing apart from possibly emitting a
pr_err(). As part of reducing the amount of QE-related code in
arch/powerpc/ (and eventually support QE on other architectures),
remove this low-hanging fruit.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
arch/powerpc/platforms/85xx/common.c | 23 -------------------
arch/powerpc/platforms/85xx/corenet_generic.c | 2 --
arch/powerpc/platforms/85xx/mpc85xx.h | 2 --
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 -
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 1 -
arch/powerpc/platforms/85xx/twr_p102x.c | 1 -
6 files changed, 30 deletions(-)

diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
index fe0606439b5a..a554b6d87cf7 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -86,29 +86,6 @@ void __init mpc85xx_cpm2_pic_init(void)
#endif

#ifdef CONFIG_QUICC_ENGINE
-void __init mpc85xx_qe_init(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe");
- if (!np) {
- np = of_find_node_by_name(NULL, "qe");
- if (!np) {
- pr_err("%s: Could not find Quicc Engine node\n",
- __func__);
- return;
- }
- }
-
- if (!of_device_is_available(np)) {
- of_node_put(np);
- return;
- }
-
- of_node_put(np);
-
-}
-
void __init mpc85xx_qe_par_io_init(void)
{
struct device_node *np;
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c
index 8c1bb3941642..27ac38f7e1a9 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -56,8 +56,6 @@ void __init corenet_gen_setup_arch(void)
swiotlb_detect_4g();

pr_info("%s board\n", ppc_md.name);
-
- mpc85xx_qe_init();
}

static const struct of_device_id of_device_ids[] = {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h
index fa23f9b0592c..cb84c5c56c36 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -10,10 +10,8 @@ static inline void __init mpc85xx_cpm2_pic_init(void) {}
#endif /* CONFIG_CPM2 */

#ifdef CONFIG_QUICC_ENGINE
-extern void mpc85xx_qe_init(void);
extern void mpc85xx_qe_par_io_init(void);
#else
-static inline void __init mpc85xx_qe_init(void) {}
static inline void __init mpc85xx_qe_par_io_init(void) {}
#endif

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 4bc49e5ec0b6..fb05b4d5bf1e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -237,7 +237,6 @@ static void __init mpc85xx_mds_qe_init(void)
{
struct device_node *np;

- mpc85xx_qe_init();
mpc85xx_qe_par_io_init();
mpc85xx_mds_reset_ucc_phys();

diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 14b5a61d49c1..80a80174768c 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -72,7 +72,6 @@ static void __init mpc85xx_rdb_setup_arch(void)
fsl_pci_assign_primary();

#ifdef CONFIG_QUICC_ENGINE
- mpc85xx_qe_init();
mpc85xx_qe_par_io_init();
#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
if (machine_is(p1025_rdb)) {
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c
index b099f5607120..9abb1e9f73c4 100644
--- a/arch/powerpc/platforms/85xx/twr_p102x.c
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -57,7 +57,6 @@ static void __init twr_p1025_setup_arch(void)
fsl_pci_assign_primary();

#ifdef CONFIG_QUICC_ENGINE
- mpc85xx_qe_init();
mpc85xx_qe_par_io_init();

#if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE)
--
2.23.0

2019-10-25 20:11:31

by Rasmus Villemoes

Subject: [PATCH v2 23/23] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE

The core QE code now also builds for ARM, so replace the FSL_SOC &&
PPC32 dependencies by the more lax requirements OF && HAS_IOMEM.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
index cfa4b2939992..0c5b8b8e46b6 100644
--- a/drivers/soc/fsl/qe/Kconfig
+++ b/drivers/soc/fsl/qe/Kconfig
@@ -5,7 +5,7 @@

config QUICC_ENGINE
bool "QUICC Engine (QE) framework support"
- depends on FSL_SOC && PPC32
+ depends on OF && HAS_IOMEM
select GENERIC_ALLOCATOR
select CRC32
help
--
2.23.0

2019-10-25 20:11:42

by Rasmus Villemoes

Subject: [PATCH v2 22/23] soc/fsl/qe/qe.h: remove include of asm/cpm.h

asm/cpm.h only exists on PPC, so this prevents use of this header on
other platforms. Drivers that need asm/cpm.h (and are thus inherently
PPC-specific) must include that explicitly.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
include/soc/fsl/qe/qe.h | 1 -
1 file changed, 1 deletion(-)

diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index c1036d16ed03..3768c226490e 100644
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -17,7 +17,6 @@
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/err.h>
-#include <asm/cpm.h>
#include <soc/fsl/qe/immap_qe.h>
#include <linux/of.h>
#include <linux/of_address.h>
--
2.23.0

2019-10-25 20:12:41

by Rasmus Villemoes

Subject: [PATCH v2 18/23] soc: fsl: qe: remove unused qe_ic_set_* functions

There are no current callers of these functions, and they use the
ppc-specific virq_to_hw(). So removing them gets us one step closer to
building QE support for ARM.

If the functionality is ever actually needed, the code can be dug out
of git and then adapted to work on all architectures, but for future
reference please note that I believe qe_ic_set_priority is buggy: The
"priority < 4" should be "priority <= 4", and in the else branch 24
should be replaced by 28, at least if I'm reading the data sheet right.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe_ic.c | 94 --------------------------------------
include/soc/fsl/qe/qe_ic.h | 4 --
2 files changed, 98 deletions(-)

diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index e20f1205c0df..58f4b4914f53 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -533,97 +533,3 @@ static int __init qe_ic_of_init(void)
return 0;
}
subsys_initcall(qe_ic_of_init);
-
-void qe_ic_set_highest_priority(unsigned int virq, int high)
-{
- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
- unsigned int src = virq_to_hw(virq);
- u32 temp = 0;
-
- temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
-
- temp &= ~CICR_HP_MASK;
- temp |= src << CICR_HP_SHIFT;
-
- temp &= ~CICR_HPIT_MASK;
- temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
-
- qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
-}
-
-/* Set Priority level within its group, from 1 to 8 */
-int qe_ic_set_priority(unsigned int virq, unsigned int priority)
-{
- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
- unsigned int src = virq_to_hw(virq);
- u32 temp;
-
- if (priority > 8 || priority == 0)
- return -EINVAL;
- if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
- "%s: Invalid hw irq number for QEIC\n", __func__))
- return -EINVAL;
- if (qe_ic_info[src].pri_reg == 0)
- return -EINVAL;
-
- temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
-
- if (priority < 4) {
- temp &= ~(0x7 << (32 - priority * 3));
- temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
- } else {
- temp &= ~(0x7 << (24 - priority * 3));
- temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
- }
-
- qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
-
- return 0;
-}
-
-/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
-int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
-{
- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
- unsigned int src = virq_to_hw(virq);
- u32 temp, control_reg = QEIC_CICNR, shift = 0;
-
- if (priority > 2 || priority == 0)
- return -EINVAL;
- if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
- "%s: Invalid hw irq number for QEIC\n", __func__))
- return -EINVAL;
-
- switch (qe_ic_info[src].pri_reg) {
- case QEIC_CIPZCC:
- shift = CICNR_ZCC1T_SHIFT;
- break;
- case QEIC_CIPWCC:
- shift = CICNR_WCC1T_SHIFT;
- break;
- case QEIC_CIPYCC:
- shift = CICNR_YCC1T_SHIFT;
- break;
- case QEIC_CIPXCC:
- shift = CICNR_XCC1T_SHIFT;
- break;
- case QEIC_CIPRTA:
- shift = CRICR_RTA1T_SHIFT;
- control_reg = QEIC_CRICR;
- break;
- case QEIC_CIPRTB:
- shift = CRICR_RTB1T_SHIFT;
- control_reg = QEIC_CRICR;
- break;
- default:
- return -EINVAL;
- }
-
- shift += (2 - priority) * 2;
- temp = qe_ic_read(qe_ic->regs, control_reg);
- temp &= ~(SIGNAL_MASK << shift);
- temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
- qe_ic_write(qe_ic->regs, control_reg, temp);
-
- return 0;
-}
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index 43e4ce95c6a0..d47eb231519e 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -63,8 +63,4 @@ static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
{ return 0; }
#endif /* CONFIG_QUICC_ENGINE */

-void qe_ic_set_highest_priority(unsigned int virq, int high);
-int qe_ic_set_priority(unsigned int virq, unsigned int priority);
-int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
-
#endif /* _ASM_POWERPC_QE_IC_H */
--
2.23.0

2019-10-25 20:12:43

by Rasmus Villemoes

Subject: [PATCH v2 19/23] net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32

Currently, QUICC_ENGINE depends on PPC32, so this in itself does not
change anything. In order to allow removing the PPC32 dependency from
QUICC_ENGINE and avoid allmodconfig build failures, add this explicit
dependency.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/net/ethernet/freescale/Kconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/drivers/net/ethernet/freescale/Kconfig b/drivers/net/ethernet/freescale/Kconfig
index 6a7e8993119f..97d27c7740d4 100644
--- a/drivers/net/ethernet/freescale/Kconfig
+++ b/drivers/net/ethernet/freescale/Kconfig
@@ -75,6 +75,7 @@ config FSL_XGMAC_MDIO
config UCC_GETH
tristate "Freescale QE Gigabit Ethernet"
depends on QUICC_ENGINE
+ depends on PPC32
select FSL_PQ_MDIO
select PHYLIB
---help---
--
2.23.0

2019-10-25 20:12:47

by Rasmus Villemoes

Subject: [PATCH v2 12/23] soc: fsl: qe: drop assign-only high_active in qe_ic_init

high_active is only assigned to but never used. Remove it.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe_ic.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index f3659c312e13..61a40e40f3ae 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -450,7 +450,7 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
{
struct qe_ic *qe_ic;
struct resource res;
- u32 temp = 0, ret, high_active = 0;
+ u32 temp = 0, ret;

ret = of_address_to_resource(node, 0, &res);
if (ret)
@@ -496,10 +496,8 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
temp |= CICR_GRTB;

/* choose destination signal for highest priority interrupt */
- if (flags & QE_IC_HIGH_SIGNAL) {
+ if (flags & QE_IC_HIGH_SIGNAL)
temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
- high_active = 1;
- }

qe_ic_write(qe_ic->regs, QEIC_CICR, temp);

--
2.23.0

2019-10-28 21:07:01

by kernel test robot

Subject: Re: [PATCH v2 23/23] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE

Hi Rasmus,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on linus/master]
[also build test ERROR on v5.4-rc5 next-20191028]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url: https://github.com/0day-ci/linux/commits/Rasmus-Villemoes/QUICC-Engine-support-on-ARM/20191028-202537
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git d6d5df1db6e9d7f8f76d2911707f7d5877251b02
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=arm64

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <[email protected]>

All errors (new ones prefixed by >>):

drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_get_low_irq':
>> drivers/soc/fsl/qe/qe_ic.c:384:10: error: 'NO_IRQ' undeclared (first use in this function); did you mean 'NR_IRQS'?
return NO_IRQ;
^~~~~~
NR_IRQS
drivers/soc/fsl/qe/qe_ic.c:384:10: note: each undeclared identifier is reported only once for each function it appears in
drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_get_high_irq':
drivers/soc/fsl/qe/qe_ic.c:400:10: error: 'NO_IRQ' undeclared (first use in this function); did you mean 'NR_IRQS'?
return NO_IRQ;
^~~~~~
NR_IRQS
drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_cascade_low':
drivers/soc/fsl/qe/qe_ic.c:411:21: error: 'NO_IRQ' undeclared (first use in this function); did you mean 'NR_IRQS'?
if (cascade_irq != NO_IRQ)
^~~~~~
NR_IRQS
drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_cascade_high':
drivers/soc/fsl/qe/qe_ic.c:424:21: error: 'NO_IRQ' undeclared (first use in this function); did you mean 'NR_IRQS'?
if (cascade_irq != NO_IRQ)
^~~~~~
NR_IRQS
drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_cascade_muxed_mpic':
drivers/soc/fsl/qe/qe_ic.c:438:21: error: 'NO_IRQ' undeclared (first use in this function); did you mean 'NR_IRQS'?
if (cascade_irq == NO_IRQ)
^~~~~~
NR_IRQS
drivers/soc/fsl/qe/qe_ic.c: In function 'qe_ic_init':
drivers/soc/fsl/qe/qe_ic.c:477:25: error: 'NO_IRQ' undeclared (first use in this function); did you mean 'NR_IRQS'?
if (qe_ic->virq_low == NO_IRQ) {
^~~~~~
NR_IRQS

vim +384 drivers/soc/fsl/qe/qe_ic.c

9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 372
9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 373 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
35a84c2f56e0f7 arch/powerpc/sysdev/qe_lib/qe_ic.c Olaf Hering 2006-10-07 374 unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 375 {
9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 376 int irq;
9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 377
9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 378 BUG_ON(qe_ic == NULL);
9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 379
9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 380 /* get the interrupt source vector. */
9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 381 irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 382
9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 383 if (irq == 0)
9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 @384 return NO_IRQ;
9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 385
9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 386 return irq_linear_revmap(qe_ic->irqhost, irq);
9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 387 }
9865853851313e arch/powerpc/sysdev/qe_lib/qe_ic.c Li Yang 2006-10-03 388

:::::: The code at line 384 was first introduced by commit
:::::: 9865853851313e0d94a4acde42d6f9d8070bb376 [POWERPC] Add QUICC Engine (QE) infrastructure

:::::: TO: Li Yang <[email protected]>
:::::: CC: Paul Mackerras <[email protected]>

---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation

Attachments:

2019-10-29 02:41:53

by kernel test robot

Subject: Re: [PATCH v2 23/23] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE

Hi Rasmus,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v5.4-rc5 next-20191028]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url: https://github.com/0day-ci/linux/commits/Rasmus-Villemoes/QUICC-Engine-support-on-ARM/20191028-202537
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git d6d5df1db6e9d7f8f76d2911707f7d5877251b02
config: sparc64-allmodconfig (attached as .config)
compiler: sparc64-linux-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=sparc64

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <[email protected]>

All warnings (new ones prefixed by >>):

In file included from include/linux/kernel.h:11:0,
from include/linux/delay.h:22,
from drivers/net//wan/fsl_ucc_hdlc.c:7:
drivers/net//wan/fsl_ucc_hdlc.c: In function 'uhdlc_init':
>> include/linux/err.h:22:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-MAX_ERRNO)
^
include/linux/compiler.h:78:42: note: in definition of macro 'unlikely'
# define unlikely(x) __builtin_expect(!!(x), 0)
^
>> drivers/net//wan/fsl_ucc_hdlc.c:198:6: note: in expansion of macro 'IS_ERR_VALUE'
if (IS_ERR_VALUE(priv->ucc_pram_offset)) {
^~~~~~~~~~~~
>> include/linux/err.h:22:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-MAX_ERRNO)
^
include/linux/compiler.h:78:42: note: in definition of macro 'unlikely'
# define unlikely(x) __builtin_expect(!!(x), 0)
^
drivers/net//wan/fsl_ucc_hdlc.c:236:6: note: in expansion of macro 'IS_ERR_VALUE'
if (IS_ERR_VALUE(riptr)) {
^~~~~~~~~~~~
>> include/linux/err.h:22:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-MAX_ERRNO)
^
include/linux/compiler.h:78:42: note: in definition of macro 'unlikely'
# define unlikely(x) __builtin_expect(!!(x), 0)
^
drivers/net//wan/fsl_ucc_hdlc.c:243:6: note: in expansion of macro 'IS_ERR_VALUE'
if (IS_ERR_VALUE(tiptr)) {
^~~~~~~~~~~~
--
In file included from include/linux/kernel.h:11:0,
from drivers/soc//fsl/qe/ucc_fast.c:11:
drivers/soc//fsl/qe/ucc_fast.c: In function 'ucc_fast_init':
>> include/linux/err.h:22:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-MAX_ERRNO)
^
include/linux/compiler.h:78:42: note: in definition of macro 'unlikely'
# define unlikely(x) __builtin_expect(!!(x), 0)
^
>> drivers/soc//fsl/qe/ucc_fast.c:267:6: note: in expansion of macro 'IS_ERR_VALUE'
if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
^~~~~~~~~~~~
>> include/linux/err.h:22:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-MAX_ERRNO)
^
include/linux/compiler.h:78:42: note: in definition of macro 'unlikely'
# define unlikely(x) __builtin_expect(!!(x), 0)
^
drivers/soc//fsl/qe/ucc_fast.c:280:6: note: in expansion of macro 'IS_ERR_VALUE'
if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
^~~~~~~~~~~~
--
In file included from include/linux/kernel.h:11:0,
from include/linux/delay.h:22,
from drivers/net/wan/fsl_ucc_hdlc.c:7:
drivers/net/wan/fsl_ucc_hdlc.c: In function 'uhdlc_init':
>> include/linux/err.h:22:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-MAX_ERRNO)
^
include/linux/compiler.h:78:42: note: in definition of macro 'unlikely'
# define unlikely(x) __builtin_expect(!!(x), 0)
^
drivers/net/wan/fsl_ucc_hdlc.c:198:6: note: in expansion of macro 'IS_ERR_VALUE'
if (IS_ERR_VALUE(priv->ucc_pram_offset)) {
^~~~~~~~~~~~
>> include/linux/err.h:22:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-MAX_ERRNO)
^
include/linux/compiler.h:78:42: note: in definition of macro 'unlikely'
# define unlikely(x) __builtin_expect(!!(x), 0)
^
drivers/net/wan/fsl_ucc_hdlc.c:236:6: note: in expansion of macro 'IS_ERR_VALUE'
if (IS_ERR_VALUE(riptr)) {
^~~~~~~~~~~~
>> include/linux/err.h:22:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-MAX_ERRNO)
^
include/linux/compiler.h:78:42: note: in definition of macro 'unlikely'
# define unlikely(x) __builtin_expect(!!(x), 0)
^
drivers/net/wan/fsl_ucc_hdlc.c:243:6: note: in expansion of macro 'IS_ERR_VALUE'
if (IS_ERR_VALUE(tiptr)) {
^~~~~~~~~~~~
--
In file included from include/linux/kernel.h:11:0,
from drivers/soc/fsl/qe/ucc_fast.c:11:
drivers/soc/fsl/qe/ucc_fast.c: In function 'ucc_fast_init':
>> include/linux/err.h:22:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-MAX_ERRNO)
^
include/linux/compiler.h:78:42: note: in definition of macro 'unlikely'
# define unlikely(x) __builtin_expect(!!(x), 0)
^
drivers/soc/fsl/qe/ucc_fast.c:267:6: note: in expansion of macro 'IS_ERR_VALUE'
if (IS_ERR_VALUE(uccf->ucc_fast_tx_virtual_fifo_base_offset)) {
^~~~~~~~~~~~
>> include/linux/err.h:22:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-MAX_ERRNO)
^
include/linux/compiler.h:78:42: note: in definition of macro 'unlikely'
# define unlikely(x) __builtin_expect(!!(x), 0)
^
drivers/soc/fsl/qe/ucc_fast.c:280:6: note: in expansion of macro 'IS_ERR_VALUE'
if (IS_ERR_VALUE(uccf->ucc_fast_rx_virtual_fifo_base_offset)) {
^~~~~~~~~~~~

vim +22 include/linux/err.h

ebba5f9fcb8823 Randy Dunlap 2006-09-27 21
aa00edc1287a69 Linus Torvalds 2016-05-27 @22 #define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-MAX_ERRNO)
07ab67c8d0d7c1 Linus Torvalds 2005-05-19 23

:::::: The code at line 22 was first introduced by commit
:::::: aa00edc1287a693eadc7bc67a3d73555d969b35d make IS_ERR_VALUE() complain about non-pointer-sized arguments

:::::: TO: Linus Torvalds <[email protected]>
:::::: CC: Linus Torvalds <[email protected]>

---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation

Attachments:

2019-10-29 07:06:39

by kernel test robot

Subject: Re: [PATCH v2 23/23] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE

Hi Rasmus,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on linus/master]
[also build test WARNING on v5.4-rc5 next-20191028]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url: https://github.com/0day-ci/linux/commits/Rasmus-Villemoes/QUICC-Engine-support-on-ARM/20191028-202537
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git d6d5df1db6e9d7f8f76d2911707f7d5877251b02
reproduce:
# apt-get install sparse
# sparse version: v0.6.1-dirty
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <[email protected]>


sparse warnings: (new ones prefixed by >>)

>> drivers/net/wan/fsl_ucc_hdlc.c:300:57: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
>> drivers/net/wan/fsl_ucc_hdlc.c:300:57: sparse: expected void [noderef] <asn:2> *
>> drivers/net/wan/fsl_ucc_hdlc.c:300:57: sparse: got restricted __be16 *
drivers/net/wan/fsl_ucc_hdlc.c:302:46: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:302:46: sparse: expected void [noderef] <asn:2> *
>> drivers/net/wan/fsl_ucc_hdlc.c:302:46: sparse: got restricted __be32 *
drivers/net/wan/fsl_ucc_hdlc.c:311:57: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:311:57: sparse: expected void [noderef] <asn:2> *
drivers/net/wan/fsl_ucc_hdlc.c:311:57: sparse: got restricted __be16 *
drivers/net/wan/fsl_ucc_hdlc.c:313:46: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:313:46: sparse: expected void [noderef] <asn:2> *
drivers/net/wan/fsl_ucc_hdlc.c:313:46: sparse: got restricted __be32 *
>> drivers/net/wan/fsl_ucc_hdlc.c:363:29: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned short [usertype] @@ got resunsigned short [usertype] @@
>> drivers/net/wan/fsl_ucc_hdlc.c:363:29: sparse: expected unsigned short [usertype]
>> drivers/net/wan/fsl_ucc_hdlc.c:363:29: sparse: got restricted __be16 [usertype]
>> drivers/net/wan/fsl_ucc_hdlc.c:370:36: sparse: sparse: restricted __be16 degrades to integer
>> drivers/net/wan/fsl_ucc_hdlc.c:393:12: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct qe_bd [noderef] <asn:2> *bd @@ got ref] <asn:2> *bd @@
>> drivers/net/wan/fsl_ucc_hdlc.c:393:12: sparse: expected struct qe_bd [noderef] <asn:2> *bd
>> drivers/net/wan/fsl_ucc_hdlc.c:393:12: sparse: got struct qe_bd *curtx_bd
>> drivers/net/wan/fsl_ucc_hdlc.c:403:9: sparse: sparse: dereference of noderef expression
>> drivers/net/wan/fsl_ucc_hdlc.c:416:20: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct qe_bd [noderef] <asn:2> *[assigned] bd @@ got > *[assigned] bd @@
>> drivers/net/wan/fsl_ucc_hdlc.c:416:20: sparse: expected struct qe_bd [noderef] <asn:2> *[assigned] bd
>> drivers/net/wan/fsl_ucc_hdlc.c:416:20: sparse: got struct qe_bd *tx_bd_base
>> drivers/net/wan/fsl_ucc_hdlc.c:418:16: sparse: sparse: incompatible types in comparison expression (different address spaces):
>> drivers/net/wan/fsl_ucc_hdlc.c:418:16: sparse: struct qe_bd [noderef] <asn:2> *
>> drivers/net/wan/fsl_ucc_hdlc.c:418:16: sparse: struct qe_bd *
drivers/net/wan/fsl_ucc_hdlc.c:453:33: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:497:41: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:519:33: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:543:38: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:587:67: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:602:41: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
>> drivers/net/wan/fsl_ucc_hdlc.c:735:37: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned long offset @@ got restricted __be16 [noderef] [userunsigned long offset @@
drivers/net/wan/fsl_ucc_hdlc.c:736:37: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned long offset @@ got restricted __be16 [noderef] [userunsigned long offset @@
>> drivers/net/wan/fsl_ucc_hdlc.c:847:38: sparse: sparse: incorrect type in initializer (different address spaces) @@ expected struct qe_mux *qe_mux_reg @@ got struct qe_mux [nodstruct qe_mux *qe_mux_reg @@
drivers/net/wan/fsl_ucc_hdlc.c:850:40: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:851:40: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:854:39: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
>> drivers/net/wan/fsl_ucc_hdlc.c:857:37: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void const volatile [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:862:38: sparse: sparse: incorrect type in initializer (different address spaces) @@ expected struct qe_mux *qe_mux_reg @@ got struct qe_mux [nodstruct qe_mux *qe_mux_reg @@
>> drivers/net/wan/fsl_ucc_hdlc.c:864:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void volatile [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:866:40: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:867:40: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:869:39: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:991:57: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:993:46: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:1002:57: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/net/wan/fsl_ucc_hdlc.c:1004:46: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
>> drivers/net/wan/fsl_ucc_hdlc.c:403:9: sparse: sparse: dereference of noderef expression
drivers/net/wan/fsl_ucc_hdlc.c:720:29: sparse: sparse: dereference of noderef expression
drivers/net/wan/fsl_ucc_hdlc.c:735:27: sparse: sparse: dereference of noderef expression
drivers/net/wan/fsl_ucc_hdlc.c:736:27: sparse: sparse: dereference of noderef expression
drivers/net/wan/fsl_ucc_hdlc.c:811:21: sparse: sparse: dereference of noderef expression
drivers/net/wan/fsl_ucc_hdlc.c:1019:29: sparse: sparse: dereference of noderef expression
--
>> drivers/soc/fsl/qe/qe.c:430:21: sparse: sparse: cast to restricted __be32
>> drivers/soc/fsl/qe/qe.c:430:21: sparse: sparse: cast to restricted __be32
>> drivers/soc/fsl/qe/qe.c:430:21: sparse: sparse: cast to restricted __be32
>> drivers/soc/fsl/qe/qe.c:430:21: sparse: sparse: cast to restricted __be32
>> drivers/soc/fsl/qe/qe.c:430:21: sparse: sparse: cast to restricted __be32
>> drivers/soc/fsl/qe/qe.c:430:21: sparse: sparse: cast to restricted __be32
>> drivers/soc/fsl/qe/qe.c:532:41: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned long long static [addressable] [toplevel] [usertype] extended_modes @@ got addressable] [toplevel] [usertype] extended_modes @@
>> drivers/soc/fsl/qe/qe.c:532:41: sparse: expected unsigned long long static [addressable] [toplevel] [usertype] extended_modes
>> drivers/soc/fsl/qe/qe.c:532:41: sparse: got restricted __be64 const [usertype] extended_modes
--
>> drivers/soc/fsl/qe/qe_common.c:75:48: sparse: sparse: incorrect type in argument 2 (different base types) @@ expected restricted __be32 const [usertype] *addr @@ got t [usertype] *addr @@
>> drivers/soc/fsl/qe/qe_common.c:75:48: sparse: expected restricted __be32 const [usertype] *addr
>> drivers/soc/fsl/qe/qe_common.c:75:48: sparse: got unsigned int *
--
>> drivers/soc/fsl/qe/qe_ic.c:293:32: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected restricted __be32 [noderef] [usertype] <asn:2> *base @@ got icted __be32 [noderef] [usertype] <asn:2> *base @@
>> drivers/soc/fsl/qe/qe_ic.c:293:32: sparse: expected restricted __be32 [noderef] [usertype] <asn:2> *base
>> drivers/soc/fsl/qe/qe_ic.c:293:32: sparse: got unsigned int [noderef] [usertype] <asn:2> *regs
drivers/soc/fsl/qe/qe_ic.c:294:26: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected restricted __be32 [noderef] [usertype] <asn:2> *base @@ got icted __be32 [noderef] [usertype] <asn:2> *base @@
drivers/soc/fsl/qe/qe_ic.c:294:26: sparse: expected restricted __be32 [noderef] [usertype] <asn:2> *base
drivers/soc/fsl/qe/qe_ic.c:294:26: sparse: got unsigned int [noderef] [usertype] <asn:2> *regs
drivers/soc/fsl/qe/qe_ic.c:309:32: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected restricted __be32 [noderef] [usertype] <asn:2> *base @@ got icted __be32 [noderef] [usertype] <asn:2> *base @@
drivers/soc/fsl/qe/qe_ic.c:309:32: sparse: expected restricted __be32 [noderef] [usertype] <asn:2> *base
drivers/soc/fsl/qe/qe_ic.c:309:32: sparse: got unsigned int [noderef] [usertype] <asn:2> *regs
drivers/soc/fsl/qe/qe_ic.c:310:26: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected restricted __be32 [noderef] [usertype] <asn:2> *base @@ got icted __be32 [noderef] [usertype] <asn:2> *base @@
drivers/soc/fsl/qe/qe_ic.c:310:26: sparse: expected restricted __be32 [noderef] [usertype] <asn:2> *base
drivers/soc/fsl/qe/qe_ic.c:310:26: sparse: got unsigned int [noderef] [usertype] <asn:2> *regs
drivers/soc/fsl/qe/qe_ic.c:381:31: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected restricted __be32 [noderef] [usertype] <asn:2> *base @@ got icted __be32 [noderef] [usertype] <asn:2> *base @@
drivers/soc/fsl/qe/qe_ic.c:381:31: sparse: expected restricted __be32 [noderef] [usertype] <asn:2> *base
drivers/soc/fsl/qe/qe_ic.c:381:31: sparse: got unsigned int [noderef] [usertype] <asn:2> *regs
drivers/soc/fsl/qe/qe_ic.c:384:24: sparse: sparse: undefined identifier 'NO_IRQ'
drivers/soc/fsl/qe/qe_ic.c:397:31: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected restricted __be32 [noderef] [usertype] <asn:2> *base @@ got icted __be32 [noderef] [usertype] <asn:2> *base @@
drivers/soc/fsl/qe/qe_ic.c:400:24: sparse: sparse: undefined identifier 'NO_IRQ'
drivers/soc/fsl/qe/qe_ic.c:411:28: sparse: sparse: undefined identifier 'NO_IRQ'
drivers/soc/fsl/qe/qe_ic.c:424:28: sparse: sparse: undefined identifier 'NO_IRQ'
drivers/soc/fsl/qe/qe_ic.c:438:28: sparse: sparse: undefined identifier 'NO_IRQ'
drivers/soc/fsl/qe/qe_ic.c:441:28: sparse: sparse: undefined identifier 'NO_IRQ'
drivers/soc/fsl/qe/qe_ic.c:477:32: sparse: sparse: undefined identifier 'NO_IRQ'
drivers/soc/fsl/qe/qe_ic.c:514:33: sparse: sparse: undefined identifier 'NO_IRQ'
--
>> drivers/soc/fsl/qe/ucc.c:638:20: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct qe_mux *qe_mux_reg @@ got struct qe_mux [nodstruct qe_mux *qe_mux_reg @@
>> drivers/soc/fsl/qe/ucc.c:638:20: sparse: expected struct qe_mux *qe_mux_reg
>> drivers/soc/fsl/qe/ucc.c:638:20: sparse: got struct qe_mux [noderef] <asn:2> *
>> drivers/soc/fsl/qe/ucc.c:653:9: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
>> drivers/soc/fsl/qe/ucc.c:653:9: sparse: expected void [noderef] <asn:2> *
>> drivers/soc/fsl/qe/ucc.c:653:9: sparse: got restricted __be32 *
drivers/soc/fsl/qe/ucc.c:653:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
>> drivers/soc/fsl/qe/ucc.c:653:9: sparse: expected void [noderef] <asn:2> *
>> drivers/soc/fsl/qe/ucc.c:653:9: sparse: got restricted __be32 *
--
>> drivers/soc/fsl/qe/ucc_fast.c:215:22: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned int [noderef] [usertype] <asn:2> *p_ucce @@ got ed int [noderef] [usertype] <asn:2> *p_ucce @@
>> drivers/soc/fsl/qe/ucc_fast.c:215:22: sparse: expected unsigned int [noderef] [usertype] <asn:2> *p_ucce
>> drivers/soc/fsl/qe/ucc_fast.c:215:22: sparse: got restricted __be32 [noderef] <asn:2> *
>> drivers/soc/fsl/qe/ucc_fast.c:216:22: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned int [noderef] [usertype] <asn:2> *p_uccm @@ got ed int [noderef] [usertype] <asn:2> *p_uccm @@
>> drivers/soc/fsl/qe/ucc_fast.c:216:22: sparse: expected unsigned int [noderef] [usertype] <asn:2> *p_uccm
drivers/soc/fsl/qe/ucc_fast.c:216:22: sparse: got restricted __be32 [noderef] <asn:2> *

vim +300 drivers/net/wan/fsl_ucc_hdlc.c

c19b6d246a3562 Zhao Qiang 2016-06-06 77
c19b6d246a3562 Zhao Qiang 2016-06-06 78 static int uhdlc_init(struct ucc_hdlc_private *priv)
c19b6d246a3562 Zhao Qiang 2016-06-06 79 {
c19b6d246a3562 Zhao Qiang 2016-06-06 80 struct ucc_tdm_info *ut_info;
c19b6d246a3562 Zhao Qiang 2016-06-06 81 struct ucc_fast_info *uf_info;
c19b6d246a3562 Zhao Qiang 2016-06-06 82 u32 cecr_subblock;
c19b6d246a3562 Zhao Qiang 2016-06-06 83 u16 bd_status;
c19b6d246a3562 Zhao Qiang 2016-06-06 84 int ret, i;
c19b6d246a3562 Zhao Qiang 2016-06-06 85 void *bd_buffer;
c19b6d246a3562 Zhao Qiang 2016-06-06 86 dma_addr_t bd_dma_addr;
c19b6d246a3562 Zhao Qiang 2016-06-06 87 u32 riptr;
c19b6d246a3562 Zhao Qiang 2016-06-06 88 u32 tiptr;
c19b6d246a3562 Zhao Qiang 2016-06-06 89 u32 gumr;
c19b6d246a3562 Zhao Qiang 2016-06-06 90
c19b6d246a3562 Zhao Qiang 2016-06-06 91 ut_info = priv->ut_info;
c19b6d246a3562 Zhao Qiang 2016-06-06 92 uf_info = &ut_info->uf_info;
c19b6d246a3562 Zhao Qiang 2016-06-06 93
c19b6d246a3562 Zhao Qiang 2016-06-06 94 if (priv->tsa) {
c19b6d246a3562 Zhao Qiang 2016-06-06 95 uf_info->tsa = 1;
c19b6d246a3562 Zhao Qiang 2016-06-06 96 uf_info->ctsp = 1;
040b7c94e4ec58 David Gounaris 2018-09-03 97 uf_info->cds = 1;
040b7c94e4ec58 David Gounaris 2018-09-03 98 uf_info->ctss = 1;
040b7c94e4ec58 David Gounaris 2018-09-03 99 } else {
040b7c94e4ec58 David Gounaris 2018-09-03 100 uf_info->cds = 0;
040b7c94e4ec58 David Gounaris 2018-09-03 101 uf_info->ctsp = 0;
040b7c94e4ec58 David Gounaris 2018-09-03 102 uf_info->ctss = 0;
c19b6d246a3562 Zhao Qiang 2016-06-06 103 }
067bb938dad61e Holger Brunck 2017-05-17 104
067bb938dad61e Holger Brunck 2017-05-17 105 /* This sets HPM register in CMXUCR register which configures a
067bb938dad61e Holger Brunck 2017-05-17 106 * open drain connected HDLC bus
067bb938dad61e Holger Brunck 2017-05-17 107 */
067bb938dad61e Holger Brunck 2017-05-17 108 if (priv->hdlc_bus)
067bb938dad61e Holger Brunck 2017-05-17 109 uf_info->brkpt_support = 1;
067bb938dad61e Holger Brunck 2017-05-17 110
c19b6d246a3562 Zhao Qiang 2016-06-06 111 uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
c19b6d246a3562 Zhao Qiang 2016-06-06 112 UCC_HDLC_UCCE_TXB) << 16);
c19b6d246a3562 Zhao Qiang 2016-06-06 113
c19b6d246a3562 Zhao Qiang 2016-06-06 114 ret = ucc_fast_init(uf_info, &priv->uccf);
c19b6d246a3562 Zhao Qiang 2016-06-06 115 if (ret) {
c19b6d246a3562 Zhao Qiang 2016-06-06 116 dev_err(priv->dev, "Failed to init uccf.");
c19b6d246a3562 Zhao Qiang 2016-06-06 117 return ret;
c19b6d246a3562 Zhao Qiang 2016-06-06 118 }
c19b6d246a3562 Zhao Qiang 2016-06-06 119
c19b6d246a3562 Zhao Qiang 2016-06-06 120 priv->uf_regs = priv->uccf->uf_regs;
c19b6d246a3562 Zhao Qiang 2016-06-06 121 ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
c19b6d246a3562 Zhao Qiang 2016-06-06 122
c19b6d246a3562 Zhao Qiang 2016-06-06 123 /* Loopback mode */
c19b6d246a3562 Zhao Qiang 2016-06-06 124 if (priv->loopback) {
c19b6d246a3562 Zhao Qiang 2016-06-06 125 dev_info(priv->dev, "Loopback Mode\n");
54e9e0874938ba Holger Brunck 2017-05-17 126 /* use the same clock when work in loopback */
54e9e0874938ba Holger Brunck 2017-05-17 127 qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1);
54e9e0874938ba Holger Brunck 2017-05-17 128
c19b6d246a3562 Zhao Qiang 2016-06-06 129 gumr = ioread32be(&priv->uf_regs->gumr);
c19b6d246a3562 Zhao Qiang 2016-06-06 130 gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS |
c19b6d246a3562 Zhao Qiang 2016-06-06 131 UCC_FAST_GUMR_TCI);
c19b6d246a3562 Zhao Qiang 2016-06-06 132 gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN);
c19b6d246a3562 Zhao Qiang 2016-06-06 133 iowrite32be(gumr, &priv->uf_regs->gumr);
c19b6d246a3562 Zhao Qiang 2016-06-06 134 }
c19b6d246a3562 Zhao Qiang 2016-06-06 135
c19b6d246a3562 Zhao Qiang 2016-06-06 136 /* Initialize SI */
c19b6d246a3562 Zhao Qiang 2016-06-06 137 if (priv->tsa)
c19b6d246a3562 Zhao Qiang 2016-06-06 138 ucc_tdm_init(priv->utdm, priv->ut_info);
c19b6d246a3562 Zhao Qiang 2016-06-06 139
c19b6d246a3562 Zhao Qiang 2016-06-06 140 /* Write to QE CECR, UCCx channel to Stop Transmission */
c19b6d246a3562 Zhao Qiang 2016-06-06 141 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
c19b6d246a3562 Zhao Qiang 2016-06-06 142 ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock,
c19b6d246a3562 Zhao Qiang 2016-06-06 143 QE_CR_PROTOCOL_UNSPECIFIED, 0);
c19b6d246a3562 Zhao Qiang 2016-06-06 144
c19b6d246a3562 Zhao Qiang 2016-06-06 145 /* Set UPSMR normal mode (need fixed)*/
c19b6d246a3562 Zhao Qiang 2016-06-06 146 iowrite32be(0, &priv->uf_regs->upsmr);
c19b6d246a3562 Zhao Qiang 2016-06-06 147
067bb938dad61e Holger Brunck 2017-05-17 148 /* hdlc_bus mode */
067bb938dad61e Holger Brunck 2017-05-17 149 if (priv->hdlc_bus) {
067bb938dad61e Holger Brunck 2017-05-17 150 u32 upsmr;
067bb938dad61e Holger Brunck 2017-05-17 151
067bb938dad61e Holger Brunck 2017-05-17 152 dev_info(priv->dev, "HDLC bus Mode\n");
067bb938dad61e Holger Brunck 2017-05-17 153 upsmr = ioread32be(&priv->uf_regs->upsmr);
067bb938dad61e Holger Brunck 2017-05-17 154
067bb938dad61e Holger Brunck 2017-05-17 155 /* bus mode and retransmit enable, with collision window
067bb938dad61e Holger Brunck 2017-05-17 156 * set to 8 bytes
067bb938dad61e Holger Brunck 2017-05-17 157 */
067bb938dad61e Holger Brunck 2017-05-17 158 upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS |
067bb938dad61e Holger Brunck 2017-05-17 159 UCC_HDLC_UPSMR_CW8;
067bb938dad61e Holger Brunck 2017-05-17 160 iowrite32be(upsmr, &priv->uf_regs->upsmr);
067bb938dad61e Holger Brunck 2017-05-17 161
067bb938dad61e Holger Brunck 2017-05-17 162 /* explicitly disable CDS & CTSP */
067bb938dad61e Holger Brunck 2017-05-17 163 gumr = ioread32be(&priv->uf_regs->gumr);
067bb938dad61e Holger Brunck 2017-05-17 164 gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP);
067bb938dad61e Holger Brunck 2017-05-17 165 /* set automatic sync to explicitly ignore CD signal */
067bb938dad61e Holger Brunck 2017-05-17 166 gumr |= UCC_FAST_GUMR_SYNL_AUTO;
067bb938dad61e Holger Brunck 2017-05-17 167 iowrite32be(gumr, &priv->uf_regs->gumr);
067bb938dad61e Holger Brunck 2017-05-17 168 }
067bb938dad61e Holger Brunck 2017-05-17 169
c19b6d246a3562 Zhao Qiang 2016-06-06 170 priv->rx_ring_size = RX_BD_RING_LEN;
c19b6d246a3562 Zhao Qiang 2016-06-06 171 priv->tx_ring_size = TX_BD_RING_LEN;
c19b6d246a3562 Zhao Qiang 2016-06-06 172 /* Alloc Rx BD */
c19b6d246a3562 Zhao Qiang 2016-06-06 173 priv->rx_bd_base = dma_alloc_coherent(priv->dev,
5b8aad93c52bdd Holger Brunck 2017-05-17 174 RX_BD_RING_LEN * sizeof(struct qe_bd),
c19b6d246a3562 Zhao Qiang 2016-06-06 175 &priv->dma_rx_bd, GFP_KERNEL);
c19b6d246a3562 Zhao Qiang 2016-06-06 176
c19b6d246a3562 Zhao Qiang 2016-06-06 177 if (!priv->rx_bd_base) {
c19b6d246a3562 Zhao Qiang 2016-06-06 178 dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n");
c19b6d246a3562 Zhao Qiang 2016-06-06 179 ret = -ENOMEM;
1efb597d8bf56c Zhao Qiang 2016-07-15 180 goto free_uccf;
c19b6d246a3562 Zhao Qiang 2016-06-06 181 }
c19b6d246a3562 Zhao Qiang 2016-06-06 182
c19b6d246a3562 Zhao Qiang 2016-06-06 183 /* Alloc Tx BD */
c19b6d246a3562 Zhao Qiang 2016-06-06 184 priv->tx_bd_base = dma_alloc_coherent(priv->dev,
5b8aad93c52bdd Holger Brunck 2017-05-17 185 TX_BD_RING_LEN * sizeof(struct qe_bd),
c19b6d246a3562 Zhao Qiang 2016-06-06 186 &priv->dma_tx_bd, GFP_KERNEL);
c19b6d246a3562 Zhao Qiang 2016-06-06 187
c19b6d246a3562 Zhao Qiang 2016-06-06 188 if (!priv->tx_bd_base) {
c19b6d246a3562 Zhao Qiang 2016-06-06 189 dev_err(priv->dev, "Cannot allocate MURAM memory for TxBDs\n");
c19b6d246a3562 Zhao Qiang 2016-06-06 190 ret = -ENOMEM;
1efb597d8bf56c Zhao Qiang 2016-07-15 191 goto free_rx_bd;
c19b6d246a3562 Zhao Qiang 2016-06-06 192 }
c19b6d246a3562 Zhao Qiang 2016-06-06 193
c19b6d246a3562 Zhao Qiang 2016-06-06 194 /* Alloc parameter ram for ucc hdlc */
85deed56032b6c Holger Brunck 2017-05-22 195 priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param),
c19b6d246a3562 Zhao Qiang 2016-06-06 196 ALIGNMENT_OF_UCC_HDLC_PRAM);
c19b6d246a3562 Zhao Qiang 2016-06-06 197
fd800f646402c0 YueHaibing 2018-07-23 198 if (IS_ERR_VALUE(priv->ucc_pram_offset)) {
24a24d07d688a4 Colin Ian King 2016-08-28 199 dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n");
c19b6d246a3562 Zhao Qiang 2016-06-06 200 ret = -ENOMEM;
1efb597d8bf56c Zhao Qiang 2016-07-15 201 goto free_tx_bd;
c19b6d246a3562 Zhao Qiang 2016-06-06 202 }
c19b6d246a3562 Zhao Qiang 2016-06-06 203
6396bb221514d2 Kees Cook 2018-06-12 204 priv->rx_skbuff = kcalloc(priv->rx_ring_size,
6396bb221514d2 Kees Cook 2018-06-12 205 sizeof(*priv->rx_skbuff),
c19b6d246a3562 Zhao Qiang 2016-06-06 206 GFP_KERNEL);
c19b6d246a3562 Zhao Qiang 2016-06-06 207 if (!priv->rx_skbuff)
1efb597d8bf56c Zhao Qiang 2016-07-15 208 goto free_ucc_pram;
c19b6d246a3562 Zhao Qiang 2016-06-06 209
6396bb221514d2 Kees Cook 2018-06-12 210 priv->tx_skbuff = kcalloc(priv->tx_ring_size,
6396bb221514d2 Kees Cook 2018-06-12 211 sizeof(*priv->tx_skbuff),
c19b6d246a3562 Zhao Qiang 2016-06-06 212 GFP_KERNEL);
c19b6d246a3562 Zhao Qiang 2016-06-06 213 if (!priv->tx_skbuff)
1efb597d8bf56c Zhao Qiang 2016-07-15 214 goto free_rx_skbuff;
c19b6d246a3562 Zhao Qiang 2016-06-06 215
c19b6d246a3562 Zhao Qiang 2016-06-06 216 priv->skb_curtx = 0;
c19b6d246a3562 Zhao Qiang 2016-06-06 217 priv->skb_dirtytx = 0;
c19b6d246a3562 Zhao Qiang 2016-06-06 218 priv->curtx_bd = priv->tx_bd_base;
c19b6d246a3562 Zhao Qiang 2016-06-06 219 priv->dirty_tx = priv->tx_bd_base;
c19b6d246a3562 Zhao Qiang 2016-06-06 220 priv->currx_bd = priv->rx_bd_base;
c19b6d246a3562 Zhao Qiang 2016-06-06 221 priv->currx_bdnum = 0;
c19b6d246a3562 Zhao Qiang 2016-06-06 222
c19b6d246a3562 Zhao Qiang 2016-06-06 223 /* init parameter base */
c19b6d246a3562 Zhao Qiang 2016-06-06 224 cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
c19b6d246a3562 Zhao Qiang 2016-06-06 225 ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock,
c19b6d246a3562 Zhao Qiang 2016-06-06 226 QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset);
c19b6d246a3562 Zhao Qiang 2016-06-06 227
c19b6d246a3562 Zhao Qiang 2016-06-06 228 priv->ucc_pram = (struct ucc_hdlc_param __iomem *)
c19b6d246a3562 Zhao Qiang 2016-06-06 229 qe_muram_addr(priv->ucc_pram_offset);
c19b6d246a3562 Zhao Qiang 2016-06-06 230
c19b6d246a3562 Zhao Qiang 2016-06-06 231 /* Zero out parameter ram */
c19b6d246a3562 Zhao Qiang 2016-06-06 232 memset_io(priv->ucc_pram, 0, sizeof(struct ucc_hdlc_param));
c19b6d246a3562 Zhao Qiang 2016-06-06 233
c19b6d246a3562 Zhao Qiang 2016-06-06 234 /* Alloc riptr, tiptr */
c19b6d246a3562 Zhao Qiang 2016-06-06 235 riptr = qe_muram_alloc(32, 32);
fd800f646402c0 YueHaibing 2018-07-23 236 if (IS_ERR_VALUE(riptr)) {
c19b6d246a3562 Zhao Qiang 2016-06-06 237 dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n");
c19b6d246a3562 Zhao Qiang 2016-06-06 238 ret = -ENOMEM;
1efb597d8bf56c Zhao Qiang 2016-07-15 239 goto free_tx_skbuff;
c19b6d246a3562 Zhao Qiang 2016-06-06 240 }
c19b6d246a3562 Zhao Qiang 2016-06-06 241
c19b6d246a3562 Zhao Qiang 2016-06-06 242 tiptr = qe_muram_alloc(32, 32);
fd800f646402c0 YueHaibing 2018-07-23 243 if (IS_ERR_VALUE(tiptr)) {
c19b6d246a3562 Zhao Qiang 2016-06-06 244 dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n");
c19b6d246a3562 Zhao Qiang 2016-06-06 245 ret = -ENOMEM;
1efb597d8bf56c Zhao Qiang 2016-07-15 246 goto free_riptr;
c19b6d246a3562 Zhao Qiang 2016-06-06 247 }
c19b6d246a3562 Zhao Qiang 2016-06-06 248
c19b6d246a3562 Zhao Qiang 2016-06-06 249 /* Set RIPTR, TIPTR */
c19b6d246a3562 Zhao Qiang 2016-06-06 250 iowrite16be(riptr, &priv->ucc_pram->riptr);
c19b6d246a3562 Zhao Qiang 2016-06-06 251 iowrite16be(tiptr, &priv->ucc_pram->tiptr);
c19b6d246a3562 Zhao Qiang 2016-06-06 252
c19b6d246a3562 Zhao Qiang 2016-06-06 253 /* Set MRBLR */
c19b6d246a3562 Zhao Qiang 2016-06-06 254 iowrite16be(MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr);
c19b6d246a3562 Zhao Qiang 2016-06-06 255
c19b6d246a3562 Zhao Qiang 2016-06-06 256 /* Set RBASE, TBASE */
c19b6d246a3562 Zhao Qiang 2016-06-06 257 iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase);
c19b6d246a3562 Zhao Qiang 2016-06-06 258 iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase);
c19b6d246a3562 Zhao Qiang 2016-06-06 259
c19b6d246a3562 Zhao Qiang 2016-06-06 260 /* Set RSTATE, TSTATE */
c19b6d246a3562 Zhao Qiang 2016-06-06 261 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate);
c19b6d246a3562 Zhao Qiang 2016-06-06 262 iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate);
c19b6d246a3562 Zhao Qiang 2016-06-06 263
c19b6d246a3562 Zhao Qiang 2016-06-06 264 /* Set C_MASK, C_PRES for 16bit CRC */
c19b6d246a3562 Zhao Qiang 2016-06-06 265 iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask);
c19b6d246a3562 Zhao Qiang 2016-06-06 266 iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres);
c19b6d246a3562 Zhao Qiang 2016-06-06 267
c19b6d246a3562 Zhao Qiang 2016-06-06 268 iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr);
c19b6d246a3562 Zhao Qiang 2016-06-06 269 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr);
c19b6d246a3562 Zhao Qiang 2016-06-06 270 iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt);
045f77baf6b429 David Gounaris 2018-09-03 271 iowrite16be(priv->hmask, &priv->ucc_pram->hmask);
c19b6d246a3562 Zhao Qiang 2016-06-06 272 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1);
c19b6d246a3562 Zhao Qiang 2016-06-06 273 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2);
c19b6d246a3562 Zhao Qiang 2016-06-06 274 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3);
c19b6d246a3562 Zhao Qiang 2016-06-06 275 iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4);
c19b6d246a3562 Zhao Qiang 2016-06-06 276
c19b6d246a3562 Zhao Qiang 2016-06-06 277 /* Get BD buffer */
750afb08ca7131 Luis Chamberlain 2019-01-04 278 bd_buffer = dma_alloc_coherent(priv->dev,
750afb08ca7131 Luis Chamberlain 2019-01-04 279 (RX_BD_RING_LEN + TX_BD_RING_LEN) * MAX_RX_BUF_LENGTH,
c19b6d246a3562 Zhao Qiang 2016-06-06 280 &bd_dma_addr, GFP_KERNEL);
c19b6d246a3562 Zhao Qiang 2016-06-06 281
c19b6d246a3562 Zhao Qiang 2016-06-06 282 if (!bd_buffer) {
c19b6d246a3562 Zhao Qiang 2016-06-06 283 dev_err(priv->dev, "Could not allocate buffer descriptors\n");
c19b6d246a3562 Zhao Qiang 2016-06-06 284 ret = -ENOMEM;
1efb597d8bf56c Zhao Qiang 2016-07-15 285 goto free_tiptr;
c19b6d246a3562 Zhao Qiang 2016-06-06 286 }
c19b6d246a3562 Zhao Qiang 2016-06-06 287
c19b6d246a3562 Zhao Qiang 2016-06-06 288 priv->rx_buffer = bd_buffer;
c19b6d246a3562 Zhao Qiang 2016-06-06 289 priv->tx_buffer = bd_buffer + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
c19b6d246a3562 Zhao Qiang 2016-06-06 290
c19b6d246a3562 Zhao Qiang 2016-06-06 291 priv->dma_rx_addr = bd_dma_addr;
c19b6d246a3562 Zhao Qiang 2016-06-06 292 priv->dma_tx_addr = bd_dma_addr + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH;
c19b6d246a3562 Zhao Qiang 2016-06-06 293
c19b6d246a3562 Zhao Qiang 2016-06-06 294 for (i = 0; i < RX_BD_RING_LEN; i++) {
c19b6d246a3562 Zhao Qiang 2016-06-06 295 if (i < (RX_BD_RING_LEN - 1))
c19b6d246a3562 Zhao Qiang 2016-06-06 296 bd_status = R_E_S | R_I_S;
c19b6d246a3562 Zhao Qiang 2016-06-06 297 else
c19b6d246a3562 Zhao Qiang 2016-06-06 298 bd_status = R_E_S | R_I_S | R_W_S;
c19b6d246a3562 Zhao Qiang 2016-06-06 299
c19b6d246a3562 Zhao Qiang 2016-06-06 @300 iowrite16be(bd_status, &priv->rx_bd_base[i].status);
c19b6d246a3562 Zhao Qiang 2016-06-06 301 iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH,
c19b6d246a3562 Zhao Qiang 2016-06-06 @302 &priv->rx_bd_base[i].buf);
c19b6d246a3562 Zhao Qiang 2016-06-06 303 }
c19b6d246a3562 Zhao Qiang 2016-06-06 304
c19b6d246a3562 Zhao Qiang 2016-06-06 305 for (i = 0; i < TX_BD_RING_LEN; i++) {
c19b6d246a3562 Zhao Qiang 2016-06-06 306 if (i < (TX_BD_RING_LEN - 1))
c19b6d246a3562 Zhao Qiang 2016-06-06 307 bd_status = T_I_S | T_TC_S;
c19b6d246a3562 Zhao Qiang 2016-06-06 308 else
c19b6d246a3562 Zhao Qiang 2016-06-06 309 bd_status = T_I_S | T_TC_S | T_W_S;
c19b6d246a3562 Zhao Qiang 2016-06-06 310
c19b6d246a3562 Zhao Qiang 2016-06-06 @311 iowrite16be(bd_status, &priv->tx_bd_base[i].status);
c19b6d246a3562 Zhao Qiang 2016-06-06 312 iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH,
c19b6d246a3562 Zhao Qiang 2016-06-06 @313 &priv->tx_bd_base[i].buf);
c19b6d246a3562 Zhao Qiang 2016-06-06 314 }
c19b6d246a3562 Zhao Qiang 2016-06-06 315
c19b6d246a3562 Zhao Qiang 2016-06-06 316 return 0;
c19b6d246a3562 Zhao Qiang 2016-06-06 317
1efb597d8bf56c Zhao Qiang 2016-07-15 318 free_tiptr:
c19b6d246a3562 Zhao Qiang 2016-06-06 319 qe_muram_free(tiptr);
1efb597d8bf56c Zhao Qiang 2016-07-15 320 free_riptr:
c19b6d246a3562 Zhao Qiang 2016-06-06 321 qe_muram_free(riptr);
1efb597d8bf56c Zhao Qiang 2016-07-15 322 free_tx_skbuff:
c19b6d246a3562 Zhao Qiang 2016-06-06 323 kfree(priv->tx_skbuff);
1efb597d8bf56c Zhao Qiang 2016-07-15 324 free_rx_skbuff:
c19b6d246a3562 Zhao Qiang 2016-06-06 325 kfree(priv->rx_skbuff);
1efb597d8bf56c Zhao Qiang 2016-07-15 326 free_ucc_pram:
c19b6d246a3562 Zhao Qiang 2016-06-06 327 qe_muram_free(priv->ucc_pram_offset);
1efb597d8bf56c Zhao Qiang 2016-07-15 328 free_tx_bd:
c19b6d246a3562 Zhao Qiang 2016-06-06 329 dma_free_coherent(priv->dev,
5b8aad93c52bdd Holger Brunck 2017-05-17 330 TX_BD_RING_LEN * sizeof(struct qe_bd),
c19b6d246a3562 Zhao Qiang 2016-06-06 331 priv->tx_bd_base, priv->dma_tx_bd);
1efb597d8bf56c Zhao Qiang 2016-07-15 332 free_rx_bd:
c19b6d246a3562 Zhao Qiang 2016-06-06 333 dma_free_coherent(priv->dev,
5b8aad93c52bdd Holger Brunck 2017-05-17 334 RX_BD_RING_LEN * sizeof(struct qe_bd),
c19b6d246a3562 Zhao Qiang 2016-06-06 335 priv->rx_bd_base, priv->dma_rx_bd);
1efb597d8bf56c Zhao Qiang 2016-07-15 336 free_uccf:
c19b6d246a3562 Zhao Qiang 2016-06-06 337 ucc_fast_free(priv->uccf);
c19b6d246a3562 Zhao Qiang 2016-06-06 338
c19b6d246a3562 Zhao Qiang 2016-06-06 339 return ret;
c19b6d246a3562 Zhao Qiang 2016-06-06 340 }
c19b6d246a3562 Zhao Qiang 2016-06-06 341
c19b6d246a3562 Zhao Qiang 2016-06-06 342 static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
c19b6d246a3562 Zhao Qiang 2016-06-06 343 {
c19b6d246a3562 Zhao Qiang 2016-06-06 344 hdlc_device *hdlc = dev_to_hdlc(dev);
c19b6d246a3562 Zhao Qiang 2016-06-06 345 struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)hdlc->priv;
c19b6d246a3562 Zhao Qiang 2016-06-06 346 struct qe_bd __iomem *bd;
c19b6d246a3562 Zhao Qiang 2016-06-06 347 u16 bd_status;
c19b6d246a3562 Zhao Qiang 2016-06-06 348 unsigned long flags;
c19b6d246a3562 Zhao Qiang 2016-06-06 349 u16 *proto_head;
c19b6d246a3562 Zhao Qiang 2016-06-06 350
c19b6d246a3562 Zhao Qiang 2016-06-06 351 switch (dev->type) {
c19b6d246a3562 Zhao Qiang 2016-06-06 352 case ARPHRD_RAWHDLC:
c19b6d246a3562 Zhao Qiang 2016-06-06 353 if (skb_headroom(skb) < HDLC_HEAD_LEN) {
c19b6d246a3562 Zhao Qiang 2016-06-06 354 dev->stats.tx_dropped++;
c19b6d246a3562 Zhao Qiang 2016-06-06 355 dev_kfree_skb(skb);
c19b6d246a3562 Zhao Qiang 2016-06-06 356 netdev_err(dev, "No enough space for hdlc head\n");
c19b6d246a3562 Zhao Qiang 2016-06-06 357 return -ENOMEM;
c19b6d246a3562 Zhao Qiang 2016-06-06 358 }
c19b6d246a3562 Zhao Qiang 2016-06-06 359
c19b6d246a3562 Zhao Qiang 2016-06-06 360 skb_push(skb, HDLC_HEAD_LEN);
c19b6d246a3562 Zhao Qiang 2016-06-06 361
c19b6d246a3562 Zhao Qiang 2016-06-06 362 proto_head = (u16 *)skb->data;
c19b6d246a3562 Zhao Qiang 2016-06-06 @363 *proto_head = htons(DEFAULT_HDLC_HEAD);
c19b6d246a3562 Zhao Qiang 2016-06-06 364
c19b6d246a3562 Zhao Qiang 2016-06-06 365 dev->stats.tx_bytes += skb->len;
c19b6d246a3562 Zhao Qiang 2016-06-06 366 break;
c19b6d246a3562 Zhao Qiang 2016-06-06 367
c19b6d246a3562 Zhao Qiang 2016-06-06 368 case ARPHRD_PPP:
c19b6d246a3562 Zhao Qiang 2016-06-06 369 proto_head = (u16 *)skb->data;
c19b6d246a3562 Zhao Qiang 2016-06-06 @370 if (*proto_head != htons(DEFAULT_PPP_HEAD)) {
c19b6d246a3562 Zhao Qiang 2016-06-06 371 dev->stats.tx_dropped++;
c19b6d246a3562 Zhao Qiang 2016-06-06 372 dev_kfree_skb(skb);
c19b6d246a3562 Zhao Qiang 2016-06-06 373 netdev_err(dev, "Wrong ppp header\n");
c19b6d246a3562 Zhao Qiang 2016-06-06 374 return -ENOMEM;
c19b6d246a3562 Zhao Qiang 2016-06-06 375 }
c19b6d246a3562 Zhao Qiang 2016-06-06 376
c19b6d246a3562 Zhao Qiang 2016-06-06 377 dev->stats.tx_bytes += skb->len;
c19b6d246a3562 Zhao Qiang 2016-06-06 378 break;
c19b6d246a3562 Zhao Qiang 2016-06-06 379
8978ca7c8b7b07 David Gounaris 2018-09-03 380 case ARPHRD_ETHER:
8978ca7c8b7b07 David Gounaris 2018-09-03 381 dev->stats.tx_bytes += skb->len;
8978ca7c8b7b07 David Gounaris 2018-09-03 382 break;
8978ca7c8b7b07 David Gounaris 2018-09-03 383
c19b6d246a3562 Zhao Qiang 2016-06-06 384 default:
c19b6d246a3562 Zhao Qiang 2016-06-06 385 dev->stats.tx_dropped++;
c19b6d246a3562 Zhao Qiang 2016-06-06 386 dev_kfree_skb(skb);
c19b6d246a3562 Zhao Qiang 2016-06-06 387 return -ENOMEM;
c19b6d246a3562 Zhao Qiang 2016-06-06 388 }
2e7ad56aa54778 Mathias Thore 2018-11-07 389 netdev_sent_queue(dev, skb->len);
c19b6d246a3562 Zhao Qiang 2016-06-06 390 spin_lock_irqsave(&priv->lock, flags);
c19b6d246a3562 Zhao Qiang 2016-06-06 391
c19b6d246a3562 Zhao Qiang 2016-06-06 392 /* Start from the next BD that should be filled */
c19b6d246a3562 Zhao Qiang 2016-06-06 @393 bd = priv->curtx_bd;
c19b6d246a3562 Zhao Qiang 2016-06-06 394 bd_status = ioread16be(&bd->status);
c19b6d246a3562 Zhao Qiang 2016-06-06 395 /* Save the skb pointer so we can free it later */
c19b6d246a3562 Zhao Qiang 2016-06-06 396 priv->tx_skbuff[priv->skb_curtx] = skb;
c19b6d246a3562 Zhao Qiang 2016-06-06 397
c19b6d246a3562 Zhao Qiang 2016-06-06 398 /* Update the current skb pointer (wrapping if this was the last) */
c19b6d246a3562 Zhao Qiang 2016-06-06 399 priv->skb_curtx =
c19b6d246a3562 Zhao Qiang 2016-06-06 400 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN);
c19b6d246a3562 Zhao Qiang 2016-06-06 401
c19b6d246a3562 Zhao Qiang 2016-06-06 402 /* copy skb data to tx buffer for sdma processing */
c19b6d246a3562 Zhao Qiang 2016-06-06 @403 memcpy(priv->tx_buffer + (be32_to_cpu(bd->buf) - priv->dma_tx_addr),
c19b6d246a3562 Zhao Qiang 2016-06-06 404 skb->data, skb->len);
c19b6d246a3562 Zhao Qiang 2016-06-06 405
c19b6d246a3562 Zhao Qiang 2016-06-06 406 /* set bd status and length */
c19b6d246a3562 Zhao Qiang 2016-06-06 407 bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S;
c19b6d246a3562 Zhao Qiang 2016-06-06 408
c19b6d246a3562 Zhao Qiang 2016-06-06 409 iowrite16be(skb->len, &bd->length);
02bb56ddc67116 Zhao Qiang 2017-03-14 410 iowrite16be(bd_status, &bd->status);
c19b6d246a3562 Zhao Qiang 2016-06-06 411
c19b6d246a3562 Zhao Qiang 2016-06-06 412 /* Move to next BD in the ring */
c19b6d246a3562 Zhao Qiang 2016-06-06 413 if (!(bd_status & T_W_S))
c19b6d246a3562 Zhao Qiang 2016-06-06 414 bd += 1;
c19b6d246a3562 Zhao Qiang 2016-06-06 415 else
c19b6d246a3562 Zhao Qiang 2016-06-06 @416 bd = priv->tx_bd_base;
c19b6d246a3562 Zhao Qiang 2016-06-06 417
c19b6d246a3562 Zhao Qiang 2016-06-06 @418 if (bd == priv->dirty_tx) {
c19b6d246a3562 Zhao Qiang 2016-06-06 419 if (!netif_queue_stopped(dev))
c19b6d246a3562 Zhao Qiang 2016-06-06 420 netif_stop_queue(dev);
c19b6d246a3562 Zhao Qiang 2016-06-06 421 }
c19b6d246a3562 Zhao Qiang 2016-06-06 422
c19b6d246a3562 Zhao Qiang 2016-06-06 423 priv->curtx_bd = bd;
c19b6d246a3562 Zhao Qiang 2016-06-06 424
c19b6d246a3562 Zhao Qiang 2016-06-06 425 spin_unlock_irqrestore(&priv->lock, flags);
c19b6d246a3562 Zhao Qiang 2016-06-06 426
c19b6d246a3562 Zhao Qiang 2016-06-06 427 return NETDEV_TX_OK;
c19b6d246a3562 Zhao Qiang 2016-06-06 428 }
c19b6d246a3562 Zhao Qiang 2016-06-06 429

:::::: The code at line 300 was first introduced by commit
:::::: c19b6d246a35627c3a69b2fa6bdece212b48214b drivers/net: support hdlc function for QE-UCC

:::::: TO: Zhao Qiang <[email protected]>
:::::: CC: David S. Miller <[email protected]>

---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation

2019-10-29 09:58:10

by Christophe Leroy

Subject: Re: [PATCH v2 03/23] soc: fsl: qe: avoid ppc-specific io accessors

Le 25/10/2019 à 14:40, Rasmus Villemoes a écrit :
> In preparation for allowing to build QE support for architectures
> other than PPC, replace the ppc-specific io accessors. Done via
>
> $ spatch --sp-file io.cocci --in-place drivers/soc/fsl/qe/
>
> where io.cocci is
>
> @@
> expression addr, val;
> @@
> - out_be32(addr, val)
> + iowrite32be(val, addr)
>
> @@
> expression addr;
> @@
> - in_be32(addr)
> + ioread32be(addr)
>
> @@
> expression addr, val;
> @@
> - out_be16(addr, val)
> + iowrite16be(val, addr)
>
> @@
> expression addr;
> @@
> - in_be16(addr)
> + ioread16be(addr)
>
> @@
> expression addr, val;
> @@
> - out_8(addr, val)
> + iowrite8(val, addr)
>
> @@
> expression addr;
> @@
> - in_8(addr)
> + ioread8(addr)
>
> @@
> expression addr, clr, set;
> @@
> - clrsetbits_be32(addr, clr, set)
> + qe_clrsetbits32(addr, clr, set)
>
> @@
> expression addr, clr, set;
> @@
> - clrsetbits_be16(addr, clr, set)
> + qe_clrsetbits16(addr, clr, set)
>
> @@
> expression addr, clr, set;
> @@
> - clrsetbits_8(addr, clr, set)
> + qe_clrsetbits8(addr, clr, set)
>
> @@
> expression addr, set;
> @@
> - setbits32(addr, set)
> + qe_setbits32(addr, set)
>
> @@
> expression addr, set;
> @@
> - setbits16(addr, set)
> + qe_setbits16(addr, set)
>
> @@
> expression addr, set;
> @@
> - setbits8(addr, set)
> + qe_setbits8(addr, set)
>
> @@
> expression addr, clr;
> @@
> - clrbits32(addr, clr)
> + qe_clrbits32(addr, clr)
>
> @@
> expression addr, clr;
> @@
> - clrbits16(addr, clr)
> + qe_clrbits16(addr, clr)
>
> @@
> expression addr, clr;
> @@
> - clrbits8(addr, clr)
> + qe_clrbits8(addr, clr)

As discussed already, this patch changes io accesors from inline to
outline, this has a performance impact on powerpc32 like 83xx.

Could you please include in your series before this patch a patch to
change generic io accessors to inline on powerpc ?

Christophe


>
> Signed-off-by: Rasmus Villemoes <[email protected]>
> ---
> drivers/soc/fsl/qe/gpio.c | 30 +++++++--------
> drivers/soc/fsl/qe/qe.c | 35 +++++++++---------
> drivers/soc/fsl/qe/qe_ic.c | 4 +-
> drivers/soc/fsl/qe/qe_io.c | 40 +++++++++-----------
> drivers/soc/fsl/qe/qe_tdm.c | 8 ++--
> drivers/soc/fsl/qe/ucc.c | 16 ++++----
> drivers/soc/fsl/qe/ucc_fast.c | 70 ++++++++++++++++++-----------------
> drivers/soc/fsl/qe/ucc_slow.c | 38 +++++++++----------
> drivers/soc/fsl/qe/usb.c | 2 +-
> 9 files changed, 120 insertions(+), 123 deletions(-)
>
> diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
> index f0c29ed8f0ff..949a35ac253c 100644
> --- a/drivers/soc/fsl/qe/gpio.c
> +++ b/drivers/soc/fsl/qe/gpio.c
> @@ -41,13 +41,13 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
> container_of(mm_gc, struct qe_gpio_chip, mm_gc);
> struct qe_pio_regs __iomem *regs = mm_gc->regs;
>
> - qe_gc->cpdata = in_be32(&regs->cpdata);
> + qe_gc->cpdata = ioread32be(&regs->cpdata);
> qe_gc->saved_regs.cpdata = qe_gc->cpdata;
> - qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
> - qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
> - qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
> - qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
> - qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
> + qe_gc->saved_regs.cpdir1 = ioread32be(&regs->cpdir1);
> + qe_gc->saved_regs.cpdir2 = ioread32be(&regs->cpdir2);
> + qe_gc->saved_regs.cppar1 = ioread32be(&regs->cppar1);
> + qe_gc->saved_regs.cppar2 = ioread32be(&regs->cppar2);
> + qe_gc->saved_regs.cpodr = ioread32be(&regs->cpodr);
> }
>
> static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
> @@ -56,7 +56,7 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
> struct qe_pio_regs __iomem *regs = mm_gc->regs;
> u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
>
> - return !!(in_be32(&regs->cpdata) & pin_mask);
> + return !!(ioread32be(&regs->cpdata) & pin_mask);
> }
>
> static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
> @@ -74,7 +74,7 @@ static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
> else
> qe_gc->cpdata &= ~pin_mask;
>
> - out_be32(&regs->cpdata, qe_gc->cpdata);
> + iowrite32be(qe_gc->cpdata, &regs->cpdata);
>
> spin_unlock_irqrestore(&qe_gc->lock, flags);
> }
> @@ -101,7 +101,7 @@ static void qe_gpio_set_multiple(struct gpio_chip *gc,
> }
> }
>
> - out_be32(&regs->cpdata, qe_gc->cpdata);
> + iowrite32be(qe_gc->cpdata, &regs->cpdata);
>
> spin_unlock_irqrestore(&qe_gc->lock, flags);
> }
> @@ -255,11 +255,11 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)
> spin_lock_irqsave(&qe_gc->lock, flags);
>
> if (second_reg) {
> - clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
> - clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
> + qe_clrsetbits32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
> + qe_clrsetbits32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
> } else {
> - clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
> - clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
> + qe_clrsetbits32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
> + qe_clrsetbits32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
> }
>
> if (sregs->cpdata & mask1)
> @@ -267,8 +267,8 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)
> else
> qe_gc->cpdata &= ~mask1;
>
> - out_be32(&regs->cpdata, qe_gc->cpdata);
> - clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
> + iowrite32be(qe_gc->cpdata, &regs->cpdata);
> + qe_clrsetbits32(&regs->cpodr, mask1, sregs->cpodr & mask1);
>
> spin_unlock_irqrestore(&qe_gc->lock, flags);
> }
> diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
> index 2a0e6e642776..60bf047001be 100644
> --- a/drivers/soc/fsl/qe/qe.c
> +++ b/drivers/soc/fsl/qe/qe.c
> @@ -112,7 +112,7 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
>
> spin_lock_irqsave(&qe_lock, flags);
> if (cmd == QE_RESET) {
> - out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
> + iowrite32be((u32)(cmd | QE_CR_FLG), &qe_immr->cp.cecr);
> } else {
> if (cmd == QE_ASSIGN_PAGE) {
> /* Here device is the SNUM, not sub-block */
> @@ -129,15 +129,14 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
> mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
> }
>
> - out_be32(&qe_immr->cp.cecdr, cmd_input);
> - out_be32(&qe_immr->cp.cecr,
> - (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
> - mcn_protocol << mcn_shift));
> + iowrite32be(cmd_input, &qe_immr->cp.cecdr);
> + iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) | (u32)mcn_protocol << mcn_shift),
> + &qe_immr->cp.cecr);
> }
>
> /* wait for the QE_CR_FLG to clear */
> - ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
> - 100, 0);
> + ret = spin_event_timeout((ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
> + 100, 0);
> /* On timeout (e.g. failure), the expression will be false (ret == 0),
> otherwise it will be true (ret == 1). */
> spin_unlock_irqrestore(&qe_lock, flags);
> @@ -230,7 +229,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
> tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
> QE_BRGC_ENABLE | div16;
>
> - out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
> + iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);
>
> return 0;
> }
> @@ -377,9 +376,9 @@ static int qe_sdma_init(void)
> return -ENOMEM;
> }
>
> - out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
> - out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
> - (0x1 << QE_SDMR_CEN_SHIFT)));
> + iowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK, &sdma->sdebcr);
> + iowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),
> + &sdma->sdmr);
>
> return 0;
> }
> @@ -417,14 +416,14 @@ static void qe_upload_microcode(const void *base,
> "uploading microcode '%s'\n", ucode->id);
>
> /* Use auto-increment */
> - out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
> - QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
> + iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR,
> + &qe_immr->iram.iadd);
>
> for (i = 0; i < be32_to_cpu(ucode->count); i++)
> - out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
> + iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
>
> /* Set I-RAM Ready Register */
> - out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));
> + iowrite32be(be32_to_cpu(QE_IRAM_READY), &qe_immr->iram.iready);
> }
>
> /*
> @@ -509,7 +508,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
> * If the microcode calls for it, split the I-RAM.
> */
> if (!firmware->split)
> - setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
> + qe_setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
>
> if (firmware->soc.model)
> printk(KERN_INFO
> @@ -543,11 +542,11 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
> u32 trap = be32_to_cpu(ucode->traps[j]);
>
> if (trap)
> - out_be32(&qe_immr->rsp[i].tibcr[j], trap);
> + iowrite32be(trap, &qe_immr->rsp[i].tibcr[j]);
> }
>
> /* Enable traps */
> - out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
> + iowrite32be(be32_to_cpu(ucode->eccr), &qe_immr->rsp[i].eccr);
> }
>
> qe_firmware_uploaded = 1;
> diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
> index 791adcd121d1..d420492b4c23 100644
> --- a/drivers/soc/fsl/qe/qe_ic.c
> +++ b/drivers/soc/fsl/qe/qe_ic.c
> @@ -173,13 +173,13 @@ static struct qe_ic_info qe_ic_info[] = {
>
> static inline u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)
> {
> - return in_be32(base + (reg >> 2));
> + return ioread32be(base + (reg >> 2));
> }
>
> static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg,
> u32 value)
> {
> - out_be32(base + (reg >> 2), value);
> + iowrite32be(value, base + (reg >> 2));
> }
>
> static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
> diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c
> index 3657e296a8a2..776a2c9361e1 100644
> --- a/drivers/soc/fsl/qe/qe_io.c
> +++ b/drivers/soc/fsl/qe/qe_io.c
> @@ -57,16 +57,16 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
> pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));
>
> /* Set open drain, if required */
> - tmp_val = in_be32(&par_io->cpodr);
> + tmp_val = ioread32be(&par_io->cpodr);
> if (open_drain)
> - out_be32(&par_io->cpodr, pin_mask1bit | tmp_val);
> + iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);
> else
> - out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val);
> + iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);
>
> /* define direction */
> tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
> - in_be32(&par_io->cpdir2) :
> - in_be32(&par_io->cpdir1);
> + ioread32be(&par_io->cpdir2) :
> + ioread32be(&par_io->cpdir1);
>
> /* get all bits mask for 2 bit per port */
> pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
> @@ -78,34 +78,30 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
>
> /* clear and set 2 bits mask */
> if (pin > (QE_PIO_PINS / 2) - 1) {
> - out_be32(&par_io->cpdir2,
> - ~pin_mask2bits & tmp_val);
> + iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);
> tmp_val &= ~pin_mask2bits;
> - out_be32(&par_io->cpdir2, new_mask2bits | tmp_val);
> + iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);
> } else {
> - out_be32(&par_io->cpdir1,
> - ~pin_mask2bits & tmp_val);
> + iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);
> tmp_val &= ~pin_mask2bits;
> - out_be32(&par_io->cpdir1, new_mask2bits | tmp_val);
> + iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);
> }
> /* define pin assignment */
> tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
> - in_be32(&par_io->cppar2) :
> - in_be32(&par_io->cppar1);
> + ioread32be(&par_io->cppar2) :
> + ioread32be(&par_io->cppar1);
>
> new_mask2bits = (u32) (assignment << (QE_PIO_PINS -
> (pin % (QE_PIO_PINS / 2) + 1) * 2));
> /* clear and set 2 bits mask */
> if (pin > (QE_PIO_PINS / 2) - 1) {
> - out_be32(&par_io->cppar2,
> - ~pin_mask2bits & tmp_val);
> + iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);
> tmp_val &= ~pin_mask2bits;
> - out_be32(&par_io->cppar2, new_mask2bits | tmp_val);
> + iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);
> } else {
> - out_be32(&par_io->cppar1,
> - ~pin_mask2bits & tmp_val);
> + iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);
> tmp_val &= ~pin_mask2bits;
> - out_be32(&par_io->cppar1, new_mask2bits | tmp_val);
> + iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);
> }
> }
> EXPORT_SYMBOL(__par_io_config_pin);
> @@ -133,12 +129,12 @@ int par_io_data_set(u8 port, u8 pin, u8 val)
> /* calculate pin location */
> pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));
>
> - tmp_val = in_be32(&par_io[port].cpdata);
> + tmp_val = ioread32be(&par_io[port].cpdata);
>
> if (val == 0) /* clear */
> - out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val);
> + iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);
> else /* set */
> - out_be32(&par_io[port].cpdata, pin_mask | tmp_val);
> + iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);
>
> return 0;
> }
> diff --git a/drivers/soc/fsl/qe/qe_tdm.c b/drivers/soc/fsl/qe/qe_tdm.c
> index e37ebc3be661..e7b1c8e3d229 100644
> --- a/drivers/soc/fsl/qe/qe_tdm.c
> +++ b/drivers/soc/fsl/qe/qe_tdm.c
> @@ -169,10 +169,10 @@ void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)
> &siram[siram_entry_id * 32 + 0x200 + i]);
> }
>
> - setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
> - SIR_LAST);
> - setbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],
> - SIR_LAST);
> + qe_setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
> + SIR_LAST);
> + qe_setbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],
> + SIR_LAST);
>
> /* Set SIxMR register */
> sixmr = SIMR_SAD(siram_entry_id);
> diff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c
> index 024d239ac1e1..583d6b5aaf5c 100644
> --- a/drivers/soc/fsl/qe/ucc.c
> +++ b/drivers/soc/fsl/qe/ucc.c
> @@ -35,8 +35,8 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
> return -EINVAL;
>
> spin_lock_irqsave(&cmxgcr_lock, flags);
> - clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
> - ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
> + qe_clrsetbits32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
> + ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
> spin_unlock_irqrestore(&cmxgcr_lock, flags);
>
> return 0;
> @@ -80,8 +80,8 @@ int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
> return -EINVAL;
> }
>
> - clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
> - UCC_GUEMR_SET_RESERVED3 | speed);
> + qe_clrsetbits8(guemr, UCC_GUEMR_MODE_MASK,
> + UCC_GUEMR_SET_RESERVED3 | speed);
>
> return 0;
> }
> @@ -109,9 +109,9 @@ int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
> get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift);
>
> if (set)
> - setbits32(cmxucr, mask << shift);
> + qe_setbits32(cmxucr, mask << shift);
> else
> - clrbits32(cmxucr, mask << shift);
> + qe_clrbits32(cmxucr, mask << shift);
>
> return 0;
> }
> @@ -207,8 +207,8 @@ int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
> if (mode == COMM_DIR_RX)
> shift += 4;
>
> - clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
> - clock_bits << shift);
> + qe_clrsetbits32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
> + clock_bits << shift);
>
> return 0;
> }
> diff --git a/drivers/soc/fsl/qe/ucc_fast.c b/drivers/soc/fsl/qe/ucc_fast.c
> index af4d80e38521..bda5222aadf3 100644
> --- a/drivers/soc/fsl/qe/ucc_fast.c
> +++ b/drivers/soc/fsl/qe/ucc_fast.c
> @@ -29,41 +29,41 @@ void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
> printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);
>
> printk(KERN_INFO "gumr : addr=0x%p, val=0x%08x\n",
> - &uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
> + &uccf->uf_regs->gumr, ioread32be(&uccf->uf_regs->gumr));
> printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n",
> - &uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
> + &uccf->uf_regs->upsmr, ioread32be(&uccf->uf_regs->upsmr));
> printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n",
> - &uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
> + &uccf->uf_regs->utodr, ioread16be(&uccf->uf_regs->utodr));
> printk(KERN_INFO "udsr : addr=0x%p, val=0x%04x\n",
> - &uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
> + &uccf->uf_regs->udsr, ioread16be(&uccf->uf_regs->udsr));
> printk(KERN_INFO "ucce : addr=0x%p, val=0x%08x\n",
> - &uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
> + &uccf->uf_regs->ucce, ioread32be(&uccf->uf_regs->ucce));
> printk(KERN_INFO "uccm : addr=0x%p, val=0x%08x\n",
> - &uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
> + &uccf->uf_regs->uccm, ioread32be(&uccf->uf_regs->uccm));
> printk(KERN_INFO "uccs : addr=0x%p, val=0x%02x\n",
> - &uccf->uf_regs->uccs, in_8(&uccf->uf_regs->uccs));
> + &uccf->uf_regs->uccs, ioread8(&uccf->uf_regs->uccs));
> printk(KERN_INFO "urfb : addr=0x%p, val=0x%08x\n",
> - &uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
> + &uccf->uf_regs->urfb, ioread32be(&uccf->uf_regs->urfb));
> printk(KERN_INFO "urfs : addr=0x%p, val=0x%04x\n",
> - &uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
> + &uccf->uf_regs->urfs, ioread16be(&uccf->uf_regs->urfs));
> printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n",
> - &uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
> + &uccf->uf_regs->urfet, ioread16be(&uccf->uf_regs->urfet));
> printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n",
> - &uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset));
> + &uccf->uf_regs->urfset, ioread16be(&uccf->uf_regs->urfset));
> printk(KERN_INFO "utfb : addr=0x%p, val=0x%08x\n",
> - &uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
> + &uccf->uf_regs->utfb, ioread32be(&uccf->uf_regs->utfb));
> printk(KERN_INFO "utfs : addr=0x%p, val=0x%04x\n",
> - &uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
> + &uccf->uf_regs->utfs, ioread16be(&uccf->uf_regs->utfs));
> printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n",
> - &uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
> + &uccf->uf_regs->utfet, ioread16be(&uccf->uf_regs->utfet));
> printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n",
> - &uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
> + &uccf->uf_regs->utftt, ioread16be(&uccf->uf_regs->utftt));
> printk(KERN_INFO "utpt : addr=0x%p, val=0x%04x\n",
> - &uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
> + &uccf->uf_regs->utpt, ioread16be(&uccf->uf_regs->utpt));
> printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",
> - &uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
> + &uccf->uf_regs->urtry, ioread32be(&uccf->uf_regs->urtry));
> printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",
> - &uccf->uf_regs->guemr, in_8(&uccf->uf_regs->guemr));
> + &uccf->uf_regs->guemr, ioread8(&uccf->uf_regs->guemr));
> }
> EXPORT_SYMBOL(ucc_fast_dump_regs);
>
> @@ -85,7 +85,7 @@ EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock);
>
> void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
> {
> - out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
> + iowrite16be(UCC_FAST_TOD, &uccf->uf_regs->utodr);
> }
> EXPORT_SYMBOL(ucc_fast_transmit_on_demand);
>
> @@ -97,7 +97,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
> uf_regs = uccf->uf_regs;
>
> /* Enable reception and/or transmission on this UCC. */
> - gumr = in_be32(&uf_regs->gumr);
> + gumr = ioread32be(&uf_regs->gumr);
> if (mode & COMM_DIR_TX) {
> gumr |= UCC_FAST_GUMR_ENT;
> uccf->enabled_tx = 1;
> @@ -106,7 +106,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
> gumr |= UCC_FAST_GUMR_ENR;
> uccf->enabled_rx = 1;
> }
> - out_be32(&uf_regs->gumr, gumr);
> + iowrite32be(gumr, &uf_regs->gumr);
> }
> EXPORT_SYMBOL(ucc_fast_enable);
>
> @@ -118,7 +118,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
> uf_regs = uccf->uf_regs;
>
> /* Disable reception and/or transmission on this UCC. */
> - gumr = in_be32(&uf_regs->gumr);
> + gumr = ioread32be(&uf_regs->gumr);
> if (mode & COMM_DIR_TX) {
> gumr &= ~UCC_FAST_GUMR_ENT;
> uccf->enabled_tx = 0;
> @@ -127,7 +127,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
> gumr &= ~UCC_FAST_GUMR_ENR;
> uccf->enabled_rx = 0;
> }
> - out_be32(&uf_regs->gumr, gumr);
> + iowrite32be(gumr, &uf_regs->gumr);
> }
> EXPORT_SYMBOL(ucc_fast_disable);
>
> @@ -259,7 +259,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
> gumr |= uf_info->tenc;
> gumr |= uf_info->tcrc;
> gumr |= uf_info->mode;
> - out_be32(&uf_regs->gumr, gumr);
> + iowrite32be(gumr, &uf_regs->gumr);
>
> /* Allocate memory for Tx Virtual Fifo */
> uccf->ucc_fast_tx_virtual_fifo_base_offset =
> @@ -286,15 +286,17 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
> }
>
> /* Set Virtual Fifo registers */
> - out_be16(&uf_regs->urfs, uf_info->urfs);
> - out_be16(&uf_regs->urfet, uf_info->urfet);
> - out_be16(&uf_regs->urfset, uf_info->urfset);
> - out_be16(&uf_regs->utfs, uf_info->utfs);
> - out_be16(&uf_regs->utfet, uf_info->utfet);
> - out_be16(&uf_regs->utftt, uf_info->utftt);
> + iowrite16be(uf_info->urfs, &uf_regs->urfs);
> + iowrite16be(uf_info->urfet, &uf_regs->urfet);
> + iowrite16be(uf_info->urfset, &uf_regs->urfset);
> + iowrite16be(uf_info->utfs, &uf_regs->utfs);
> + iowrite16be(uf_info->utfet, &uf_regs->utfet);
> + iowrite16be(uf_info->utftt, &uf_regs->utftt);
> /* utfb, urfb are offsets from MURAM base */
> - out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);
> - out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);
> + iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset,
> + &uf_regs->utfb);
> + iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset,
> + &uf_regs->urfb);
>
> /* Mux clocking */
> /* Grant Support */
> @@ -362,14 +364,14 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
> }
>
> /* Set interrupt mask register at UCC level. */
> - out_be32(&uf_regs->uccm, uf_info->uccm_mask);
> + iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
>
> /* First, clear anything pending at UCC level,
> * otherwise, old garbage may come through
> * as soon as the dam is opened. */
>
> /* Writing '1' clears */
> - out_be32(&uf_regs->ucce, 0xffffffff);
> + iowrite32be(0xffffffff, &uf_regs->ucce);
>
> *uccf_ret = uccf;
> return 0;
> diff --git a/drivers/soc/fsl/qe/ucc_slow.c b/drivers/soc/fsl/qe/ucc_slow.c
> index 34f0ec3a63b5..74213f8b361c 100644
> --- a/drivers/soc/fsl/qe/ucc_slow.c
> +++ b/drivers/soc/fsl/qe/ucc_slow.c
> @@ -78,7 +78,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
> us_regs = uccs->us_regs;
>
> /* Enable reception and/or transmission on this UCC. */
> - gumr_l = in_be32(&us_regs->gumr_l);
> + gumr_l = ioread32be(&us_regs->gumr_l);
> if (mode & COMM_DIR_TX) {
> gumr_l |= UCC_SLOW_GUMR_L_ENT;
> uccs->enabled_tx = 1;
> @@ -87,7 +87,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
> gumr_l |= UCC_SLOW_GUMR_L_ENR;
> uccs->enabled_rx = 1;
> }
> - out_be32(&us_regs->gumr_l, gumr_l);
> + iowrite32be(gumr_l, &us_regs->gumr_l);
> }
> EXPORT_SYMBOL(ucc_slow_enable);
>
> @@ -99,7 +99,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
> us_regs = uccs->us_regs;
>
> /* Disable reception and/or transmission on this UCC. */
> - gumr_l = in_be32(&us_regs->gumr_l);
> + gumr_l = ioread32be(&us_regs->gumr_l);
> if (mode & COMM_DIR_TX) {
> gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
> uccs->enabled_tx = 0;
> @@ -108,7 +108,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
> gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
> uccs->enabled_rx = 0;
> }
> - out_be32(&us_regs->gumr_l, gumr_l);
> + iowrite32be(gumr_l, &us_regs->gumr_l);
> }
> EXPORT_SYMBOL(ucc_slow_disable);
>
> @@ -198,7 +198,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
> return ret;
> }
>
> - out_be16(&uccs->us_pram->mrblr, us_info->max_rx_buf_length);
> + iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr);
>
> INIT_LIST_HEAD(&uccs->confQ);
>
> @@ -228,27 +228,27 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
> bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
> for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) {
> /* clear bd buffer */
> - out_be32(&bd->buf, 0);
> + iowrite32be(0, &bd->buf);
> /* set bd status and length */
> - out_be32((u32 *) bd, 0);
> + iowrite32be(0, (u32 *)bd);
> bd++;
> }
> /* for last BD set Wrap bit */
> - out_be32(&bd->buf, 0);
> - out_be32((u32 *) bd, cpu_to_be32(T_W));
> + iowrite32be(0, &bd->buf);
> + iowrite32be(cpu_to_be32(T_W), (u32 *)bd);
>
> /* Init Rx bds */
> bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
> for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {
> /* set bd status and length */
> - out_be32((u32*)bd, 0);
> + iowrite32be(0, (u32 *)bd);
> /* clear bd buffer */
> - out_be32(&bd->buf, 0);
> + iowrite32be(0, &bd->buf);
> bd++;
> }
> /* for last BD set Wrap bit */
> - out_be32((u32*)bd, cpu_to_be32(R_W));
> - out_be32(&bd->buf, 0);
> + iowrite32be(cpu_to_be32(R_W), (u32 *)bd);
> + iowrite32be(0, &bd->buf);
>
> /* Set GUMR (For more details see the hardware spec.). */
> /* gumr_h */
> @@ -269,7 +269,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
> gumr |= UCC_SLOW_GUMR_H_TXSY;
> if (us_info->rtsm)
> gumr |= UCC_SLOW_GUMR_H_RTSM;
> - out_be32(&us_regs->gumr_h, gumr);
> + iowrite32be(gumr, &us_regs->gumr_h);
>
> /* gumr_l */
> gumr = us_info->tdcr | us_info->rdcr | us_info->tenc | us_info->renc |
> @@ -282,7 +282,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
> gumr |= UCC_SLOW_GUMR_L_TINV;
> if (us_info->tend)
> gumr |= UCC_SLOW_GUMR_L_TEND;
> - out_be32(&us_regs->gumr_l, gumr);
> + iowrite32be(gumr, &us_regs->gumr_l);
>
> /* Function code registers */
>
> @@ -292,8 +292,8 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
> uccs->us_pram->rbmr = UCC_BMR_BO_BE;
>
> /* rbase, tbase are offsets from MURAM base */
> - out_be16(&uccs->us_pram->rbase, uccs->rx_base_offset);
> - out_be16(&uccs->us_pram->tbase, uccs->tx_base_offset);
> + iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase);
> + iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase);
>
> /* Mux clocking */
> /* Grant Support */
> @@ -323,14 +323,14 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
> }
>
> /* Set interrupt mask register at UCC level. */
> - out_be16(&us_regs->uccm, us_info->uccm_mask);
> + iowrite16be(us_info->uccm_mask, &us_regs->uccm);
>
> /* First, clear anything pending at UCC level,
> * otherwise, old garbage may come through
> * as soon as the dam is opened. */
>
> /* Writing '1' clears */
> - out_be16(&us_regs->ucce, 0xffff);
> + iowrite16be(0xffff, &us_regs->ucce);
>
> /* Issue QE Init command */
> if (us_info->init_tx && us_info->init_rx)
> diff --git a/drivers/soc/fsl/qe/usb.c b/drivers/soc/fsl/qe/usb.c
> index 32d8269fa692..59b326e924dc 100644
> --- a/drivers/soc/fsl/qe/usb.c
> +++ b/drivers/soc/fsl/qe/usb.c
> @@ -43,7 +43,7 @@ int qe_usb_clock_set(enum qe_clock clk, int rate)
>
> spin_lock_irqsave(&cmxgcr_lock, flags);
>
> - clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);
> + qe_clrsetbits32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);
>
> spin_unlock_irqrestore(&cmxgcr_lock, flags);
>
>

2019-10-29 22:52:25

by Rasmus Villemoes

Subject: Re: [PATCH v2 20/23] serial: make SERIAL_QE depend on PPC32

On 29/10/2019 23.44, Leo Li wrote:
>
>
>> -----Original Message-----
>> From: Rasmus Villemoes <[email protected]>
>> Sent: Friday, October 25, 2019 7:41 AM
>> To: Qiang Zhao <[email protected]>; Leo Li <[email protected]>;
>> Christophe Leroy <[email protected]>
>> Cc: [email protected]; [email protected];
>> [email protected]; Scott Wood <[email protected]>; Valentin
>> Longchamp <[email protected]>; Rasmus Villemoes
>> <[email protected]>; [email protected]
>> Subject: [PATCH v2 20/23] serial: make SERIAL_QE depend on PPC32
>>
>> Currently SERIAL_QE depends on QUICC_ENGINE, which in turn depends on
>> PPC32, so this doesn't add any extra dependency. However, the QUICC
>> Engine IP block also exists on some arm boards, so this serves as preparation
>> for removing the PPC32 dependency from QUICC_ENGINE and build the QE
>> support in drivers/soc/fsl/qe, while preventing allmodconfig/randconfig
>> failures due to SERIAL_QE not being supported yet.
>>
>> Signed-off-by: Rasmus Villemoes <[email protected]>
>
> I think your purpose of this series is to make the QE UART not depending on PPC32. If it does accomplish that then we don't need this change.

Yeah, as I've said in private, I now have the patches to make this work,
so this patch (and the later one removing it again) are both gone from
my current dev branch. I'll still wait a day or two to allow the ppc
people to respond to the inline/OOL iowrite32be issue, but after that
I'll resend the whole series.

Rasmus

2019-10-29 22:52:49

by Leo Li

Subject: RE: [PATCH v2 20/23] serial: make SERIAL_QE depend on PPC32

> -----Original Message-----
> From: Rasmus Villemoes <[email protected]>
> Sent: Friday, October 25, 2019 7:41 AM
> To: Qiang Zhao <[email protected]>; Leo Li <[email protected]>;
> Christophe Leroy <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; Scott Wood <[email protected]>; Valentin
> Longchamp <[email protected]>; Rasmus Villemoes
> <[email protected]>; [email protected]
> Subject: [PATCH v2 20/23] serial: make SERIAL_QE depend on PPC32
>
> Currently SERIAL_QE depends on QUICC_ENGINE, which in turn depends on
> PPC32, so this doesn't add any extra dependency. However, the QUICC
> Engine IP block also exists on some arm boards, so this serves as preparation
> for removing the PPC32 dependency from QUICC_ENGINE and build the QE
> support in drivers/soc/fsl/qe, while preventing allmodconfig/randconfig
> failures due to SERIAL_QE not being supported yet.
>
> Signed-off-by: Rasmus Villemoes <[email protected]>

I think your purpose of this series is to make the QE UART not depending on PPC32. If it does accomplish that then we don't need this change.

> ---
> drivers/tty/serial/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index
> 67a9eb3f94ce..78246f535809 100644
> --- a/drivers/tty/serial/Kconfig
> +++ b/drivers/tty/serial/Kconfig
> @@ -1056,6 +1056,7 @@ config SERIAL_LANTIQ config SERIAL_QE
> tristate "Freescale QUICC Engine serial port support"
> depends on QUICC_ENGINE
> + depends on PPC32
> select SERIAL_CORE
> select FW_LOADER
> help
> --
> 2.23.0

2019-10-30 00:38:25

by Michael Ellerman

Subject: Re: [PATCH 4/7] soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic

Rasmus Villemoes <[email protected]> writes:
> On 18/10/2019 18.08, Christoph Hellwig wrote:
>> On Fri, Oct 18, 2019 at 02:52:31PM +0200, Rasmus Villemoes wrote:
>>> /* wait for the QE_CR_FLG to clear */
>>> - ret = spin_event_timeout((ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
>>> - 100, 0);
>>> - /* On timeout (e.g. failure), the expression will be false (ret == 0),
>>> - otherwise it will be true (ret == 1). */
>>> + ret = readx_poll_timeout_atomic(ioread32be, &qe_immr->cp.cecr, val, (val & QE_CR_FLG) == 0,
>>
>> This creates an overly long line.
>
> Yeah, readx_poll_timeout_atomic is a mouthful, and then one also has to
> put in the name of the accessor... I'll wrap it when I respin the
> series, thanks.
>
>> Btw, given how few users of spin_event_timeout we have it might be good
>> idea to just kill it entirely.
>
> Maybe. That's for the ppc folks to comment on; the iopoll.h helpers are
> not completely equivalent (because obviously they don't read tbl
> directly).

AFAICS it was added by and only ever used by Freescale folks, most of
whom have now moved on to other things.

I'd be happy to see it replaced with something generic.

I created an issue in our github to remind us to do that cleanup. Though
in practice that probably just means we'll never get around to it:

https://github.com/linuxppc/issues/issues/280

> Maybe the generic versions should be taught
> spin_begin/spin_end/spin_cpu_relax so at least that part would be
> drop-in replacement.

That would be nice. Though TBH the intersection of platforms that use
spin_event_timeout() and also define a non-empty spin_begin() etc. is
close to if not zero.

cheers

2019-10-30 10:49:41

by Christophe Leroy

Subject: Re: [PATCH v2 09/23] soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c

Le 25/10/2019 à 14:40, Rasmus Villemoes a écrit :
> These functions are only ever called through a function pointer, and
> therefore it makes no sense for them to be "static inline" - gcc has
> no choice but to emit a copy in each translation unit that takes the
> address of one of these (currently various platform code under
> arch/powerpc/). So move them into qe_ic.c and leave ordinary extern
> declarations in the header file.

What is the point in moving fonctions that you will drop in the next
patch (qe_ic_cascade_low_ipic() and qe_ic_cascade_high_ipic())
Only move the ones that will remain.

Christophe


>
> Signed-off-by: Rasmus Villemoes <[email protected]>
> ---
> drivers/soc/fsl/qe/qe_ic.c | 58 +++++++++++++++++++++++++++++++++++
> include/soc/fsl/qe/qe_ic.h | 62 +++-----------------------------------
> 2 files changed, 63 insertions(+), 57 deletions(-)
>
> diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
> index 7b1870d2866a..a847b2672e90 100644
> --- a/drivers/soc/fsl/qe/qe_ic.c
> +++ b/drivers/soc/fsl/qe/qe_ic.c
> @@ -402,6 +402,64 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
> return irq_linear_revmap(qe_ic->irqhost, irq);
> }
>
> +void qe_ic_cascade_low_ipic(struct irq_desc *desc)
> +{
> + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
> + unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
> +
> + if (cascade_irq != NO_IRQ)
> + generic_handle_irq(cascade_irq);
> +}
> +
> +void qe_ic_cascade_high_ipic(struct irq_desc *desc)
> +{
> + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
> + unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
> +
> + if (cascade_irq != NO_IRQ)
> + generic_handle_irq(cascade_irq);
> +}
> +
> +void qe_ic_cascade_low_mpic(struct irq_desc *desc)
> +{
> + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
> + unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> +
> + if (cascade_irq != NO_IRQ)
> + generic_handle_irq(cascade_irq);
> +
> + chip->irq_eoi(&desc->irq_data);
> +}
> +
> +void qe_ic_cascade_high_mpic(struct irq_desc *desc)
> +{
> + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
> + unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> +
> + if (cascade_irq != NO_IRQ)
> + generic_handle_irq(cascade_irq);
> +
> + chip->irq_eoi(&desc->irq_data);
> +}
> +
> +void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
> +{
> + struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
> + unsigned int cascade_irq;
> + struct irq_chip *chip = irq_desc_get_chip(desc);
> +
> + cascade_irq = qe_ic_get_high_irq(qe_ic);
> + if (cascade_irq == NO_IRQ)
> + cascade_irq = qe_ic_get_low_irq(qe_ic);
> +
> + if (cascade_irq != NO_IRQ)
> + generic_handle_irq(cascade_irq);
> +
> + chip->irq_eoi(&desc->irq_data);
> +}
> +
> void __init qe_ic_init(struct device_node *node, unsigned int flags,
> void (*low_handler)(struct irq_desc *desc),
> void (*high_handler)(struct irq_desc *desc))
> diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
> index 714a9b890d8d..f3492eb13052 100644
> --- a/include/soc/fsl/qe/qe_ic.h
> +++ b/include/soc/fsl/qe/qe_ic.h
> @@ -74,62 +74,10 @@ void qe_ic_set_highest_priority(unsigned int virq, int high);
> int qe_ic_set_priority(unsigned int virq, unsigned int priority);
> int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
>
> -static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
> -{
> - struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
> - unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
> -
> - if (cascade_irq != NO_IRQ)
> - generic_handle_irq(cascade_irq);
> -}
> -
> -static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
> -{
> - struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
> - unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
> -
> - if (cascade_irq != NO_IRQ)
> - generic_handle_irq(cascade_irq);
> -}
> -
> -static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
> -{
> - struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
> - unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
> - struct irq_chip *chip = irq_desc_get_chip(desc);
> -
> - if (cascade_irq != NO_IRQ)
> - generic_handle_irq(cascade_irq);
> -
> - chip->irq_eoi(&desc->irq_data);
> -}
> -
> -static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
> -{
> - struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
> - unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
> - struct irq_chip *chip = irq_desc_get_chip(desc);
> -
> - if (cascade_irq != NO_IRQ)
> - generic_handle_irq(cascade_irq);
> -
> - chip->irq_eoi(&desc->irq_data);
> -}
> -
> -static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
> -{
> - struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
> - unsigned int cascade_irq;
> - struct irq_chip *chip = irq_desc_get_chip(desc);
> -
> - cascade_irq = qe_ic_get_high_irq(qe_ic);
> - if (cascade_irq == NO_IRQ)
> - cascade_irq = qe_ic_get_low_irq(qe_ic);
> -
> - if (cascade_irq != NO_IRQ)
> - generic_handle_irq(cascade_irq);
> -
> - chip->irq_eoi(&desc->irq_data);
> -}
> +void qe_ic_cascade_low_ipic(struct irq_desc *desc);
> +void qe_ic_cascade_high_ipic(struct irq_desc *desc);
> +void qe_ic_cascade_low_mpic(struct irq_desc *desc);
> +void qe_ic_cascade_high_mpic(struct irq_desc *desc);
> +void qe_ic_cascade_muxed_mpic(struct irq_desc *desc);
>
> #endif /* _ASM_POWERPC_QE_IC_H */
>

2019-10-30 10:56:55

by Christophe Leroy

Subject: Re: [PATCH v2 19/23] net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32

Le 25/10/2019 à 14:40, Rasmus Villemoes a écrit :
> Currently, QUICC_ENGINE depends on PPC32, so this in itself does not
> change anything. In order to allow removing the PPC32 dependency from
> QUICC_ENGINE and avoid allmodconfig build failures, add this explicit
> dependency.
>
> Signed-off-by: Rasmus Villemoes <[email protected]>
> ---
> drivers/net/ethernet/freescale/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/net/ethernet/freescale/Kconfig b/drivers/net/ethernet/freescale/Kconfig
> index 6a7e8993119f..97d27c7740d4 100644
> --- a/drivers/net/ethernet/freescale/Kconfig
> +++ b/drivers/net/ethernet/freescale/Kconfig
> @@ -75,6 +75,7 @@ config FSL_XGMAC_MDIO
> config UCC_GETH
> tristate "Freescale QE Gigabit Ethernet"
> depends on QUICC_ENGINE
> + depends on PPC32

I think it would be more obvious to have:
depends on QUICC_ENGINE && PPC32

Christophe

> select FSL_PQ_MDIO
> select PHYLIB
> ---help---
>

2019-10-30 10:57:54

by Christophe Leroy

Subject: Re: [PATCH v2 20/23] serial: make SERIAL_QE depend on PPC32

Le 25/10/2019 à 14:40, Rasmus Villemoes a écrit :
> Currently SERIAL_QE depends on QUICC_ENGINE, which in turn depends on
> PPC32, so this doesn't add any extra dependency. However, the QUICC
> Engine IP block also exists on some arm boards, so this serves as
> preparation for removing the PPC32 dependency from QUICC_ENGINE and
> build the QE support in drivers/soc/fsl/qe, while preventing
> allmodconfig/randconfig failures due to SERIAL_QE not being supported
> yet.
>
> Signed-off-by: Rasmus Villemoes <[email protected]>
> ---
> drivers/tty/serial/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
> index 67a9eb3f94ce..78246f535809 100644
> --- a/drivers/tty/serial/Kconfig
> +++ b/drivers/tty/serial/Kconfig
> @@ -1056,6 +1056,7 @@ config SERIAL_LANTIQ
> config SERIAL_QE
> tristate "Freescale QUICC Engine serial port support"
> depends on QUICC_ENGINE
> + depends on PPC32

Same, would be more obvious as
depends on QUICC_ENGINE && PPC32

Christophe

> select SERIAL_CORE
> select FW_LOADER
> help
>

2019-11-01 12:44:11

by Rasmus Villemoes

Subject: [PATCH v3 00/36] QUICC Engine support on ARM

There have been several attempts in the past few years to allow
building the QUICC engine drivers for platforms other than PPC. This
is yet another attempt.

Changes in v3:

- Address the performance impact on ppc from replacing out_be32 by
iowrite32be by instead introducing a qe_iowrite32be wrapper and
using that - patches 3 and 4 in this series.

- Extend the series so that both the QE core as well as ucc_uart
builds for ARM - patches 26-33.

- Reorganize things a bit to avoid touching code that gets killed
anyway in a later patch.

Also the patches are now better grouped:

1-5 are about replacing in_be32 etc. in the core QE code (drivers/soc/fsl/qe).

6-8 handle miscellaneous other ppcisms.

9-21 deal with qe_ic: Simplifying the driver significantly by removing
unused code, and removing the platform-specific initialization from
arch/powerpc/.

22-25 deal with raw access to devicetree properties in native endianness.

26-33 makes drivers/tty/serial/ucc_uart.c (CONFIG_SERIAL_QE) ready to build on arm.

34-36 remove the PPC32 dependency from QUICC_ENGINE. Two drivers that
depend on QUICC_ENGINE get an explicit PPC32 dependency to prevent
allmodconfig build failures.

The series has been built and booted on both an mpc8309-based platform
(ppc) as well as an ls1021a-based platform (arm). The core QE code is
exercised on both, while I could only test the ucc_uart on arm, since
the uarts are not wired up on our mpc8309 board.

Rasmus Villemoes (36):
soc: fsl: qe: remove space-before-tab
soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs
soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers
soc: fsl: qe: introduce qe_io{read,write}* wrappers
soc: fsl: qe: avoid ppc-specific io accessors
soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic
soc: fsl: qe: qe.c: guard use of pvr_version_is() with CONFIG_PPC32
soc: fsl: qe: drop unneeded #includes
soc: fsl: qe: drop assign-only high_active in qe_ic_init
soc: fsl: qe: remove pointless sysfs registration in qe_ic.c
soc: fsl: qe: use qe_ic_cascade_{low,high}_mpic also on 83xx
soc: fsl: qe: move calls of qe_ic_init out of arch/powerpc/
powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQ
powerpc/85xx: remove mostly pointless mpc85xx_qe_init()
soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c
soc: fsl: qe: rename qe_ic_cascade_low_mpic -> qe_ic_cascade_low
soc: fsl: qe: remove unused qe_ic_set_* functions
soc: fsl: qe: don't use NO_IRQ in qe_ic.c
soc: fsl: qe: make qe_ic_get_{low,high}_irq static
soc: fsl: qe: simplify qe_ic_init()
soc: fsl: qe: merge qe_ic.h headers into qe_ic.c
soc: fsl: qe: qe.c: use of_property_read_* helpers
soc: fsl: qe: qe_io.c: don't open-code of_parse_phandle()
soc: fsl: qe: qe_io.c: access device tree property using be32_to_cpu
soc: fsl: qe: qe_io.c: use of_property_read_u32() in par_io_init()
soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fsl
soc/fsl/qe/qe.h: update include path for cpm.h
serial: ucc_uart: explicitly include soc/fsl/cpm.h
serial: ucc_uart: replace ppc-specific IO accessors
serial: ucc_uart: factor out soft_uart initialization
serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32
serial: ucc_uart: use of_property_read_u32() in ucc_uart_probe()
serial: ucc_uart: access __be32 field using be32_to_cpu
net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32
net/wan: make FSL_UCC_HDLC explicitly depend on PPC32
soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE

arch/powerpc/include/asm/cpm.h | 172 +-------
arch/powerpc/platforms/83xx/km83xx.c | 3 +-
arch/powerpc/platforms/83xx/misc.c | 23 --
arch/powerpc/platforms/83xx/mpc832x_mds.c | 3 +-
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 3 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c | 3 +-
arch/powerpc/platforms/83xx/mpc836x_rdk.c | 3 +-
arch/powerpc/platforms/83xx/mpc83xx.h | 7 -
arch/powerpc/platforms/85xx/common.c | 23 --
arch/powerpc/platforms/85xx/corenet_generic.c | 12 -
arch/powerpc/platforms/85xx/mpc85xx.h | 2 -
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 28 --
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 18 -
arch/powerpc/platforms/85xx/twr_p102x.c | 16 -
drivers/net/ethernet/freescale/Kconfig | 2 +-
drivers/net/wan/Kconfig | 2 +-
drivers/net/wan/fsl_ucc_hdlc.c | 4 +-
drivers/soc/fsl/qe/Kconfig | 2 +-
drivers/soc/fsl/qe/gpio.c | 34 +-
drivers/soc/fsl/qe/qe.c | 95 ++---
drivers/soc/fsl/qe/qe_ic.c | 285 ++++++-------
drivers/soc/fsl/qe/qe_ic.h | 99 -----
drivers/soc/fsl/qe/qe_io.c | 70 ++--
drivers/soc/fsl/qe/qe_tdm.c | 8 +-
drivers/soc/fsl/qe/ucc.c | 26 +-
drivers/soc/fsl/qe/ucc_fast.c | 71 ++--
drivers/soc/fsl/qe/ucc_slow.c | 38 +-
drivers/soc/fsl/qe/usb.c | 2 +-
drivers/tty/serial/ucc_uart.c | 383 +++++++++---------
include/soc/fsl/cpm.h | 171 ++++++++
include/soc/fsl/qe/qe.h | 42 +-
include/soc/fsl/qe/qe_ic.h | 135 ------
32 files changed, 701 insertions(+), 1084 deletions(-)
delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
create mode 100644 include/soc/fsl/cpm.h
delete mode 100644 include/soc/fsl/qe/qe_ic.h

--
2.23.0

2019-11-01 12:44:12

by Rasmus Villemoes

Subject: [PATCH v3 02/36] soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs

The actual io accessors (e.g. in_be32) implicitly add a volatile
qualifier to their address argument. Remove volatile from the struct
definition and the qe_ic_(read/write) helpers, in preparation for
switching from the ppc-specific io accessors to generic ones.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe_ic.c | 4 ++--
drivers/soc/fsl/qe/qe_ic.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 9bac546998d3..791adcd121d1 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -171,12 +171,12 @@ static struct qe_ic_info qe_ic_info[] = {
},
};

-static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
+static inline u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)
{
return in_be32(base + (reg >> 2));
}

-static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
+static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg,
u32 value)
{
out_be32(base + (reg >> 2), value);
diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h
index 08c695672a03..9420378d9b6b 100644
--- a/drivers/soc/fsl/qe/qe_ic.h
+++ b/drivers/soc/fsl/qe/qe_ic.h
@@ -72,7 +72,7 @@

struct qe_ic {
/* Control registers offset */
- volatile u32 __iomem *regs;
+ u32 __iomem *regs;

/* The remapper for this QEIC */
struct irq_domain *irqhost;
--
2.23.0

2019-11-01 12:44:17

by Rasmus Villemoes

Subject: [PATCH v3 01/36] soc: fsl: qe: remove space-before-tab

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 417df7e19281..2a0e6e642776 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -378,8 +378,8 @@ static int qe_sdma_init(void)
}

out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
- out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
- (0x1 << QE_SDMR_CEN_SHIFT)));
+ out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
+ (0x1 << QE_SDMR_CEN_SHIFT)));

return 0;
}
--
2.23.0

2019-11-01 12:44:21

by Rasmus Villemoes

Subject: [PATCH v3 06/36] soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic

In preparation for allowing QE to be built for architectures other
than ppc, use the generic readx_poll_timeout_atomic() helper from
iopoll.h rather than the ppc-only spin_event_timeout().

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 456bd7416876..85737e6f5b62 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -22,6 +22,7 @@
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/ioport.h>
+#include <linux/iopoll.h>
#include <linux/crc32.h>
#include <linux/mod_devicetable.h>
#include <linux/of_platform.h>
@@ -108,7 +109,8 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
{
unsigned long flags;
u8 mcn_shift = 0, dev_shift = 0;
- u32 ret;
+ u32 val;
+ int ret;

spin_lock_irqsave(&qe_lock, flags);
if (cmd == QE_RESET) {
@@ -135,13 +137,12 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
}

/* wait for the QE_CR_FLG to clear */
- ret = spin_event_timeout((qe_ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
- 100, 0);
- /* On timeout (e.g. failure), the expression will be false (ret == 0),
- otherwise it will be true (ret == 1). */
+ ret = readx_poll_timeout_atomic(qe_ioread32be, &qe_immr->cp.cecr, val,
+ (val & QE_CR_FLG) == 0, 0, 100);
+ /* On timeout, ret is -ETIMEDOUT, otherwise it will be 0. */
spin_unlock_irqrestore(&qe_lock, flags);

- return ret == 1;
+ return ret == 0;
}
EXPORT_SYMBOL(qe_issue_cmd);

--
2.23.0

2019-11-01 12:44:26

by Rasmus Villemoes

Subject: [PATCH v3 11/36] soc: fsl: qe: use qe_ic_cascade_{low,high}_mpic also on 83xx

The *_ipic and *_mpic handlers are almost identical - the only
difference is that the latter end with an unconditional
chip->irq_eoi() call. Since IPIC does not have ->irq_eoi, we can
reduce some code duplication by calling irq_eoi conditionally.

This is similar to what is already done in mpc8xxx_gpio_irq_cascade().

This leaves the functions slightly misnamed, but that will be fixed in
a subsequent patch.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
arch/powerpc/platforms/83xx/misc.c | 2 +-
include/soc/fsl/qe/qe_ic.h | 24 ++++--------------------
2 files changed, 5 insertions(+), 21 deletions(-)

diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c
index f46d7bf3b140..779791c0570f 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -100,7 +100,7 @@ void __init mpc83xx_qe_init_IRQ(void)
if (!np)
return;
}
- qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);
of_node_put(np);
}

diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index 714a9b890d8d..bfaa233d8328 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -74,24 +74,6 @@ void qe_ic_set_highest_priority(unsigned int virq, int high);
int qe_ic_set_priority(unsigned int virq, unsigned int priority);
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);

-static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-}
-
-static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-}
-
static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
{
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
@@ -101,7 +83,8 @@ static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
if (cascade_irq != NO_IRQ)
generic_handle_irq(cascade_irq);

- chip->irq_eoi(&desc->irq_data);
+ if (chip->irq_eoi)
+ chip->irq_eoi(&desc->irq_data);
}

static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
@@ -113,7 +96,8 @@ static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
if (cascade_irq != NO_IRQ)
generic_handle_irq(cascade_irq);

- chip->irq_eoi(&desc->irq_data);
+ if (chip->irq_eoi)
+ chip->irq_eoi(&desc->irq_data);
}

static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
--
2.23.0

2019-11-01 12:44:38

by Rasmus Villemoes

Subject: [PATCH v3 19/36] soc: fsl: qe: make qe_ic_get_{low,high}_irq static

These are only called from within qe_ic.c, so make them static.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe_ic.c | 4 ++--
include/soc/fsl/qe/qe_ic.h | 10 ----------
2 files changed, 2 insertions(+), 12 deletions(-)

diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 8f74bc6efd5c..23b457e884d8 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -283,7 +283,7 @@ static const struct irq_domain_ops qe_ic_host_ops = {
};

/* Return an interrupt vector or 0 if no interrupt is pending. */
-unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
+static unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
{
int irq;

@@ -299,7 +299,7 @@ unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
}

/* Return an interrupt vector or 0 if no interrupt is pending. */
-unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
+static unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
{
int irq;

diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index d47eb231519e..70bb5a0f6535 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -53,14 +53,4 @@ enum qe_ic_grp_id {
QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
};

-#ifdef CONFIG_QUICC_ENGINE
-unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
-unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
-#else
-static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
-{ return 0; }
-static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
-{ return 0; }
-#endif /* CONFIG_QUICC_ENGINE */
-
#endif /* _ASM_POWERPC_QE_IC_H */
--
2.23.0

2019-11-01 12:44:56

by Rasmus Villemoes

Subject: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly depend on PPC32

Currently, FSL_UCC_HDLC depends on QUICC_ENGINE, which in turn depends
on PPC32. As preparation for removing the latter and thus allowing the
core QE code to be built for other architectures, make FSL_UCC_HDLC
explicitly depend on PPC32.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/net/wan/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
index dd1a147f2971..78785d790bcc 100644
--- a/drivers/net/wan/Kconfig
+++ b/drivers/net/wan/Kconfig
@@ -270,7 +270,7 @@ config FARSYNC
config FSL_UCC_HDLC
tristate "Freescale QUICC Engine HDLC support"
depends on HDLC
- depends on QUICC_ENGINE
+ depends on QUICC_ENGINE && PPC32
help
Driver for Freescale QUICC Engine HDLC controller. The driver
supports HDLC in NMSI and TDM mode.
--
2.23.0

2019-11-01 12:45:05

by Rasmus Villemoes

Subject: [PATCH v3 34/36] net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32

Currently, QUICC_ENGINE depends on PPC32, so this in itself does not
change anything. In order to allow removing the PPC32 dependency from
QUICC_ENGINE and avoid allmodconfig build failures, add this explicit
dependency.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/net/ethernet/freescale/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/freescale/Kconfig b/drivers/net/ethernet/freescale/Kconfig
index 6a7e8993119f..2bd7ace0a953 100644
--- a/drivers/net/ethernet/freescale/Kconfig
+++ b/drivers/net/ethernet/freescale/Kconfig
@@ -74,7 +74,7 @@ config FSL_XGMAC_MDIO

config UCC_GETH
tristate "Freescale QE Gigabit Ethernet"
- depends on QUICC_ENGINE
+ depends on QUICC_ENGINE && PPC32
select FSL_PQ_MDIO
select PHYLIB
---help---
--
2.23.0

2019-11-01 12:45:06

by Rasmus Villemoes

Subject: [PATCH v3 31/36] serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32

The Soft UART hack is only needed for some PPC-based SOCs. To allow
building this driver for non-PPC, guard soft_uart_init() and its
helpers by CONFIG_PPC32, and use a no-op soft_uart_init() otherwise.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/tty/serial/ucc_uart.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index f286e91714cb..313697842e24 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -33,7 +33,10 @@

#include <linux/firmware.h>
#include <soc/fsl/cpm.h>
-#include <asm/reg.h>
+
+#ifdef CONFIG_PPC32
+#include <asm/reg.h> /* mfspr, SPRN_SVR */
+#endif

/*
* The GUMR flag for Soft UART. This would normally be defined in qe.h,
@@ -1096,6 +1099,8 @@ static const struct uart_ops qe_uart_pops = {
.verify_port = qe_uart_verify_port,
};

+
+#ifdef CONFIG_PPC32
/*
* Obtain the SOC model number and revision level
*
@@ -1238,6 +1243,16 @@ static int soft_uart_init(struct platform_device *ofdev)
return 0;
}

+#else /* !CONFIG_PPC32 */
+
+static int soft_uart_init(struct platform_device *ofdev)
+{
+ return 0;
+}
+
+#endif
+
+
static int ucc_uart_probe(struct platform_device *ofdev)
{
struct device_node *np = ofdev->dev.of_node;
--
2.23.0

2019-11-01 12:45:08

by Rasmus Villemoes

Subject: [PATCH v3 33/36] serial: ucc_uart: access __be32 field using be32_to_cpu

The buf member of struct qe_bd is a __be32, so to make this work on
little-endian hosts, use be32_to_cpu when reading it.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/tty/serial/ucc_uart.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index f5ea84928a3b..a5330582b610 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -343,7 +343,7 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
/* Pick next descriptor and fill from buffer */
bdp = qe_port->tx_cur;

- p = qe2cpu_addr(bdp->buf, qe_port);
+ p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);

*p++ = port->x_char;
qe_iowrite16be(1, &bdp->length);
@@ -371,7 +371,7 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
while (!(qe_ioread16be(&bdp->status) & BD_SC_READY) &&
(xmit->tail != xmit->head)) {
count = 0;
- p = qe2cpu_addr(bdp->buf, qe_port);
+ p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
while (count < qe_port->tx_fifosize) {
*p++ = xmit->buf[xmit->tail];
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
@@ -491,7 +491,7 @@ static void qe_uart_int_rx(struct uart_qe_port *qe_port)
}

/* get pointer */
- cp = qe2cpu_addr(bdp->buf, qe_port);
+ cp = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);

/* loop through the buffer */
while (i-- > 0) {
--
2.23.0

2019-11-01 12:45:14

by Rasmus Villemoes

Subject: [PATCH v3 30/36] serial: ucc_uart: factor out soft_uart initialization

The "soft uart" mechanism is a workaround for a silicon bug which (as
far as I know) only affects some PPC-based SOCs.

The code that determines which microcode blob to request relies on
some powerpc-specific bits (e.g. the mfspr(SPRN_SVR) and hence also
the asm/reg.h header). This makes it a little awkward to allow this
driver to be built for non-PPC based SOCs with a QE, even if they are
not affected by that silicon bug and thus don't need any of the Soft
UART logic.

There's no way around guarding those bits with some ifdeffery, so to
keep that isolated, factor out the
do-we-need-soft-uart-and-if-so-handle-the-firmware to a separate
function, which we can then easily stub out for non-PPC.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/tty/serial/ucc_uart.c | 110 ++++++++++++++++++----------------
1 file changed, 58 insertions(+), 52 deletions(-)

diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index 8a378ee5d34f..f286e91714cb 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -1183,70 +1183,76 @@ static void uart_firmware_cont(const struct firmware *fw, void *context)
release_firmware(fw);
}

-static int ucc_uart_probe(struct platform_device *ofdev)
+static int soft_uart_init(struct platform_device *ofdev)
{
struct device_node *np = ofdev->dev.of_node;
- const unsigned int *iprop; /* Integer OF properties */
- const char *sprop; /* String OF properties */
- struct uart_qe_port *qe_port = NULL;
- struct resource res;
+ struct qe_firmware_info *qe_fw_info;
int ret;

- /*
- * Determine if we need Soft-UART mode
- */
if (of_find_property(np, "soft-uart", NULL)) {
dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
soft_uart = 1;
+ } else {
+ return 0;
}

- /*
- * If we are using Soft-UART, determine if we need to upload the
- * firmware, too.
- */
- if (soft_uart) {
- struct qe_firmware_info *qe_fw_info;
-
- qe_fw_info = qe_get_firmware_info();
-
- /* Check if the firmware has been uploaded. */
- if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
- firmware_loaded = 1;
- } else {
- char filename[32];
- unsigned int soc;
- unsigned int rev_h;
- unsigned int rev_l;
-
- soc = soc_info(&rev_h, &rev_l);
- if (!soc) {
- dev_err(&ofdev->dev, "unknown CPU model\n");
- return -ENXIO;
- }
- sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
- soc, rev_h, rev_l);
-
- dev_info(&ofdev->dev, "waiting for firmware %s\n",
- filename);
+ qe_fw_info = qe_get_firmware_info();

- /*
- * We call request_firmware_nowait instead of
- * request_firmware so that the driver can load and
- * initialize the ports without holding up the rest of
- * the kernel. If hotplug support is enabled in the
- * kernel, then we use it.
- */
- ret = request_firmware_nowait(THIS_MODULE,
- FW_ACTION_HOTPLUG, filename, &ofdev->dev,
- GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
- if (ret) {
- dev_err(&ofdev->dev,
- "could not load firmware %s\n",
- filename);
- return ret;
- }
+ /* Check if the firmware has been uploaded. */
+ if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
+ firmware_loaded = 1;
+ } else {
+ char filename[32];
+ unsigned int soc;
+ unsigned int rev_h;
+ unsigned int rev_l;
+
+ soc = soc_info(&rev_h, &rev_l);
+ if (!soc) {
+ dev_err(&ofdev->dev, "unknown CPU model\n");
+ return -ENXIO;
+ }
+ sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
+ soc, rev_h, rev_l);
+
+ dev_info(&ofdev->dev, "waiting for firmware %s\n",
+ filename);
+
+ /*
+ * We call request_firmware_nowait instead of
+ * request_firmware so that the driver can load and
+ * initialize the ports without holding up the rest of
+ * the kernel. If hotplug support is enabled in the
+ * kernel, then we use it.
+ */
+ ret = request_firmware_nowait(THIS_MODULE,
+ FW_ACTION_HOTPLUG, filename, &ofdev->dev,
+ GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
+ if (ret) {
+ dev_err(&ofdev->dev,
+ "could not load firmware %s\n",
+ filename);
+ return ret;
}
}
+ return 0;
+}
+
+static int ucc_uart_probe(struct platform_device *ofdev)
+{
+ struct device_node *np = ofdev->dev.of_node;
+ const unsigned int *iprop; /* Integer OF properties */
+ const char *sprop; /* String OF properties */
+ struct uart_qe_port *qe_port = NULL;
+ struct resource res;
+ int ret;
+
+ /*
+ * Determine if we need Soft-UART mode
+ */
+ ret = soft_uart_init(ofdev);
+ if (ret)
+ return ret;

qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
if (!qe_port) {
--
2.23.0

2019-11-01 12:45:17

by Rasmus Villemoes

Subject: [PATCH v3 29/36] serial: ucc_uart: replace ppc-specific IO accessors

Some ARM-based SOCs (e.g. LS1021A) also have a QUICC engine. As
preparation for allowing this driver to build on ARM, replace the
ppc-specific in_be16() etc. by the qe_io* helpers. Done via
coccinelle.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/tty/serial/ucc_uart.c | 210 +++++++++++++++++-----------------
1 file changed, 102 insertions(+), 108 deletions(-)

diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index 7e802616cba8..8a378ee5d34f 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -258,11 +258,11 @@ static unsigned int qe_uart_tx_empty(struct uart_port *port)
struct qe_bd *bdp = qe_port->tx_bd_base;

while (1) {
- if (in_be16(&bdp->status) & BD_SC_READY)
+ if (qe_ioread16be(&bdp->status) & BD_SC_READY)
/* This BD is not done, so return "not done" */
return 0;

- if (in_be16(&bdp->status) & BD_SC_WRAP)
+ if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
/*
* This BD is done and it's the last one, so return
* "done"
@@ -308,7 +308,7 @@ static void qe_uart_stop_tx(struct uart_port *port)
struct uart_qe_port *qe_port =
container_of(port, struct uart_qe_port, port);

- clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
+ qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
}

/*
@@ -343,10 +343,10 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
p = qe2cpu_addr(bdp->buf, qe_port);

*p++ = port->x_char;
- out_be16(&bdp->length, 1);
- setbits16(&bdp->status, BD_SC_READY);
+ qe_iowrite16be(1, &bdp->length);
+ qe_setbits_be16(&bdp->status, BD_SC_READY);
/* Get next BD. */
- if (in_be16(&bdp->status) & BD_SC_WRAP)
+ if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
bdp = qe_port->tx_bd_base;
else
bdp++;
@@ -365,7 +365,7 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
/* Pick next descriptor and fill from buffer */
bdp = qe_port->tx_cur;

- while (!(in_be16(&bdp->status) & BD_SC_READY) &&
+ while (!(qe_ioread16be(&bdp->status) & BD_SC_READY) &&
(xmit->tail != xmit->head)) {
count = 0;
p = qe2cpu_addr(bdp->buf, qe_port);
@@ -378,11 +378,11 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
break;
}

- out_be16(&bdp->length, count);
- setbits16(&bdp->status, BD_SC_READY);
+ qe_iowrite16be(count, &bdp->length);
+ qe_setbits_be16(&bdp->status, BD_SC_READY);

/* Get next BD. */
- if (in_be16(&bdp->status) & BD_SC_WRAP)
+ if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
bdp = qe_port->tx_bd_base;
else
bdp++;
@@ -415,12 +415,12 @@ static void qe_uart_start_tx(struct uart_port *port)
container_of(port, struct uart_qe_port, port);

/* If we currently are transmitting, then just return */
- if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
+ if (qe_ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
return;

/* Otherwise, pump the port and start transmission */
if (qe_uart_tx_pump(qe_port))
- setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
+ qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
}

/*
@@ -431,7 +431,7 @@ static void qe_uart_stop_rx(struct uart_port *port)
struct uart_qe_port *qe_port =
container_of(port, struct uart_qe_port, port);

- clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
+ qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
}

/* Start or stop sending break signal
@@ -470,14 +470,14 @@ static void qe_uart_int_rx(struct uart_qe_port *qe_port)
*/
bdp = qe_port->rx_cur;
while (1) {
- status = in_be16(&bdp->status);
+ status = qe_ioread16be(&bdp->status);

/* If this one is empty, then we assume we've read them all */
if (status & BD_SC_EMPTY)
break;

/* get number of characters, and check space in RX buffer */
- i = in_be16(&bdp->length);
+ i = qe_ioread16be(&bdp->length);

/* If we don't have enough room in RX buffer for the entire BD,
* then we try later, which will be the next RX interrupt.
@@ -508,9 +508,10 @@ static void qe_uart_int_rx(struct uart_qe_port *qe_port)
}

/* This BD is ready to be used again. Clear status. get next */
- clrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR |
- BD_SC_OV | BD_SC_ID, BD_SC_EMPTY);
- if (in_be16(&bdp->status) & BD_SC_WRAP)
+ qe_clrsetbits_be16(&bdp->status,
+ BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID,
+ BD_SC_EMPTY);
+ if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
bdp = qe_port->rx_bd_base;
else
bdp++;
@@ -569,8 +570,8 @@ static irqreturn_t qe_uart_int(int irq, void *data)
u16 events;

/* Clear the interrupts */
- events = in_be16(&uccp->ucce);
- out_be16(&uccp->ucce, events);
+ events = qe_ioread16be(&uccp->ucce);
+ qe_iowrite16be(events, &uccp->ucce);

if (events & UCC_UART_UCCE_BRKE)
uart_handle_break(&qe_port->port);
@@ -601,17 +602,17 @@ static void qe_uart_initbd(struct uart_qe_port *qe_port)
bdp = qe_port->rx_bd_base;
qe_port->rx_cur = qe_port->rx_bd_base;
for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
- out_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT);
- out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
- out_be16(&bdp->length, 0);
+ qe_iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
+ qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+ qe_iowrite16be(0, &bdp->length);
bd_virt += qe_port->rx_fifosize;
bdp++;
}

/* */
- out_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
- out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
- out_be16(&bdp->length, 0);
+ qe_iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
+ qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+ qe_iowrite16be(0, &bdp->length);

/* Set the physical address of the host memory
* buffers in the buffer descriptors, and the
@@ -622,21 +623,21 @@ static void qe_uart_initbd(struct uart_qe_port *qe_port)
qe_port->tx_cur = qe_port->tx_bd_base;
bdp = qe_port->tx_bd_base;
for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
- out_be16(&bdp->status, BD_SC_INTRPT);
- out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
- out_be16(&bdp->length, 0);
+ qe_iowrite16be(BD_SC_INTRPT, &bdp->status);
+ qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+ qe_iowrite16be(0, &bdp->length);
bd_virt += qe_port->tx_fifosize;
bdp++;
}

/* Loopback requires the preamble bit to be set on the first TX BD */
#ifdef LOOPBACK
- setbits16(&qe_port->tx_cur->status, BD_SC_P);
+ qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);
#endif

- out_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT);
- out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
- out_be16(&bdp->length, 0);
+ qe_iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status);
+ qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+ qe_iowrite16be(0, &bdp->length);
}

/*
@@ -658,78 +659,74 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);

/* Program the UCC UART parameter RAM */
- out_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
- out_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
- out_be16(&uccup->common.mrblr, qe_port->rx_fifosize);
- out_be16(&uccup->maxidl, 0x10);
- out_be16(&uccup->brkcr, 1);
- out_be16(&uccup->parec, 0);
- out_be16(&uccup->frmec, 0);
- out_be16(&uccup->nosec, 0);
- out_be16(&uccup->brkec, 0);
- out_be16(&uccup->uaddr[0], 0);
- out_be16(&uccup->uaddr[1], 0);
- out_be16(&uccup->toseq, 0);
+ qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr);
+ qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr);
+ qe_iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
+ qe_iowrite16be(0x10, &uccup->maxidl);
+ qe_iowrite16be(1, &uccup->brkcr);
+ qe_iowrite16be(0, &uccup->parec);
+ qe_iowrite16be(0, &uccup->frmec);
+ qe_iowrite16be(0, &uccup->nosec);
+ qe_iowrite16be(0, &uccup->brkec);
+ qe_iowrite16be(0, &uccup->uaddr[0]);
+ qe_iowrite16be(0, &uccup->uaddr[1]);
+ qe_iowrite16be(0, &uccup->toseq);
for (i = 0; i < 8; i++)
- out_be16(&uccup->cchars[i], 0xC000);
- out_be16(&uccup->rccm, 0xc0ff);
+ qe_iowrite16be(0xC000, &uccup->cchars[i]);
+ qe_iowrite16be(0xc0ff, &uccup->rccm);

/* Configure the GUMR registers for UART */
if (soft_uart) {
/* Soft-UART requires a 1X multiplier for TX */
- clrsetbits_be32(&uccp->gumr_l,
- UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
- UCC_SLOW_GUMR_L_RDCR_MASK,
- UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |
- UCC_SLOW_GUMR_L_RDCR_16);
-
- clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
- UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
+ qe_clrsetbits_be32(&uccp->gumr_l,
+ UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
+ UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | UCC_SLOW_GUMR_L_RDCR_16);
+
+ qe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
+ UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
} else {
- clrsetbits_be32(&uccp->gumr_l,
- UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
- UCC_SLOW_GUMR_L_RDCR_MASK,
- UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |
- UCC_SLOW_GUMR_L_RDCR_16);
-
- clrsetbits_be32(&uccp->gumr_h,
- UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
- UCC_SLOW_GUMR_H_RFW);
+ qe_clrsetbits_be32(&uccp->gumr_l,
+ UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
+ UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
+
+ qe_clrsetbits_be32(&uccp->gumr_h,
+ UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
+ UCC_SLOW_GUMR_H_RFW);
}

#ifdef LOOPBACK
- clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
- UCC_SLOW_GUMR_L_DIAG_LOOP);
- clrsetbits_be32(&uccp->gumr_h,
- UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
- UCC_SLOW_GUMR_H_CDS);
+ qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
+ UCC_SLOW_GUMR_L_DIAG_LOOP);
+ qe_clrsetbits_be32(&uccp->gumr_h,
+ UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
+ UCC_SLOW_GUMR_H_CDS);
#endif

/* Disable rx interrupts and clear all pending events. */
- out_be16(&uccp->uccm, 0);
- out_be16(&uccp->ucce, 0xffff);
- out_be16(&uccp->udsr, 0x7e7e);
+ qe_iowrite16be(0, &uccp->uccm);
+ qe_iowrite16be(0xffff, &uccp->ucce);
+ qe_iowrite16be(0x7e7e, &uccp->udsr);

/* Initialize UPSMR */
- out_be16(&uccp->upsmr, 0);
+ qe_iowrite16be(0, &uccp->upsmr);

if (soft_uart) {
- out_be16(&uccup->supsmr, 0x30);
- out_be16(&uccup->res92, 0);
- out_be32(&uccup->rx_state, 0);
- out_be32(&uccup->rx_cnt, 0);
- out_8(&uccup->rx_bitmark, 0);
- out_8(&uccup->rx_length, 10);
- out_be32(&uccup->dump_ptr, 0x4000);
- out_8(&uccup->rx_temp_dlst_qe, 0);
- out_be32(&uccup->rx_frame_rem, 0);
- out_8(&uccup->rx_frame_rem_size, 0);
+ qe_iowrite16be(0x30, &uccup->supsmr);
+ qe_iowrite16be(0, &uccup->res92);
+ qe_iowrite32be(0, &uccup->rx_state);
+ qe_iowrite32be(0, &uccup->rx_cnt);
+ qe_iowrite8(0, &uccup->rx_bitmark);
+ qe_iowrite8(10, &uccup->rx_length);
+ qe_iowrite32be(0x4000, &uccup->dump_ptr);
+ qe_iowrite8(0, &uccup->rx_temp_dlst_qe);
+ qe_iowrite32be(0, &uccup->rx_frame_rem);
+ qe_iowrite8(0, &uccup->rx_frame_rem_size);
/* Soft-UART requires TX to be 1X */
- out_8(&uccup->tx_mode,
- UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1);
- out_be16(&uccup->tx_state, 0);
- out_8(&uccup->resD4, 0);
- out_be16(&uccup->resD5, 0);
+ qe_iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1,
+ &uccup->tx_mode);
+ qe_iowrite16be(0, &uccup->tx_state);
+ qe_iowrite8(0, &uccup->resD4);
+ qe_iowrite16be(0, &uccup->resD5);

/* Set UART mode.
* Enable receive and transmit.
@@ -743,22 +740,19 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
* ...
* 6.Receiver must use 16x over sampling
*/
- clrsetbits_be32(&uccp->gumr_l,
- UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
- UCC_SLOW_GUMR_L_RDCR_MASK,
- UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 |
- UCC_SLOW_GUMR_L_RDCR_16);
+ qe_clrsetbits_be32(&uccp->gumr_l,
+ UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
+ UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);

- clrsetbits_be32(&uccp->gumr_h,
- UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
- UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX |
- UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
+ qe_clrsetbits_be32(&uccp->gumr_h,
+ UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
+ UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);

#ifdef LOOPBACK
- clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
- UCC_SLOW_GUMR_L_DIAG_LOOP);
- clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP |
- UCC_SLOW_GUMR_H_CDS);
+ qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
+ UCC_SLOW_GUMR_L_DIAG_LOOP);
+ qe_clrbits_be32(&uccp->gumr_h,
+ UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_CDS);
#endif

cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
@@ -801,7 +795,7 @@ static int qe_uart_startup(struct uart_port *port)
}

/* Startup rx-int */
- setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
+ qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);

return 0;
@@ -837,7 +831,7 @@ static void qe_uart_shutdown(struct uart_port *port)

/* Stop uarts */
ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
- clrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
+ qe_clrbits_be16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);

/* Shut them really down and reinit buffer descriptors */
ucc_slow_graceful_stop_tx(qe_port->us_private);
@@ -857,9 +851,9 @@ static void qe_uart_set_termios(struct uart_port *port,
struct ucc_slow __iomem *uccp = qe_port->uccp;
unsigned int baud;
unsigned long flags;
- u16 upsmr = in_be16(&uccp->upsmr);
+ u16 upsmr = qe_ioread16be(&uccp->upsmr);
struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
- u16 supsmr = in_be16(&uccup->supsmr);
+ u16 supsmr = qe_ioread16be(&uccup->supsmr);
u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */

/* Character length programmed into the mode register is the
@@ -957,10 +951,10 @@ static void qe_uart_set_termios(struct uart_port *port,
/* Update the per-port timeout. */
uart_update_timeout(port, termios->c_cflag, baud);

- out_be16(&uccp->upsmr, upsmr);
+ qe_iowrite16be(upsmr, &uccp->upsmr);
if (soft_uart) {
- out_be16(&uccup->supsmr, supsmr);
- out_8(&uccup->rx_length, char_length);
+ qe_iowrite16be(supsmr, &uccup->supsmr);
+ qe_iowrite8(char_length, &uccup->rx_length);

/* Soft-UART requires a 1X multiplier for TX */
qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
--
2.23.0

2019-11-01 12:45:19

by Rasmus Villemoes

Subject: [PATCH v3 24/36] soc: fsl: qe: qe_io.c: access device tree property using be32_to_cpu

We need to apply be32_to_cpu to make this work correctly on
little-endian hosts.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe_io.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c
index 99aeb01586bd..61dd8eb8c0fe 100644
--- a/drivers/soc/fsl/qe/qe_io.c
+++ b/drivers/soc/fsl/qe/qe_io.c
@@ -142,7 +142,7 @@ int par_io_of_config(struct device_node *np)
{
struct device_node *pio;
int pio_map_len;
- const unsigned int *pio_map;
+ const __be32 *pio_map;

if (par_io == NULL) {
printk(KERN_ERR "par_io not initialized\n");
@@ -167,9 +167,15 @@ int par_io_of_config(struct device_node *np)
}

while (pio_map_len > 0) {
- par_io_config_pin((u8) pio_map[0], (u8) pio_map[1],
- (int) pio_map[2], (int) pio_map[3],
- (int) pio_map[4], (int) pio_map[5]);
+ u8 port = be32_to_cpu(pio_map[0]);
+ u8 pin = be32_to_cpu(pio_map[1]);
+ int dir = be32_to_cpu(pio_map[2]);
+ int open_drain = be32_to_cpu(pio_map[3]);
+ int assignment = be32_to_cpu(pio_map[4]);
+ int has_irq = be32_to_cpu(pio_map[5]);
+
+ par_io_config_pin(port, pin, dir, open_drain,
+ assignment, has_irq);
pio_map += 6;
pio_map_len -= 6;
}
--
2.23.0

2019-11-01 12:45:24

by Rasmus Villemoes

Subject: [PATCH v3 26/36] soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fsl

Some drivers, e.g. ucc_uart, need definitions from cpm.h. In order to
allow building those drivers for non-ppc based SOCs, move the header
to include/soc/fsl. For now, leave a trivial wrapper at the old
location so drivers can be updated one by one.

Signed-off-by: Rasmus Villemoes <[email protected]>
---
arch/powerpc/include/asm/cpm.h | 172 +--------------------------------
include/soc/fsl/cpm.h | 171 ++++++++++++++++++++++++++++++++
2 files changed, 172 insertions(+), 171 deletions(-)
create mode 100644 include/soc/fsl/cpm.h

diff --git a/arch/powerpc/include/asm/cpm.h b/arch/powerpc/include/asm/cpm.h
index 4c24ea8209bb..ce483b0f8a4d 100644
--- a/arch/powerpc/include/asm/cpm.h
+++ b/arch/powerpc/include/asm/cpm.h
@@ -1,171 +1 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __CPM_H
-#define __CPM_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/of.h>
-#include <soc/fsl/qe/qe.h>
-
-/*
- * SPI Parameter RAM common to QE and CPM.
- */
-struct spi_pram {
- __be16 rbase; /* Rx Buffer descriptor base address */
- __be16 tbase; /* Tx Buffer descriptor base address */
- u8 rfcr; /* Rx function code */
- u8 tfcr; /* Tx function code */
- __be16 mrblr; /* Max receive buffer length */
- __be32 rstate; /* Internal */
- __be32 rdp; /* Internal */
- __be16 rbptr; /* Internal */
- __be16 rbc; /* Internal */
- __be32 rxtmp; /* Internal */
- __be32 tstate; /* Internal */
- __be32 tdp; /* Internal */
- __be16 tbptr; /* Internal */
- __be16 tbc; /* Internal */
- __be32 txtmp; /* Internal */
- __be32 res; /* Tx temp. */
- __be16 rpbase; /* Relocation pointer (CPM1 only) */
- __be16 res1; /* Reserved */
-};
-
-/*
- * USB Controller pram common to QE and CPM.
- */
-struct usb_ctlr {
- u8 usb_usmod;
- u8 usb_usadr;
- u8 usb_uscom;
- u8 res1[1];
- __be16 usb_usep[4];
- u8 res2[4];
- __be16 usb_usber;
- u8 res3[2];
- __be16 usb_usbmr;
- u8 res4[1];
- u8 usb_usbs;
- /* Fields down below are QE-only */
- __be16 usb_ussft;
- u8 res5[2];
- __be16 usb_usfrn;
- u8 res6[0x22];
-} __attribute__ ((packed));
-
-/*
- * Function code bits, usually generic to devices.
- */
-#ifdef CONFIG_CPM1
-#define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */
-#define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */
-#define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
-#define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
-#else
-#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
-#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
-#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
-#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
-#endif
-#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
-
-/* Opcodes common to CPM1 and CPM2
-*/
-#define CPM_CR_INIT_TRX ((ushort)0x0000)
-#define CPM_CR_INIT_RX ((ushort)0x0001)
-#define CPM_CR_INIT_TX ((ushort)0x0002)
-#define CPM_CR_HUNT_MODE ((ushort)0x0003)
-#define CPM_CR_STOP_TX ((ushort)0x0004)
-#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
-#define CPM_CR_RESTART_TX ((ushort)0x0006)
-#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
-#define CPM_CR_SET_GADDR ((ushort)0x0008)
-#define CPM_CR_SET_TIMER ((ushort)0x0008)
-#define CPM_CR_STOP_IDMA ((ushort)0x000b)
-
-/* Buffer descriptors used by many of the CPM protocols. */
-typedef struct cpm_buf_desc {
- ushort cbd_sc; /* Status and Control */
- ushort cbd_datlen; /* Data length in buffer */
- uint cbd_bufaddr; /* Buffer address in host memory */
-} cbd_t;
-
-/* Buffer descriptor control/status used by serial
- */
-
-#define BD_SC_EMPTY (0x8000) /* Receive is empty */
-#define BD_SC_READY (0x8000) /* Transmit is ready */
-#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
-#define BD_SC_INTRPT (0x1000) /* Interrupt on change */
-#define BD_SC_LAST (0x0800) /* Last buffer in frame */
-#define BD_SC_TC (0x0400) /* Transmit CRC */
-#define BD_SC_CM (0x0200) /* Continuous mode */
-#define BD_SC_ID (0x0100) /* Rec'd too many idles */
-#define BD_SC_P (0x0100) /* xmt preamble */
-#define BD_SC_BR (0x0020) /* Break received */
-#define BD_SC_FR (0x0010) /* Framing error */
-#define BD_SC_PR (0x0008) /* Parity error */
-#define BD_SC_NAK (0x0004) /* NAK - did not respond */
-#define BD_SC_OV (0x0002) /* Overrun */
-#define BD_SC_UN (0x0002) /* Underrun */
-#define BD_SC_CD (0x0001) /* */
-#define BD_SC_CL (0x0001) /* Collision */
-
-/* Buffer descriptor control/status used by Ethernet receive.
- * Common to SCC and FCC.
- */
-#define BD_ENET_RX_EMPTY (0x8000)
-#define BD_ENET_RX_WRAP (0x2000)
-#define BD_ENET_RX_INTR (0x1000)
-#define BD_ENET_RX_LAST (0x0800)
-#define BD_ENET_RX_FIRST (0x0400)
-#define BD_ENET_RX_MISS (0x0100)
-#define BD_ENET_RX_BC (0x0080) /* FCC Only */
-#define BD_ENET_RX_MC (0x0040) /* FCC Only */
-#define BD_ENET_RX_LG (0x0020)
-#define BD_ENET_RX_NO (0x0010)
-#define BD_ENET_RX_SH (0x0008)
-#define BD_ENET_RX_CR (0x0004)
-#define BD_ENET_RX_OV (0x0002)
-#define BD_ENET_RX_CL (0x0001)
-#define BD_ENET_RX_STATS (0x01ff) /* All status bits */
-
-/* Buffer descriptor control/status used by Ethernet transmit.
- * Common to SCC and FCC.
- */
-#define BD_ENET_TX_READY (0x8000)
-#define BD_ENET_TX_PAD (0x4000)
-#define BD_ENET_TX_WRAP (0x2000)
-#define BD_ENET_TX_INTR (0x1000)
-#define BD_ENET_TX_LAST (0x0800)
-#define BD_ENET_TX_TC (0x0400)
-#define BD_ENET_TX_DEF (0x0200)
-#define BD_ENET_TX_HB (0x0100)
-#define BD_ENET_TX_LC (0x0080)
-#define BD_ENET_TX_RL (0x0040)
-#define BD_ENET_TX_RCMASK (0x003c)
-#define BD_ENET_TX_UN (0x0002)
-#define BD_ENET_TX_CSL (0x0001)
-#define BD_ENET_TX_STATS (0x03ff) /* All status bits */
-
-/* Buffer descriptor control/status used by Transparent mode SCC.
- */
-#define BD_SCC_TX_LAST (0x0800)
-
-/* Buffer descriptor control/status used by I2C.
- */
-#define BD_I2C_START (0x0400)
-
-#ifdef CONFIG_CPM
-int cpm_command(u32 command, u8 opcode);
-#else
-static inline int cpm_command(u32 command, u8 opcode)
-{
- return -ENOSYS;
-}
-#endif /* CONFIG_CPM */
-
-int cpm2_gpiochip_add32(struct device *dev);
-
-#endif
+#include <soc/fsl/cpm.h>
diff --git a/include/soc/fsl/cpm.h b/include/soc/fsl/cpm.h
new file mode 100644
index 000000000000..4c24ea8209bb
--- /dev/null
+++ b/include/soc/fsl/cpm.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __CPM_H
+#define __CPM_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/of.h>
+#include <soc/fsl/qe/qe.h>
+
+/*
+ * SPI Parameter RAM common to QE and CPM.
+ */
+struct spi_pram {
+ __be16 rbase; /* Rx Buffer descriptor base address */
+ __be16 tbase; /* Tx Buffer descriptor base address */
+ u8 rfcr; /* Rx function code */
+ u8 tfcr; /* Tx function code */
+ __be16 mrblr; /* Max receive buffer length */
+ __be32 rstate; /* Internal */
+ __be32 rdp; /* Internal */
+ __be16 rbptr; /* Internal */
+ __be16 rbc; /* Internal */
+ __be32 rxtmp; /* Internal */
+ __be32 tstate; /* Internal */
+ __be32 tdp; /* Internal */
+ __be16 tbptr; /* Internal */
+ __be16 tbc; /* Internal */
+ __be32 txtmp; /* Internal */
+ __be32 res; /* Tx temp. */
+ __be16 rpbase; /* Relocation pointer (CPM1 only) */
+ __be16 res1; /* Reserved */
+};
+
+/*
+ * USB Controller pram common to QE and CPM.
+ */
+struct usb_ctlr {
+ u8 usb_usmod;
+ u8 usb_usadr;
+ u8 usb_uscom;
+ u8 res1[1];
+ __be16 usb_usep[4];
+ u8 res2[4];
+ __be16 usb_usber;
+ u8 res3[2];
+ __be16 usb_usbmr;
+ u8 res4[1];
+ u8 usb_usbs;
+ /* Fields down below are QE-only */
+ __be16 usb_ussft;
+ u8 res5[2];
+ __be16 usb_usfrn;
+ u8 res6[0x22];
+} __attribute__ ((packed));
+
+/*
+ * Function code bits, usually generic to devices.
+ */
+#ifdef CONFIG_CPM1
+#define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */
+#define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */
+#define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
+#define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
+#else
+#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
+#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
+#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
+#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
+#endif
+#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
+
+/* Opcodes common to CPM1 and CPM2
+*/
+#define CPM_CR_INIT_TRX ((ushort)0x0000)
+#define CPM_CR_INIT_RX ((ushort)0x0001)
+#define CPM_CR_INIT_TX ((ushort)0x0002)
+#define CPM_CR_HUNT_MODE ((ushort)0x0003)
+#define CPM_CR_STOP_TX ((ushort)0x0004)
+#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
+#define CPM_CR_RESTART_TX ((ushort)0x0006)
+#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
+#define CPM_CR_SET_GADDR ((ushort)0x0008)
+#define CPM_CR_SET_TIMER ((ushort)0x0008)
+#define CPM_CR_STOP_IDMA ((ushort)0x000b)
+
+/* Buffer descriptors used by many of the CPM protocols. */
+typedef struct cpm_buf_desc {
+ ushort cbd_sc; /* Status and Control */
+ ushort cbd_datlen; /* Data length in buffer */
+ uint cbd_bufaddr; /* Buffer address in host memory */
+} cbd_t;
+
+/* Buffer descriptor control/status used by serial
+ */
+
+#define BD_SC_EMPTY (0x8000) /* Receive is empty */
+#define BD_SC_READY (0x8000) /* Transmit is ready */
+#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
+#define BD_SC_INTRPT (0x1000) /* Interrupt on change */
+#define BD_SC_LAST (0x0800) /* Last buffer in frame */
+#define BD_SC_TC (0x0400) /* Transmit CRC */
+#define BD_SC_CM (0x0200) /* Continuous mode */
+#define BD_SC_ID (0x0100) /* Rec'd too many idles */
+#define BD_SC_P (0x0100) /* xmt preamble */
+#define BD_SC_BR (0x0020) /* Break received */
+#define BD_SC_FR (0x0010) /* Framing error */
+#define BD_SC_PR (0x0008) /* Parity error */
+#define BD_SC_NAK (0x0004) /* NAK - did not respond */
+#define BD_SC_OV (0x0002) /* Overrun */
+#define BD_SC_UN (0x0002) /* Underrun */
+#define BD_SC_CD (0x0001) /* */
+#define BD_SC_CL (0x0001) /* Collision */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_RX_EMPTY (0x8000)
+#define BD_ENET_RX_WRAP (0x2000)
+#define BD_ENET_RX_INTR (0x1000)
+#define BD_ENET_RX_LAST (0x0800)
+#define BD_ENET_RX_FIRST (0x0400)
+#define BD_ENET_RX_MISS (0x0100)
+#define BD_ENET_RX_BC (0x0080) /* FCC Only */
+#define BD_ENET_RX_MC (0x0040) /* FCC Only */
+#define BD_ENET_RX_LG (0x0020)
+#define BD_ENET_RX_NO (0x0010)
+#define BD_ENET_RX_SH (0x0008)
+#define BD_ENET_RX_CR (0x0004)
+#define BD_ENET_RX_OV (0x0002)
+#define BD_ENET_RX_CL (0x0001)
+#define BD_ENET_RX_STATS (0x01ff) /* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_TX_READY (0x8000)
+#define BD_ENET_TX_PAD (0x4000)
+#define BD_ENET_TX_WRAP (0x2000)
+#define BD_ENET_TX_INTR (0x1000)
+#define BD_ENET_TX_LAST (0x0800)
+#define BD_ENET_TX_TC (0x0400)
+#define BD_ENET_TX_DEF (0x0200)
+#define BD_ENET_TX_HB (0x0100)
+#define BD_ENET_TX_LC (0x0080)
+#define BD_ENET_TX_RL (0x0040)
+#define BD_ENET_TX_RCMASK (0x003c)
+#define BD_ENET_TX_UN (0x0002)
+#define BD_ENET_TX_CSL (0x0001)
+#define BD_ENET_TX_STATS (0x03ff) /* All status bits */
+
+/* Buffer descriptor control/status used by Transparent mode SCC.
+ */
+#define BD_SCC_TX_LAST (0x0800)
+
+/* Buffer descriptor control/status used by I2C.
+ */
+#define BD_I2C_START (0x0400)
+
+#ifdef CONFIG_CPM
+int cpm_command(u32 command, u8 opcode);
+#else
+static inline int cpm_command(u32 command, u8 opcode)
+{
+ return -ENOSYS;
+}
+#endif /* CONFIG_CPM */
+
+int cpm2_gpiochip_add32(struct device *dev);
+
+#endif
--
2.23.0