Add compatible for J721e CPSW9G, which contains 8 external ports and 1
internal host port.
Update existing approach of using compatible to differentiate between
devices that support QSGMII mode and those that don't. The new
approach involves storing the number of qsgmii main ports for the device
in the num_qsgmii_main_ports member of the "struct phy_gmii_sel_soc_data".
This approach makes it scalable for newer devices.
=========
Changelog
=========
v2 -> v3:
1. Run 'make DT_CHECKER_FLAGS=-m dt_binding_check' and fix errors and
warnings corresponding to the patch for:
Documentation/devicetree/bindings/phy/ti,phy-gmii-sel
with the latest dt-schema and yamllint.
v1 -> v2:
1. Drop all patches corresponding to SGMII mode. This is done since I do
not have a method to test SGMII in the standard mode which uses an
SGMII PHY. The previous series used SGMII in a fixed-link mode,
bypassing the SGMII PHY. I will post the SGMII patches in a future
series after testing them.
2. Update description for the property "ti,qsgmii-main-ports", to describe
it in a unified way across the compatibles.
3. Add minItems, maxItems, and items at the top, where the property
"ti,qsgmii-main-ports" is first defined. Modify them later
appropriately, based on the compatible.
4. Update the method to fetch the property "ti,qsgmii-main-ports" from the
device-tree, to make it scalable.
5. Use dev_err() when the value(s) provided in the device-tree for the
property "ti,qsgmii-main-ports" is/are invalid.
v2:
https://lore.kernel.org/r/[email protected]/
v1:
https://lore.kernel.org/r/[email protected]/
Siddharth Vadapalli (3):
dt-bindings: phy: ti: phy-gmii-sel: Add bindings for J721e
phy: ti: gmii-sel: Update methods for fetching and using qsgmii main
port
phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J721e
.../bindings/phy/ti,phy-gmii-sel.yaml | 48 ++++++++++++++++---
drivers/phy/ti/phy-gmii-sel.c | 42 +++++++++++++---
2 files changed, 77 insertions(+), 13 deletions(-)
--
2.25.1
On 26-10-22, 13:15, Siddharth Vadapalli wrote:
> Add compatible for J721e CPSW9G, which contains 8 external ports and 1
> internal host port.
>
> Update existing approach of using compatible to differentiate between
> devices that support QSGMII mode and those that don't. The new
> approach involves storing the number of qsgmii main ports for the device
> in the num_qsgmii_main_ports member of the "struct phy_gmii_sel_soc_data".
> This approach makes it scalable for newer devices.
Applied, thanks
--
~Vinod