Hi,
This series contains patches related to the support of mt8365 iommu.
Thanks for your feedback so far.
Regards,
Alex
Changes in v6:
- Rebase
- Add new trailers
- Link to v5: https://lore.kernel.org/r/[email protected]
Changes in v5:
- Fix name file in mediatek,iommu.yaml
- Rename defines to be more consistent
- Rework INT_ID_PORT_WIDTH_6 check
- Link to v4: https://lore.kernel.org/r/[email protected]
Changes in v4:
- Typo
- Rebase
- Link to v3: https://lore.kernel.org/r/[email protected]
Changes in v3:
- Rename "mt8365-larb-port.h" to "mediatek,mt8365-larb-port.h"
- Rework the macros which retrieve larb/port ID to improve human readability
- Link to v2: https://lore.kernel.org/r/[email protected]
Changes in v2:
- Rebase.
- Change M4U_PORT_APU_READ & M4U_PORT_APU_WRITE port to avoid display
conflict in larb0. These definitions are used for vpu0 device node.
- Add dual license.
- Retitle commit.
- Rename to int_id_port_width for more detail.
- Fix typo.
- Set banks_enable and banks_num in mt8365_data to fix kernel panic at boot.
- Link to v1 - https://lore.kernel.org/lkml/[email protected]/
To: Yong Wu <[email protected]>
To: Joerg Roedel <[email protected]>
To: Will Deacon <[email protected]>
To: Robin Murphy <[email protected]>
To: Rob Herring <[email protected]>
To: Krzysztof Kozlowski <[email protected]>
To: Matthias Brugger <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Fabien Parent <[email protected]>
Cc: Markus Schneider-Pargmann <[email protected]>
Cc: Amjad Ouled-Ameur <[email protected]>
Cc: AngeloGioacchino Del Regno <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Fabien Parent (3):
dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC
iommu/mediatek: add support for 6-bit encoded port IDs
iommu/mediatek: add support for MT8365 SoC
.../devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +
drivers/iommu/mtk_iommu.c | 25 +++++-
.../dt-bindings/memory/mediatek,mt8365-larb-port.h | 90 ++++++++++++++++++++++
3 files changed, 116 insertions(+), 1 deletion(-)
---
base-commit: 11082343e3bf2953a937509f0316cabf69dbf908
change-id: 20221001-iommu-support-f409c7e094e6
Best regards,
--
Alexandre Mergnat <[email protected]>
From: Fabien Parent <[email protected]>
Add IOMMU support for MT8365 SoC.
Signed-off-by: Fabien Parent <[email protected]>
Reviewed-by: Amjad Ouled-Ameur <[email protected]>
Tested-by: Amjad Ouled-Ameur <[email protected]>
Signed-off-by: Markus Schneider-Pargmann <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Yong Wu <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
drivers/iommu/mtk_iommu.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 563e3c54a0e2..aff7a9190749 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -170,6 +170,7 @@ enum mtk_iommu_plat {
M4U_MT8186,
M4U_MT8192,
M4U_MT8195,
+ M4U_MT8365,
};
struct mtk_iommu_iova_region {
@@ -1525,6 +1526,17 @@ static const struct mtk_iommu_plat_data mt8195_data_vpp = {
{4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}},
};
+static const struct mtk_iommu_plat_data mt8365_data = {
+ .m4u_plat = M4U_MT8365,
+ .flags = RESET_AXI | INT_ID_PORT_WIDTH_6,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
+ .banks_num = 1,
+ .banks_enable = {true},
+ .iova_region = single_domain,
+ .iova_region_nr = ARRAY_SIZE(single_domain),
+ .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
@@ -1537,6 +1549,7 @@ static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
{ .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo},
{ .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp},
+ { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data},
{}
};
--
b4 0.10.1
From: Fabien Parent <[email protected]>
Until now the port ID was always encoded as a 5-bit data. On MT8365,
the port ID is encoded as a 6-bit data. This requires to add extra
macro F_MMU_INT_ID_LARB_ID_EXT, and F_MMU_INT_ID_PORT_ID_EXT in order
to support 6-bit encoded port IDs.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Markus Schneider-Pargmann <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Reviewed-by: Yong Wu <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
drivers/iommu/mtk_iommu.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5a4e00e4bbbc..563e3c54a0e2 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -108,8 +108,12 @@
#define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
#define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7)
#define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7)
+/* Macro for 5 bits length port ID field (default) */
#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
+/* Macro for 6 bits length port ID field */
+#define F_MMU_INT_ID_LARB_ID_WID_6(a) (((a) >> 8) & 0x7)
+#define F_MMU_INT_ID_PORT_ID_WID_6(a) (((a) >> 2) & 0x3f)
#define MTK_PROTECT_PA_ALIGN 256
#define MTK_IOMMU_BANK_SZ 0x1000
@@ -139,6 +143,7 @@
#define IFA_IOMMU_PCIE_SUPPORT BIT(16)
#define PGTABLE_PA_35_EN BIT(17)
#define TF_PORT_TO_ADDR_MT8173 BIT(18)
+#define INT_ID_PORT_WIDTH_6 BIT(19)
#define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
((((pdata)->flags) & (mask)) == (_x))
@@ -441,14 +446,19 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
fault_pa |= (u64)pa34_32 << 32;
if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) {
- fault_port = F_MMU_INT_ID_PORT_ID(regval);
if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
fault_larb = F_MMU_INT_ID_COMM_ID(regval);
sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
+ fault_port = F_MMU_INT_ID_PORT_ID(regval);
} else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) {
fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
+ fault_port = F_MMU_INT_ID_PORT_ID(regval);
+ } else if (MTK_IOMMU_HAS_FLAG(plat_data, INT_ID_PORT_WIDTH_6)) {
+ fault_port = F_MMU_INT_ID_PORT_ID_WID_6(regval);
+ fault_larb = F_MMU_INT_ID_LARB_ID_WID_6(regval);
} else {
+ fault_port = F_MMU_INT_ID_PORT_ID(regval);
fault_larb = F_MMU_INT_ID_LARB_ID(regval);
}
fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
--
b4 0.10.1
On 02/11/2022 16:18, Alexandre Mergnat wrote:
> Hi,
>
> This series contains patches related to the support of mt8365 iommu.
> Thanks for your feedback so far.
>
> Regards,
> Alex
>
> Changes in v6:
> - Rebase
> - Add new trailers
> - Link to v5: https://lore.kernel.org/r/[email protected]
>
> Changes in v5:
> - Fix name file in mediatek,iommu.yaml
> - Rename defines to be more consistent
> - Rework INT_ID_PORT_WIDTH_6 check
> - Link to v4: https://lore.kernel.org/r/[email protected]
>
> Changes in v4:
> - Typo
> - Rebase
> - Link to v3: https://lore.kernel.org/r/[email protected]
>
> Changes in v3:
> - Rename "mt8365-larb-port.h" to "mediatek,mt8365-larb-port.h"
> - Rework the macros which retrieve larb/port ID to improve human readability
> - Link to v2: https://lore.kernel.org/r/[email protected]
>
> Changes in v2:
> - Rebase.
> - Change M4U_PORT_APU_READ & M4U_PORT_APU_WRITE port to avoid display
> conflict in larb0. These definitions are used for vpu0 device node.
> - Add dual license.
> - Retitle commit.
> - Rename to int_id_port_width for more detail.
> - Fix typo.
> - Set banks_enable and banks_num in mt8365_data to fix kernel panic at boot.
> - Link to v1 - https://lore.kernel.org/lkml/[email protected]/
>
> To: Yong Wu <[email protected]>
> To: Joerg Roedel <[email protected]>
> To: Will Deacon <[email protected]>
> To: Robin Murphy <[email protected]>
> To: Rob Herring <[email protected]>
> To: Krzysztof Kozlowski <[email protected]>
> To: Matthias Brugger <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: [email protected]
> Cc: Fabien Parent <[email protected]>
> Cc: Markus Schneider-Pargmann <[email protected]>
> Cc: Amjad Ouled-Ameur <[email protected]>
> Cc: AngeloGioacchino Del Regno <[email protected]>
> Cc: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
>
> ---
> Fabien Parent (3):
> dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC
> iommu/mediatek: add support for 6-bit encoded port IDs
> iommu/mediatek: add support for MT8365 SoC
>
> .../devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +
> drivers/iommu/mtk_iommu.c | 25 +++++-
> .../dt-bindings/memory/mediatek,mt8365-larb-port.h | 90 ++++++++++++++++++++++
> 3 files changed, 116 insertions(+), 1 deletion(-)
> ---
> base-commit: 11082343e3bf2953a937509f0316cabf69dbf908
> change-id: 20221001-iommu-support-f409c7e094e6
>
For the whole series:
Reviewed-by: Matthias Brugger <[email protected]>
On Wed, Nov 02, 2022 at 04:18:06PM +0100, Alexandre Mergnat wrote:
> Fabien Parent (3):
> dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC
> iommu/mediatek: add support for 6-bit encoded port IDs
> iommu/mediatek: add support for MT8365 SoC
Applied, thanks.