Adds status interface for zynqmp-fpga, It's a read only interface
which allows the user to get the Programmable Logic(PL) status.
-Device Initialization error.
-Device internal signal error.
-All I/Os are placed in High-Z state.
-Device start-up sequence error.
-Firmware error.
For more details refer the ug570.
https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
Nava kishore Manne (2):
firmware: xilinx: Add pm api function for PL config reg readback
fpga: zynqmp-fpga: Adds status interface
drivers/firmware/xilinx/zynqmp.c | 33 +++++++++++
drivers/fpga/zynqmp-fpga.c | 87 ++++++++++++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 10 ++++
3 files changed, 130 insertions(+)
--
2.25.1
Adds PM API for performing Programmable Logic(PL) configuration
register readback. It provides an interface to the firmware(pmufw)
to readback the FPGA configuration register.
Signed-off-by: Nava kishore Manne <[email protected]>
---
changes for v2:
- None.
Changes for v3:
- Updated API and config reg read-back handling logic
- Updated the commit msg to align with the changes.
Changes for v4:
- Fix some minor coding issues. No functional changes.
- Updated Return value comments as suggested by Xu Yilun.
drivers/firmware/xilinx/zynqmp.c | 33 ++++++++++++++++++++++++++++
include/linux/firmware/xlnx-zynqmp.h | 10 +++++++++
2 files changed, 43 insertions(+)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index ff5cabe70a2b..ca954e1119b5 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -941,6 +941,39 @@ int zynqmp_pm_fpga_get_status(u32 *value)
}
EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status);
+/**
+ * zynqmp_pm_fpga_get_config_status - Get the FPGA configuration status.
+ * @value: Buffer to store FPGA configuration status.
+ *
+ * This function provides access to the pmufw to get the FPGA configuration
+ * status
+ *
+ * Return: 0 on success, a negative value on error
+ */
+int zynqmp_pm_fpga_get_config_status(u32 *value)
+{
+ u32 buf, phys_lower_addr, phys_upper_addr;
+ u32 ret_payload[PAYLOAD_ARG_CNT];
+ int ret;
+
+ if (!value)
+ return -EINVAL;
+
+ phys_lower_addr = lower_32_bits((u64)&buf);
+ phys_upper_addr = upper_32_bits((u64)&buf);
+
+ ret = zynqmp_pm_invoke_fn(PM_FPGA_READ,
+ XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET,
+ phys_lower_addr, phys_upper_addr,
+ XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG,
+ ret_payload);
+
+ *value = ret_payload[1];
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_config_status);
+
/**
* zynqmp_pm_pinctrl_request - Request Pin from firmware
* @pin: Pin number to request
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 76d2b3ebad84..29e8964f4297 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -70,6 +70,10 @@
#define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
#define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
+/* FPGA Status Reg */
+#define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U
+#define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG 0U
+
/*
* Node IDs for the Error Events.
*/
@@ -117,6 +121,7 @@ enum pm_api_id {
PM_CLOCK_GETRATE = 42,
PM_CLOCK_SETPARENT = 43,
PM_CLOCK_GETPARENT = 44,
+ PM_FPGA_READ = 46,
PM_SECURE_AES = 47,
PM_FEATURE_CHECK = 63,
};
@@ -505,6 +510,7 @@ int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
u32 value);
+int zynqmp_pm_fpga_get_config_status(u32 *value);
#else
static inline int zynqmp_pm_get_api_version(u32 *version)
{
@@ -790,6 +796,10 @@ static inline int zynqmp_pm_set_gem_config(u32 node,
return -ENODEV;
}
+static inline int zynqmp_pm_fpga_get_config_status(u32 *value)
+{
+ return -ENODEV;
+}
#endif
#endif /* __FIRMWARE_ZYNQMP_H__ */
--
2.25.1
On 2022-12-23 at 17:28:49 +0530, Nava kishore Manne wrote:
> Adds PM API for performing Programmable Logic(PL) configuration
> register readback. It provides an interface to the firmware(pmufw)
> to readback the FPGA configuration register.
>
> Signed-off-by: Nava kishore Manne <[email protected]>
> ---
> changes for v2:
> - None.
>
> Changes for v3:
> - Updated API and config reg read-back handling logic
> - Updated the commit msg to align with the changes.
>
> Changes for v4:
> - Fix some minor coding issues. No functional changes.
> - Updated Return value comments as suggested by Xu Yilun.
>
> drivers/firmware/xilinx/zynqmp.c | 33 ++++++++++++++++++++++++++++
> include/linux/firmware/xlnx-zynqmp.h | 10 +++++++++
> 2 files changed, 43 insertions(+)
>
> diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
> index ff5cabe70a2b..ca954e1119b5 100644
> --- a/drivers/firmware/xilinx/zynqmp.c
> +++ b/drivers/firmware/xilinx/zynqmp.c
> @@ -941,6 +941,39 @@ int zynqmp_pm_fpga_get_status(u32 *value)
> }
> EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_status);
>
> +/**
> + * zynqmp_pm_fpga_get_config_status - Get the FPGA configuration status.
> + * @value: Buffer to store FPGA configuration status.
> + *
> + * This function provides access to the pmufw to get the FPGA configuration
> + * status
> + *
> + * Return: 0 on success, a negative value on error
> + */
> +int zynqmp_pm_fpga_get_config_status(u32 *value)
> +{
> + u32 buf, phys_lower_addr, phys_upper_addr;
Why naming them phys_xxx?
> + u32 ret_payload[PAYLOAD_ARG_CNT];
> + int ret;
> +
> + if (!value)
> + return -EINVAL;
> +
> + phys_lower_addr = lower_32_bits((u64)&buf);
> + phys_upper_addr = upper_32_bits((u64)&buf);
> +
> + ret = zynqmp_pm_invoke_fn(PM_FPGA_READ,
> + XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET,
> + phys_lower_addr, phys_upper_addr,
> + XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG,
> + ret_payload);
> +
> + *value = ret_payload[1];
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(zynqmp_pm_fpga_get_config_status);
> +
> /**
> * zynqmp_pm_pinctrl_request - Request Pin from firmware
> * @pin: Pin number to request
> diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
> index 76d2b3ebad84..29e8964f4297 100644
> --- a/include/linux/firmware/xlnx-zynqmp.h
> +++ b/include/linux/firmware/xlnx-zynqmp.h
> @@ -70,6 +70,10 @@
> #define XILINX_ZYNQMP_PM_FPGA_FULL 0x0U
> #define XILINX_ZYNQMP_PM_FPGA_PARTIAL BIT(0)
>
> +/* FPGA Status Reg */
> +#define XILINX_ZYNQMP_PM_FPGA_CONFIG_STAT_OFFSET 7U
> +#define XILINX_ZYNQMP_PM_FPGA_READ_CONFIG_REG 0U
> +
> /*
> * Node IDs for the Error Events.
> */
> @@ -117,6 +121,7 @@ enum pm_api_id {
> PM_CLOCK_GETRATE = 42,
> PM_CLOCK_SETPARENT = 43,
> PM_CLOCK_GETPARENT = 44,
> + PM_FPGA_READ = 46,
> PM_SECURE_AES = 47,
> PM_FEATURE_CHECK = 63,
> };
> @@ -505,6 +510,7 @@ int zynqmp_pm_register_sgi(u32 sgi_num, u32 reset);
> int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
> int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
> u32 value);
> +int zynqmp_pm_fpga_get_config_status(u32 *value);
Is it better put it along with zynqmp_pm_fpga_get_status()?
Thanks,
Yilun
> #else
> static inline int zynqmp_pm_get_api_version(u32 *version)
> {
> @@ -790,6 +796,10 @@ static inline int zynqmp_pm_set_gem_config(u32 node,
> return -ENODEV;
> }
>
> +static inline int zynqmp_pm_fpga_get_config_status(u32 *value)
> +{
> + return -ENODEV;
> +}
> #endif
>
> #endif /* __FIRMWARE_ZYNQMP_H__ */
> --
> 2.25.1
>