On Thu, Jan 19, 2023 at 04:04:51PM +0200, Abel Vesa wrote:
> Add compatible for both PCIe found on SM8550.
> Also add the cnoc_pcie_sf_axi clock needed by the SM8550.
>
> Signed-off-by: Abel Vesa <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
> Reviewed-by: Konrad Dybcio <[email protected]>
> ---
>
> The v3 of this patchset is:
> https://lore.kernel.org/all/[email protected]/
>
> Changes since v3:
> * renamed cnoc_pcie_sf_axi to cnoc_sf_axi
>
> Changes since v2:
> * none
>
> Changes since v1:
> * changed the subject line prefix for the patch to match the history,
> like Bjorn Helgaas suggested.
> * added Konrad's R-b tag
>
>
> drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 77e5dc7b88ad..30f74bc51dbf 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -182,7 +182,7 @@ struct qcom_pcie_resources_2_3_3 {
>
> /* 6 clocks typically, 7 for sm8250 */
Now this comment is outdated ;)
Thanks,
Mani
> struct qcom_pcie_resources_2_7_0 {
> - struct clk_bulk_data clks[12];
> + struct clk_bulk_data clks[13];
> int num_clks;
> struct regulator_bulk_data supplies[2];
> struct reset_control *pci_reset;
> @@ -1208,6 +1208,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
> res->clks[idx++].id = "noc_aggr_4";
> res->clks[idx++].id = "noc_aggr_south_sf";
> res->clks[idx++].id = "cnoc_qx";
> + res->clks[idx++].id = "cnoc_sf_axi";
>
> num_opt_clks = idx - num_clks;
> res->num_clks = idx;
> @@ -1828,6 +1829,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
> { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
> { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
> + { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
> { }
> };
>
> --
> 2.34.1
>
--
மணிவண்ணன் சதாசிவம்
On 23-01-19 19:51:55, Manivannan Sadhasivam wrote:
> On Thu, Jan 19, 2023 at 04:04:51PM +0200, Abel Vesa wrote:
> > Add compatible for both PCIe found on SM8550.
> > Also add the cnoc_pcie_sf_axi clock needed by the SM8550.
> >
> > Signed-off-by: Abel Vesa <[email protected]>
>
> Reviewed-by: Manivannan Sadhasivam <[email protected]>
>
> > Reviewed-by: Konrad Dybcio <[email protected]>
> > ---
> >
> > The v3 of this patchset is:
> > https://lore.kernel.org/all/[email protected]/
> >
> > Changes since v3:
> > * renamed cnoc_pcie_sf_axi to cnoc_sf_axi
> >
> > Changes since v2:
> > * none
> >
> > Changes since v1:
> > * changed the subject line prefix for the patch to match the history,
> > like Bjorn Helgaas suggested.
> > * added Konrad's R-b tag
> >
> >
> > drivers/pci/controller/dwc/pcie-qcom.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > index 77e5dc7b88ad..30f74bc51dbf 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -182,7 +182,7 @@ struct qcom_pcie_resources_2_3_3 {
> >
> > /* 6 clocks typically, 7 for sm8250 */
>
> Now this comment is outdated ;)
>
Fair point. I'll wait for some more comments before
I'll send a new version.
> Thanks,
> Mani
>
> > struct qcom_pcie_resources_2_7_0 {
> > - struct clk_bulk_data clks[12];
> > + struct clk_bulk_data clks[13];
> > int num_clks;
> > struct regulator_bulk_data supplies[2];
> > struct reset_control *pci_reset;
> > @@ -1208,6 +1208,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
> > res->clks[idx++].id = "noc_aggr_4";
> > res->clks[idx++].id = "noc_aggr_south_sf";
> > res->clks[idx++].id = "cnoc_qx";
> > + res->clks[idx++].id = "cnoc_sf_axi";
> >
> > num_opt_clks = idx - num_clks;
> > res->num_clks = idx;
> > @@ -1828,6 +1829,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> > { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
> > { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
> > { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
> > + { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
> > { }
> > };
> >
> > --
> > 2.34.1
> >
>
> --
> மணிவண்ணன் சதாசிவம்
On Thu, Jan 19, 2023 at 05:35:08PM +0200, Abel Vesa wrote:
> On 23-01-19 19:51:55, Manivannan Sadhasivam wrote:
> > On Thu, Jan 19, 2023 at 04:04:51PM +0200, Abel Vesa wrote:
> > > Add compatible for both PCIe found on SM8550.
> > > Also add the cnoc_pcie_sf_axi clock needed by the SM8550.
> > >
> > > Signed-off-by: Abel Vesa <[email protected]>
> >
> > Reviewed-by: Manivannan Sadhasivam <[email protected]>
> >
> > > Reviewed-by: Konrad Dybcio <[email protected]>
> > > ---
> > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > > index 77e5dc7b88ad..30f74bc51dbf 100644
> > > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > > @@ -182,7 +182,7 @@ struct qcom_pcie_resources_2_3_3 {
> > >
> > > /* 6 clocks typically, 7 for sm8250 */
> >
> > Now this comment is outdated ;)
> >
>
> Fair point. I'll wait for some more comments before
> I'll send a new version.
The comment is still correct, as several of these clocks are optional
and platform dependant. There's strictly no need to update it as part
of this patch.
> > > struct qcom_pcie_resources_2_7_0 {
> > > - struct clk_bulk_data clks[12];
> > > + struct clk_bulk_data clks[13];
> > > int num_clks;
> > > struct regulator_bulk_data supplies[2];
> > > struct reset_control *pci_reset;
> > > @@ -1208,6 +1208,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
> > > res->clks[idx++].id = "noc_aggr_4";
> > > res->clks[idx++].id = "noc_aggr_south_sf";
> > > res->clks[idx++].id = "cnoc_qx";
> > > + res->clks[idx++].id = "cnoc_sf_axi";
Johan