i.MX PCIe controller is one dual mode PCIe controller, and can work either
as RC or EP.
This series add the i.MX PCIe EP mode support. And had been verified on
i.MX8MQ, i.MX8MM EVK and i.MX8MP EVK boards.
In the verification, one EVK board used as RC, the other one used as EP.
Use the cross TX/RX differential cable connect the two PCIe ports of these
two EVK boards.
+-----------+ +------------+
| PCIe TX |<-------------->|PCIe RX |
| | | |
|EVK Board | |EVK Board |
| | | |
| PCIe RX |<-------------->|PCIe TX |
+-----------+ +------------+
NOTE:
Re-base to 6.1-rc1, and re-send the v4 series.
BTW, the following PHY changes [1] is required when apply this series.
[1] https://patchwork.kernel.org/project/linux-pci/cover/[email protected]/
Main changes from v3 -> v4:
- Add the Rob's ACK in the dt-binding patch.
- Use "i.MX" to keep spell consistent.
- Squash generic endpoint infrastructure changes of
"[12/14] PCI: imx6: Add iMX8MM PCIe EP mode" into Kconfig changes.
Main changes from v2 -> v3:
- Add the i.MX8MP PCIe EP support, and verified on i.MX8MP EVK board.
- Rebase to latest pci/next branch(tag: v6.0-rc1 plus some PCIe changes).
Main changes from v1 -> v2:
- Add Rob's ACK into first two commits.
- Rebase to the tag: pci-v5.20-changes of the pci/next branch.
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 3 ++
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 14 ++++++
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 20 +++++++++
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 13 ++++++
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 19 ++++++++
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 12 ++++++
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 27 ++++++++++++
drivers/misc/pci_endpoint_test.c | 2 +
drivers/pci/controller/dwc/Kconfig | 23 +++++++++-
drivers/pci/controller/dwc/pci-imx6.c | 200 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--------
10 files changed, 314 insertions(+), 19 deletions(-)
[RESEND v4 01/14] dt-bindings: imx6q-pcie: Add i.MX8MM PCIe EP mode
[RESEND v4 02/14] dt-bindings: imx6q-pcie: Add i.MX8MQ PCIe EP mode
[RESEND v4 03/14] dt-bindings: imx6q-pcie: Add i.MX8MP PCIe EP mode
[RESEND v4 04/14] arm64: dts: Add i.MX8MM PCIe EP support
[RESEND v4 05/14] arm64: dts: Add i.MX8MM PCIe EP support on EVK
[RESEND v4 06/14] arm64: dts: Add i.MX8MQ PCIe EP support
[RESEND v4 07/14] arm64: dts: Add i.MX8MQ PCIe EP support on EVK
[RESEND v4 08/14] arm64: dts: Add i.MX8MP PCIe EP support
[RESEND v4 09/14] arm64: dts: Add i.MX8MP PCIe EP support on EVK
[RESEND v4 10/14] misc: pci_endpoint_test: Add i.MX8 PCIe EP device
[RESEND v4 11/14] PCI: imx6: Add i.MX PCIe EP mode support
[RESEND v4 12/14] PCI: imx6: Add i.MX8MQ PCIe EP support
[RESEND v4 13/14] PCI: imx6: Add i.MX8MM PCIe EP support
[RESEND v4 14/14] PCI: imx6: Add i.MX8MP PCIe EP support
Add i.MX8MM PCIe endpoint mode compatible string.
Signed-off-by: Richard Zhu <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 376e739bcad4..e4038e2b3de9 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -27,6 +27,7 @@ properties:
- fsl,imx8mq-pcie
- fsl,imx8mm-pcie
- fsl,imx8mp-pcie
+ - fsl,imx8mm-pcie-ep
reg:
items:
--
2.25.1
Add the i.MX8MP PCIe EP support.
Signed-off-by: Richard Zhu <[email protected]>
---
drivers/pci/controller/dwc/pci-imx6.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 3f01cf3776ec..3f04b9ebfd0f 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -54,6 +54,7 @@ enum imx6_pcie_variants {
IMX8MP,
IMX8MQ_EP,
IMX8MM_EP,
+ IMX8MP_EP,
};
#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
@@ -158,7 +159,8 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
imx6_pcie->drvdata->variant != IMX8MQ_EP &&
imx6_pcie->drvdata->variant != IMX8MM &&
imx6_pcie->drvdata->variant != IMX8MM_EP &&
- imx6_pcie->drvdata->variant != IMX8MP);
+ imx6_pcie->drvdata->variant != IMX8MP &&
+ imx6_pcie->drvdata->variant != IMX8MP_EP);
return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
}
@@ -323,6 +325,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
case IMX8MM:
case IMX8MM_EP:
case IMX8MP:
+ case IMX8MP_EP:
/*
* The PHY initialization had been done in the PHY
* driver, break here directly.
@@ -584,6 +587,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
case IMX8MQ:
case IMX8MQ_EP:
case IMX8MP:
+ case IMX8MP_EP:
ret = clk_prepare_enable(imx6_pcie->pcie_aux);
if (ret) {
dev_err(dev, "unable to enable pcie_aux clock\n");
@@ -631,6 +635,7 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
case IMX8MQ:
case IMX8MQ_EP:
case IMX8MP:
+ case IMX8MP_EP:
clk_disable_unprepare(imx6_pcie->pcie_aux);
break;
default:
@@ -701,6 +706,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
case IMX8MM:
case IMX8MM_EP:
case IMX8MP:
+ case IMX8MP_EP:
reset_control_assert(imx6_pcie->apps_reset);
break;
case IMX6SX:
@@ -779,6 +785,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
case IMX8MM:
case IMX8MM_EP:
case IMX8MP:
+ case IMX8MP_EP:
break;
}
@@ -831,6 +838,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
case IMX8MM:
case IMX8MM_EP:
case IMX8MP:
+ case IMX8MP_EP:
reset_control_deassert(imx6_pcie->apps_reset);
break;
}
@@ -853,6 +861,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
case IMX8MM:
case IMX8MM_EP:
case IMX8MP:
+ case IMX8MP_EP:
reset_control_assert(imx6_pcie->apps_reset);
break;
}
@@ -1104,6 +1113,7 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
switch (imx6_pcie->drvdata->variant) {
case IMX8MQ_EP:
case IMX8MM_EP:
+ case IMX8MP_EP:
pcie_dbi2_offset = SZ_1M;
break;
default:
@@ -1318,6 +1328,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
case IMX8MM:
case IMX8MM_EP:
case IMX8MP:
+ case IMX8MP_EP:
imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
if (IS_ERR(imx6_pcie->pcie_aux))
return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
@@ -1487,6 +1498,11 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.mode = DW_PCIE_EP_TYPE,
.gpr = "fsl,imx8mm-iomuxc-gpr",
},
+ [IMX8MP_EP] = {
+ .variant = IMX8MP_EP,
+ .mode = DW_PCIE_EP_TYPE,
+ .gpr = "fsl,imx8mp-iomuxc-gpr",
+ },
};
static const struct of_device_id imx6_pcie_of_match[] = {
@@ -1499,6 +1515,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
{ .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
{ .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
+ { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
{},
};
--
2.25.1
Add i.MX8MP PCIe endpoint mode compatible string.
Signed-off-by: Richard Zhu <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 114e11b62195..d79cbc55064a 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -29,6 +29,7 @@ properties:
- fsl,imx8mp-pcie
- fsl,imx8mm-pcie-ep
- fsl,imx8mq-pcie-ep
+ - fsl,imx8mp-pcie-ep
reg:
items:
--
2.25.1
Add i.MX8MQ PCIe endpoint mode compatible string.
Signed-off-by: Richard Zhu <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index e4038e2b3de9..114e11b62195 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -28,6 +28,7 @@ properties:
- fsl,imx8mm-pcie
- fsl,imx8mp-pcie
- fsl,imx8mm-pcie-ep
+ - fsl,imx8mq-pcie-ep
reg:
items:
--
2.25.1
Add i.MX8MP PCIe EP support on EVK board.
Signed-off-by: Richard Zhu <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 9f1469db554d..6daaa5ddc6b6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -390,6 +390,19 @@ &pcie {
status = "okay";
};
+&pcie_ep{
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_PCIE_ROOT>,
+ <&clk IMX8MP_CLK_HSIO_AXI>;
+ clock-names = "pcie", "pcie_aux", "pcie_bus";
+ assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
+ assigned-clock-rates = <10000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
+ status = "disabled";
+};
+
&snvs_pwrkey {
status = "okay";
};
--
2.25.1
Add i.MX8MM PCIe EP support on EVK board.
Signed-off-by: Richard Zhu <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 7d6317d95b13..d43eb2eb23bf 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -380,6 +380,20 @@ &sai2 {
status = "okay";
};
+&pcie0_ep{
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&pcie0_refclk>;
+ clock-names = "pcie", "pcie_aux", "pcie_bus";
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&clk IMX8MM_CLK_PCIE1_CTRL>;
+ assigned-clock-rates = <10000000>, <250000000>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+ <&clk IMX8MM_SYS_PLL2_250M>;
+ status = "disabled";
+};
+
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
--
2.25.1
Set the DEVICE_ID of i.MX8 PCIe and add i.MX8 PCIE EP device support in
pci_endpoint_test driver.
Signed-off-by: Richard Zhu <[email protected]>
---
drivers/misc/pci_endpoint_test.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 11530b4ec389..e2687229955d 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -72,6 +72,7 @@
#define PCI_DEVICE_ID_TI_J7200 0xb00f
#define PCI_DEVICE_ID_TI_AM64 0xb010
#define PCI_DEVICE_ID_LS1088A 0x80c0
+#define PCI_DEVICE_ID_IMX8 0x0808
#define is_am654_pci_dev(pdev) \
((pdev)->device == PCI_DEVICE_ID_TI_AM654)
@@ -980,6 +981,7 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0),
.driver_data = (kernel_ulong_t)&default_data,
},
+ { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_IMX8),},
{ PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_LS1088A),
.driver_data = (kernel_ulong_t)&default_data,
},
--
2.25.1
Add i.MX8MP PCIe EP support.
Signed-off-by: Richard Zhu <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index bb916a0948a8..53d376e14b88 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1192,6 +1192,25 @@ pcie: pcie@33800000 {
status = "disabled";
};
+ pcie_ep: pcie_ep@33800000 {
+ compatible = "fsl,imx8mp-pcie-ep";
+ reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
+ reg-names = "regs", "addr_space";
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+ interrupt-names = "dma";
+ fsl,max-link-speed = <3>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
+ resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "apps", "turnoff";
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+ num-ib-windows = <4>;
+ num-ob-windows = <4>;
+ status = "disabled";
+ };
+
gpu3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;
--
2.25.1
i.MX PCIe is one dual mode PCIe controller.
Add i.MX PCIe EP mode support here, and split the PCIe modes to the Root
Complex mode and Endpoint mode.
Signed-off-by: Richard Zhu <[email protected]>
---
drivers/pci/controller/dwc/Kconfig | 23 ++++-
drivers/pci/controller/dwc/pci-imx6.c | 128 +++++++++++++++++++++++---
2 files changed, 137 insertions(+), 14 deletions(-)
diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
index 62ce3abf0f19..83580c92d216 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -92,10 +92,31 @@ config PCI_EXYNOS
functions to implement the driver.
config PCI_IMX6
- bool "Freescale i.MX6/7/8 PCIe controller"
+ bool
+
+config PCI_IMX6_HOST
+ bool "Freescale i.MX6/7/8 PCIe controller host mode"
depends on ARCH_MXC || COMPILE_TEST
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_DW_HOST
+ select PCI_IMX6
+ help
+ Enables support for the PCIe controller in the i.MX SoCs to
+ work in Root Complex mode. The PCI controller on i.MX is based
+ on DesignWare hardware and therefore the driver re-uses the
+ DesignWare core functions to implement the driver.
+
+config PCI_IMX6_EP
+ bool "Freescale i.MX6/7/8 PCIe controller endpoint mode"
+ depends on ARCH_MXC || COMPILE_TEST
+ depends on PCI_ENDPOINT
+ select PCIE_DW_EP
+ select PCI_IMX6
+ help
+ Enables support for the PCIe controller in the i.MX SoCs to
+ work in endpoint mode. The PCI controller on i.MX is based
+ on DesignWare hardware and therefore the driver re-uses the
+ DesignWare core functions to implement the driver.
config PCIE_SPEAR13XX
bool "STMicroelectronics SPEAr PCIe controller"
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 2616585ca5f8..31467a31128a 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -60,6 +60,7 @@ enum imx6_pcie_variants {
struct imx6_pcie_drvdata {
enum imx6_pcie_variants variant;
+ enum dw_pcie_device_mode mode;
u32 flags;
int dbi_length;
const char *gpr;
@@ -159,17 +160,20 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
{
- unsigned int mask, val;
+ unsigned int mask, val, mode;
+
+ if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE)
+ mode = PCI_EXP_TYPE_ENDPOINT;
+ else
+ mode = PCI_EXP_TYPE_ROOT_PORT;
if (imx6_pcie->drvdata->variant == IMX8MQ &&
imx6_pcie->controller_id == 1) {
mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
- val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
- PCI_EXP_TYPE_ROOT_PORT);
+ val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, mode);
} else {
mask = IMX6Q_GPR12_DEVICE_TYPE;
- val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE,
- PCI_EXP_TYPE_ROOT_PORT);
+ val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode);
}
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
@@ -1002,8 +1006,99 @@ static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
static const struct dw_pcie_ops dw_pcie_ops = {
.start_link = imx6_pcie_start_link,
+ .stop_link = imx6_pcie_stop_link,
+};
+
+static void imx6_pcie_ep_init(struct dw_pcie_ep *ep)
+{
+ enum pci_barno bar;
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+ for (bar = BAR_0; bar <= BAR_5; bar++)
+ dw_pcie_ep_reset_bar(pci, bar);
+}
+
+static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
+ enum pci_epc_irq_type type,
+ u16 interrupt_num)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+ switch (type) {
+ case PCI_EPC_IRQ_LEGACY:
+ return dw_pcie_ep_raise_legacy_irq(ep, func_no);
+ case PCI_EPC_IRQ_MSI:
+ return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
+ case PCI_EPC_IRQ_MSIX:
+ return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
+ default:
+ dev_err(pci->dev, "UNKNOWN IRQ type\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct pci_epc_features imx8m_pcie_epc_features = {
+ .linkup_notifier = false,
+ .msi_capable = true,
+ .msix_capable = false,
+ .reserved_bar = 1 << BAR_1 | 1 << BAR_3,
+ .align = SZ_64K,
+};
+
+static const struct pci_epc_features*
+imx6_pcie_ep_get_features(struct dw_pcie_ep *ep)
+{
+ return &imx8m_pcie_epc_features;
+}
+
+static const struct dw_pcie_ep_ops pcie_ep_ops = {
+ .ep_init = imx6_pcie_ep_init,
+ .raise_irq = imx6_pcie_ep_raise_irq,
+ .get_features = imx6_pcie_ep_get_features,
};
+static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
+ struct platform_device *pdev)
+{
+ int ret;
+ unsigned int pcie_dbi2_offset;
+ struct dw_pcie_ep *ep;
+ struct resource *res;
+ struct dw_pcie *pci = imx6_pcie->pci;
+ struct dw_pcie_rp *pp = &pci->pp;
+ struct device *dev = pci->dev;
+
+ imx6_pcie_host_init(pp);
+ ep = &pci->ep;
+ ep->ops = &pcie_ep_ops;
+
+ switch (imx6_pcie->drvdata->variant) {
+ default:
+ pcie_dbi2_offset = SZ_4K;
+ break;
+ }
+ pci->dbi_base2 = pci->dbi_base + pcie_dbi2_offset;
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
+ if (!res)
+ return -EINVAL;
+
+ ep->phys_base = res->start;
+ ep->addr_size = resource_size(res);
+ ep->page_size = SZ_64K;
+
+ ret = dw_pcie_ep_init(ep);
+ if (ret) {
+ dev_err(dev, "failed to initialize endpoint\n");
+ return ret;
+ }
+ /* Start LTSSM. */
+ imx6_pcie_ltssm_enable(dev);
+
+ return 0;
+}
+
static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
{
struct device *dev = imx6_pcie->pci->dev;
@@ -1278,15 +1373,22 @@ static int imx6_pcie_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = dw_pcie_host_init(&pci->pp);
- if (ret < 0)
- return ret;
+ if (imx6_pcie->drvdata->mode == DW_PCIE_EP_TYPE) {
+ ret = imx6_add_pcie_ep(imx6_pcie, pdev);
+ if (ret < 0)
+ return ret;
+ } else {
+ ret = dw_pcie_host_init(&pci->pp);
+ if (ret < 0)
+ return ret;
+
+ if (pci_msi_enabled()) {
+ u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
- if (pci_msi_enabled()) {
- u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
- val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
- val |= PCI_MSI_FLAGS_ENABLE;
- dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
+ val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
+ val |= PCI_MSI_FLAGS_ENABLE;
+ dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
+ }
}
return 0;
--
2.25.1
Add i.MX8MQ PCIe EP support.
Signed-off-by: Richard Zhu <[email protected]>
---
drivers/pci/controller/dwc/pci-imx6.c | 38 +++++++++++++++++++++++----
1 file changed, 33 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 31467a31128a..f40b23c7f3cb 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -52,6 +52,7 @@ enum imx6_pcie_variants {
IMX8MQ,
IMX8MM,
IMX8MP,
+ IMX8MQ_EP,
};
#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
@@ -153,6 +154,7 @@ struct imx6_pcie {
static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
{
WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ &&
+ imx6_pcie->drvdata->variant != IMX8MQ_EP &&
imx6_pcie->drvdata->variant != IMX8MM &&
imx6_pcie->drvdata->variant != IMX8MP);
return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
@@ -167,13 +169,22 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
else
mode = PCI_EXP_TYPE_ROOT_PORT;
- if (imx6_pcie->drvdata->variant == IMX8MQ &&
- imx6_pcie->controller_id == 1) {
- mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
- val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, mode);
- } else {
+ switch (imx6_pcie->drvdata->variant) {
+ case IMX8MQ:
+ case IMX8MQ_EP:
+ if (imx6_pcie->controller_id == 1) {
+ mask = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
+ val = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
+ mode);
+ } else {
+ mask = IMX6Q_GPR12_DEVICE_TYPE;
+ val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode);
+ }
+ break;
+ default:
mask = IMX6Q_GPR12_DEVICE_TYPE;
val = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE, mode);
+ break;
}
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
@@ -315,6 +326,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
*/
break;
case IMX8MQ:
+ case IMX8MQ_EP:
/*
* TODO: Currently this code assumes external
* oscillator is being used
@@ -566,6 +578,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
break;
case IMX8MM:
case IMX8MQ:
+ case IMX8MQ_EP:
case IMX8MP:
ret = clk_prepare_enable(imx6_pcie->pcie_aux);
if (ret) {
@@ -611,6 +624,7 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
break;
case IMX8MM:
case IMX8MQ:
+ case IMX8MQ_EP:
case IMX8MP:
clk_disable_unprepare(imx6_pcie->pcie_aux);
break;
@@ -676,6 +690,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
switch (imx6_pcie->drvdata->variant) {
case IMX7D:
case IMX8MQ:
+ case IMX8MQ_EP:
reset_control_assert(imx6_pcie->pciephy_reset);
fallthrough;
case IMX8MM:
@@ -717,6 +732,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
switch (imx6_pcie->drvdata->variant) {
case IMX8MQ:
+ case IMX8MQ_EP:
reset_control_deassert(imx6_pcie->pciephy_reset);
break;
case IMX7D:
@@ -804,6 +820,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
break;
case IMX7D:
case IMX8MQ:
+ case IMX8MQ_EP:
case IMX8MM:
case IMX8MP:
reset_control_deassert(imx6_pcie->apps_reset);
@@ -824,6 +841,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
break;
case IMX7D:
case IMX8MQ:
+ case IMX8MQ_EP:
case IMX8MM:
case IMX8MP:
reset_control_assert(imx6_pcie->apps_reset);
@@ -1075,6 +1093,9 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
ep->ops = &pcie_ep_ops;
switch (imx6_pcie->drvdata->variant) {
+ case IMX8MQ_EP:
+ pcie_dbi2_offset = SZ_1M;
+ break;
default:
pcie_dbi2_offset = SZ_4K;
break;
@@ -1260,6 +1281,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
"pcie_inbound_axi clock missing or invalid\n");
break;
case IMX8MQ:
+ case IMX8MQ_EP:
imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
if (IS_ERR(imx6_pcie->pcie_aux))
return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
@@ -1444,6 +1466,11 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
.gpr = "fsl,imx8mp-iomuxc-gpr",
},
+ [IMX8MQ_EP] = {
+ .variant = IMX8MQ_EP,
+ .mode = DW_PCIE_EP_TYPE,
+ .gpr = "fsl,imx8mq-iomuxc-gpr",
+ },
};
static const struct of_device_id imx6_pcie_of_match[] = {
@@ -1454,6 +1481,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
+ { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
{},
};
--
2.25.1
Add i.MX8MM PCIe EP support.
Signed-off-by: Richard Zhu <[email protected]>
---
drivers/pci/controller/dwc/pci-imx6.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index f40b23c7f3cb..3f01cf3776ec 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -53,6 +53,7 @@ enum imx6_pcie_variants {
IMX8MM,
IMX8MP,
IMX8MQ_EP,
+ IMX8MM_EP,
};
#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
@@ -156,6 +157,7 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ &&
imx6_pcie->drvdata->variant != IMX8MQ_EP &&
imx6_pcie->drvdata->variant != IMX8MM &&
+ imx6_pcie->drvdata->variant != IMX8MM_EP &&
imx6_pcie->drvdata->variant != IMX8MP);
return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
}
@@ -319,6 +321,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
{
switch (imx6_pcie->drvdata->variant) {
case IMX8MM:
+ case IMX8MM_EP:
case IMX8MP:
/*
* The PHY initialization had been done in the PHY
@@ -577,6 +580,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
case IMX7D:
break;
case IMX8MM:
+ case IMX8MM_EP:
case IMX8MQ:
case IMX8MQ_EP:
case IMX8MP:
@@ -623,6 +627,7 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
break;
case IMX8MM:
+ case IMX8MM_EP:
case IMX8MQ:
case IMX8MQ_EP:
case IMX8MP:
@@ -694,6 +699,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
reset_control_assert(imx6_pcie->pciephy_reset);
fallthrough;
case IMX8MM:
+ case IMX8MM_EP:
case IMX8MP:
reset_control_assert(imx6_pcie->apps_reset);
break;
@@ -771,6 +777,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
break;
case IMX6Q: /* Nothing to do */
case IMX8MM:
+ case IMX8MM_EP:
case IMX8MP:
break;
}
@@ -822,6 +829,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
case IMX8MQ:
case IMX8MQ_EP:
case IMX8MM:
+ case IMX8MM_EP:
case IMX8MP:
reset_control_deassert(imx6_pcie->apps_reset);
break;
@@ -843,6 +851,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
case IMX8MQ:
case IMX8MQ_EP:
case IMX8MM:
+ case IMX8MM_EP:
case IMX8MP:
reset_control_assert(imx6_pcie->apps_reset);
break;
@@ -1094,6 +1103,7 @@ static int imx6_add_pcie_ep(struct imx6_pcie *imx6_pcie,
switch (imx6_pcie->drvdata->variant) {
case IMX8MQ_EP:
+ case IMX8MM_EP:
pcie_dbi2_offset = SZ_1M;
break;
default:
@@ -1306,6 +1316,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
}
break;
case IMX8MM:
+ case IMX8MM_EP:
case IMX8MP:
imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
if (IS_ERR(imx6_pcie->pcie_aux))
@@ -1471,6 +1482,11 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.mode = DW_PCIE_EP_TYPE,
.gpr = "fsl,imx8mq-iomuxc-gpr",
},
+ [IMX8MM_EP] = {
+ .variant = IMX8MM_EP,
+ .mode = DW_PCIE_EP_TYPE,
+ .gpr = "fsl,imx8mm-iomuxc-gpr",
+ },
};
static const struct of_device_id imx6_pcie_of_match[] = {
@@ -1482,6 +1498,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
{ .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
+ { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
{},
};
--
2.25.1
Add i.MX8MQ PCIe EP support on EVK board.
Signed-off-by: Richard Zhu <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index 82387b9cb800..9f3bad9b49a6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -377,6 +377,18 @@ &pcie1 {
status = "okay";
};
+&pcie1_ep {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie1>;
+ clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
+ <&clk IMX8MQ_CLK_PCIE2_AUX>,
+ <&clk IMX8MQ_CLK_PCIE2_PHY>,
+ <&pcie0_refclk>;
+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ vph-supply = <&vgen5_reg>;
+ status = "disabled";
+};
+
&pgc_gpu {
power-supply = <&sw1a_reg>;
};
--
2.25.1
Add i.MX8MM PCIe EP support.
Signed-off-by: Richard Zhu <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index afb90f59c83c..eca7a42ac52a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1291,6 +1291,26 @@ pcie0: pcie@33800000 {
status = "disabled";
};
+ pcie0_ep: pcie_ep@33800000 {
+ compatible = "fsl,imx8mm-pcie-ep";
+ reg = <0x33800000 0x400000>,
+ <0x18000000 0x8000000>;
+ reg-names = "regs", "addr_space";
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma";
+ fsl,max-link-speed = <2>;
+ power-domains = <&pgc_pcie>;
+ resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "apps", "turnoff";
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+ num-ib-windows = <4>;
+ num-ob-windows = <4>;
+ status = "disabled";
+ };
+
gpu_3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;
--
2.25.1
Ping.
Almost one month pass away after this re-send of v4 series.
Any comments?
Thanks.
Best Regards
Richard Zhu
> -----Original Message-----
> From: Richard Zhu <[email protected]>
> Sent: 2022??10??24?? 16:06
> To: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; Frank Li <[email protected]>
> Cc: Hongxing Zhu <[email protected]>; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; dl-linux-imx
> <[email protected]>
> Subject: [PATCH v4 0/14] Add i.MX PCIe EP mode support
>
> i.MX PCIe controller is one dual mode PCIe controller, and can work either as
> RC or EP.
>
> This series add the i.MX PCIe EP mode support. And had been verified on
> i.MX8MQ, i.MX8MM EVK and i.MX8MP EVK boards.
>
> In the verification, one EVK board used as RC, the other one used as EP.
> Use the cross TX/RX differential cable connect the two PCIe ports of these two
> EVK boards.
>
> +-----------+ +------------+
> | PCIe TX |<-------------->|PCIe RX |
> | | | |
> |EVK Board | |EVK Board |
> | | | |
> | PCIe RX |<-------------->|PCIe TX |
> +-----------+ +------------+
>
> NOTE:
> Re-base to 6.1-rc1, and re-send the v4 series.
> BTW, the following PHY changes [1] is required when apply this series.
>
> [1]
> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchw
> ork.kernel.org%2Fproject%2Flinux-pci%2Fcover%2F1665625622-20551-1-git-s
> end-email-hongxing.zhu%40nxp.com%2F&data=05%7C01%7Chongxing.z
> hu%40nxp.com%7C80b50b3789f9433f62e008dab5998a09%7C686ea1d3bc2b
> 4c6fa92cd99c5c301635%7C0%7C0%7C638021968298265067%7CUnknown%
> 7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwi
> LCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=j70ORNKBvTCjWtJzS375
> TvuQfCGrVRQNbxS%2BhrGI0ZA%3D&reserved=0
>
> Main changes from v3 -> v4:
> - Add the Rob's ACK in the dt-binding patch.
> - Use "i.MX" to keep spell consistent.
> - Squash generic endpoint infrastructure changes of
> "[12/14] PCI: imx6: Add iMX8MM PCIe EP mode" into Kconfig changes.
>
> Main changes from v2 -> v3:
> - Add the i.MX8MP PCIe EP support, and verified on i.MX8MP EVK board.
> - Rebase to latest pci/next branch(tag: v6.0-rc1 plus some PCIe changes).
>
> Main changes from v1 -> v2:
> - Add Rob's ACK into first two commits.
> - Rebase to the tag: pci-v5.20-changes of the pci/next branch.
>
> Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 3 ++
> arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 14 ++++++
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 20
> +++++++++
> arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 13 ++++++
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 19
> ++++++++
> arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 12 ++++++
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 27
> ++++++++++++
> drivers/misc/pci_endpoint_test.c | 2 +
> drivers/pci/controller/dwc/Kconfig | 23
> +++++++++-
> drivers/pci/controller/dwc/pci-imx6.c | 200
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> ++++++++++++++++--------
> 10 files changed, 314 insertions(+), 19 deletions(-)
>
> [RESEND v4 01/14] dt-bindings: imx6q-pcie: Add i.MX8MM PCIe EP mode
> [RESEND v4 02/14] dt-bindings: imx6q-pcie: Add i.MX8MQ PCIe EP mode
> [RESEND v4 03/14] dt-bindings: imx6q-pcie: Add i.MX8MP PCIe EP mode
> [RESEND v4 04/14] arm64: dts: Add i.MX8MM PCIe EP support [RESEND v4
> 05/14] arm64: dts: Add i.MX8MM PCIe EP support on EVK [RESEND v4 06/14]
> arm64: dts: Add i.MX8MQ PCIe EP support [RESEND v4 07/14] arm64: dts:
> Add i.MX8MQ PCIe EP support on EVK [RESEND v4 08/14] arm64: dts: Add
> i.MX8MP PCIe EP support [RESEND v4 09/14] arm64: dts: Add i.MX8MP PCIe
> EP support on EVK [RESEND v4 10/14] misc: pci_endpoint_test: Add i.MX8
> PCIe EP device [RESEND v4 11/14] PCI: imx6: Add i.MX PCIe EP mode support
> [RESEND v4 12/14] PCI: imx6: Add i.MX8MQ PCIe EP support [RESEND v4
> 13/14] PCI: imx6: Add i.MX8MM PCIe EP support [RESEND v4 14/14] PCI: imx6:
> Add i.MX8MP PCIe EP support
On Tue, Nov 15, 2022 at 04:42:30AM +0000, Hongxing Zhu wrote:
> Ping.
> Almost one month pass away after this re-send of v4 series.
> Any comments?
Can you rebase on top of v6.2-rc1 and resend it please ? I will merge
the dt bindings and PCI changes then.
Thanks,
Lorenzo
> Thanks.
> Best Regards
> Richard Zhu
>
> > -----Original Message-----
> > From: Richard Zhu <[email protected]>
> > Sent: 2022年10月24日 16:06
> > To: [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected];
> > [email protected]; Frank Li <[email protected]>
> > Cc: Hongxing Zhu <[email protected]>; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected]; dl-linux-imx
> > <[email protected]>
> > Subject: [PATCH v4 0/14] Add i.MX PCIe EP mode support
> >
> > i.MX PCIe controller is one dual mode PCIe controller, and can work either as
> > RC or EP.
> >
> > This series add the i.MX PCIe EP mode support. And had been verified on
> > i.MX8MQ, i.MX8MM EVK and i.MX8MP EVK boards.
> >
> > In the verification, one EVK board used as RC, the other one used as EP.
> > Use the cross TX/RX differential cable connect the two PCIe ports of these two
> > EVK boards.
> >
> > +-----------+ +------------+
> > | PCIe TX |<-------------->|PCIe RX |
> > | | | |
> > |EVK Board | |EVK Board |
> > | | | |
> > | PCIe RX |<-------------->|PCIe TX |
> > +-----------+ +------------+
> >
> > NOTE:
> > Re-base to 6.1-rc1, and re-send the v4 series.
> > BTW, the following PHY changes [1] is required when apply this series.
> >
> > [1]
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchw
> > ork.kernel.org%2Fproject%2Flinux-pci%2Fcover%2F1665625622-20551-1-git-s
> > end-email-hongxing.zhu%40nxp.com%2F&data=05%7C01%7Chongxing.z
> > hu%40nxp.com%7C80b50b3789f9433f62e008dab5998a09%7C686ea1d3bc2b
> > 4c6fa92cd99c5c301635%7C0%7C0%7C638021968298265067%7CUnknown%
> > 7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwi
> > LCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=j70ORNKBvTCjWtJzS375
> > TvuQfCGrVRQNbxS%2BhrGI0ZA%3D&reserved=0
> >
> > Main changes from v3 -> v4:
> > - Add the Rob's ACK in the dt-binding patch.
> > - Use "i.MX" to keep spell consistent.
> > - Squash generic endpoint infrastructure changes of
> > "[12/14] PCI: imx6: Add iMX8MM PCIe EP mode" into Kconfig changes.
> >
> > Main changes from v2 -> v3:
> > - Add the i.MX8MP PCIe EP support, and verified on i.MX8MP EVK board.
> > - Rebase to latest pci/next branch(tag: v6.0-rc1 plus some PCIe changes).
> >
> > Main changes from v1 -> v2:
> > - Add Rob's ACK into first two commits.
> > - Rebase to the tag: pci-v5.20-changes of the pci/next branch.
> >
> > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 3 ++
> > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 14 ++++++
> > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 20
> > +++++++++
> > arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 13 ++++++
> > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 19
> > ++++++++
> > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 12 ++++++
> > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 27
> > ++++++++++++
> > drivers/misc/pci_endpoint_test.c | 2 +
> > drivers/pci/controller/dwc/Kconfig | 23
> > +++++++++-
> > drivers/pci/controller/dwc/pci-imx6.c | 200
> > +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > ++++++++++++++++--------
> > 10 files changed, 314 insertions(+), 19 deletions(-)
> >
> > [RESEND v4 01/14] dt-bindings: imx6q-pcie: Add i.MX8MM PCIe EP mode
> > [RESEND v4 02/14] dt-bindings: imx6q-pcie: Add i.MX8MQ PCIe EP mode
> > [RESEND v4 03/14] dt-bindings: imx6q-pcie: Add i.MX8MP PCIe EP mode
> > [RESEND v4 04/14] arm64: dts: Add i.MX8MM PCIe EP support [RESEND v4
> > 05/14] arm64: dts: Add i.MX8MM PCIe EP support on EVK [RESEND v4 06/14]
> > arm64: dts: Add i.MX8MQ PCIe EP support [RESEND v4 07/14] arm64: dts:
> > Add i.MX8MQ PCIe EP support on EVK [RESEND v4 08/14] arm64: dts: Add
> > i.MX8MP PCIe EP support [RESEND v4 09/14] arm64: dts: Add i.MX8MP PCIe
> > EP support on EVK [RESEND v4 10/14] misc: pci_endpoint_test: Add i.MX8
> > PCIe EP device [RESEND v4 11/14] PCI: imx6: Add i.MX PCIe EP mode support
> > [RESEND v4 12/14] PCI: imx6: Add i.MX8MQ PCIe EP support [RESEND v4
> > 13/14] PCI: imx6: Add i.MX8MM PCIe EP support [RESEND v4 14/14] PCI: imx6:
> > Add i.MX8MP PCIe EP support
Hi Lorenzo:
> -----Original Message-----
> From: Lorenzo Pieralisi <[email protected]>
> Sent: 2023??1??14?? 0:17
> To: Hongxing Zhu <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; Frank Li <[email protected]>; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; dl-linux-imx
> <[email protected]>
> Subject: Re: [PATCH v4 0/14] Add i.MX PCIe EP mode support
>
> On Tue, Nov 15, 2022 at 04:42:30AM +0000, Hongxing Zhu wrote:
> > Ping.
> > Almost one month pass away after this re-send of v4 series.
> > Any comments?
>
> Can you rebase on top of v6.2-rc1 and resend it please ? I will merge the dt
> bindings and PCI changes then.
>
Sure, I would send next version after rebase to v6.2-rc1.
Thanks a lot for your kindly help.
Best Regards
Richard Zhu
> Thanks,
> Lorenzo
>
> > Thanks.
> > Best Regards
> > Richard Zhu
> >
> > > -----Original Message-----
> > > From: Richard Zhu <[email protected]>
> > > Sent: 2022??10??24?? 16:06
> > > To: [email protected]; [email protected]; [email protected];
> > > [email protected]; [email protected]; [email protected];
> > > [email protected]; Frank Li <[email protected]>
> > > Cc: Hongxing Zhu <[email protected]>; [email protected];
> > > [email protected]; [email protected];
> > > [email protected]; [email protected]; dl-linux-imx
> > > <[email protected]>
> > > Subject: [PATCH v4 0/14] Add i.MX PCIe EP mode support
> > >
> > > i.MX PCIe controller is one dual mode PCIe controller, and can work
> > > either as RC or EP.
> > >
> > > This series add the i.MX PCIe EP mode support. And had been verified
> > > on i.MX8MQ, i.MX8MM EVK and i.MX8MP EVK boards.
> > >
> > > In the verification, one EVK board used as RC, the other one used as EP.
> > > Use the cross TX/RX differential cable connect the two PCIe ports of
> > > these two EVK boards.
> > >
> > > +-----------+ +------------+
> > > | PCIe TX |<-------------->|PCIe RX |
> > > | | | |
> > > |EVK Board | |EVK Board |
> > > | | | |
> > > | PCIe RX |<-------------->|PCIe TX |
> > > +-----------+ +------------+
> > >
> > > NOTE:
> > > Re-base to 6.1-rc1, and re-send the v4 series.
> > > BTW, the following PHY changes [1] is required when apply this series.
> > >
> > > [1]
> > > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpa
> > >
> tchw%2F&data=05%7C01%7Chongxing.zhu%40nxp.com%7C5ccb28e3920441
> 0c3e76
> > >
> 08daf581a77c%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C6380
> 922344
> > >
> 55286842%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoi
> V2luMzI
> > >
> iLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=7F00u1UU
> 7PfxLw
> > > fBrIMPvLvLQT8ZJ6HOwkALiNsBJcI%3D&reserved=0
> > >
> ork.kernel.org%2Fproject%2Flinux-pci%2Fcover%2F1665625622-20551-1-gi
> > > t-s
> > >
> end-email-hongxing.zhu%40nxp.com%2F&data=05%7C01%7Chongxing.z
> > >
> hu%40nxp.com%7C80b50b3789f9433f62e008dab5998a09%7C686ea1d3bc2b
> > >
> 4c6fa92cd99c5c301635%7C0%7C0%7C638021968298265067%7CUnknown%
> > >
> 7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwi
> > >
> LCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=j70ORNKBvTCjWtJzS375
> > > TvuQfCGrVRQNbxS%2BhrGI0ZA%3D&reserved=0
> > >
> > > Main changes from v3 -> v4:
> > > - Add the Rob's ACK in the dt-binding patch.
> > > - Use "i.MX" to keep spell consistent.
> > > - Squash generic endpoint infrastructure changes of
> > > "[12/14] PCI: imx6: Add iMX8MM PCIe EP mode" into Kconfig changes.
> > >
> > > Main changes from v2 -> v3:
> > > - Add the i.MX8MP PCIe EP support, and verified on i.MX8MP EVK board.
> > > - Rebase to latest pci/next branch(tag: v6.0-rc1 plus some PCIe changes).
> > >
> > > Main changes from v1 -> v2:
> > > - Add Rob's ACK into first two commits.
> > > - Rebase to the tag: pci-v5.20-changes of the pci/next branch.
> > >
> > > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 3 ++
> > > arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 14
> ++++++
> > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 20
> > > +++++++++
> > > arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 13
> ++++++
> > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 19
> > > ++++++++
> > > arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 12
> ++++++
> > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 27
> > > ++++++++++++
> > > drivers/misc/pci_endpoint_test.c | 2 +
> > > drivers/pci/controller/dwc/Kconfig | 23
> > > +++++++++-
> > > drivers/pci/controller/dwc/pci-imx6.c | 200
> > >
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> > > ++++++++++++++++--------
> > > 10 files changed, 314 insertions(+), 19 deletions(-)
> > >
> > > [RESEND v4 01/14] dt-bindings: imx6q-pcie: Add i.MX8MM PCIe EP mode
> > > [RESEND v4 02/14] dt-bindings: imx6q-pcie: Add i.MX8MQ PCIe EP mode
> > > [RESEND v4 03/14] dt-bindings: imx6q-pcie: Add i.MX8MP PCIe EP mode
> > > [RESEND v4 04/14] arm64: dts: Add i.MX8MM PCIe EP support [RESEND v4
> > > 05/14] arm64: dts: Add i.MX8MM PCIe EP support on EVK [RESEND v4
> > > 06/14]
> > > arm64: dts: Add i.MX8MQ PCIe EP support [RESEND v4 07/14] arm64: dts:
> > > Add i.MX8MQ PCIe EP support on EVK [RESEND v4 08/14] arm64: dts: Add
> > > i.MX8MP PCIe EP support [RESEND v4 09/14] arm64: dts: Add i.MX8MP
> > > PCIe EP support on EVK [RESEND v4 10/14] misc: pci_endpoint_test:
> > > Add i.MX8 PCIe EP device [RESEND v4 11/14] PCI: imx6: Add i.MX PCIe
> > > EP mode support [RESEND v4 12/14] PCI: imx6: Add i.MX8MQ PCIe EP
> > > support [RESEND v4 13/14] PCI: imx6: Add i.MX8MM PCIe EP support
> [RESEND v4 14/14] PCI: imx6:
> > > Add i.MX8MP PCIe EP support