Hi,
Correct the number of GPIOs in TLMM pin controller.
I really hope I got it right... The last number of gpio-ranges is the number of
GPIOs. See: Documentation/devicetree/bindings/gpio/gpio.txt
The examples in bindings were fixed here:
https://lore.kernel.org/linux-arm-msm/[email protected]/T/#t
Not realy tested, but I do not expect troubles, unless I missed some obvious
stuff (like a number in pinctrl driver).
Best regards,
Krzysztof
Krzysztof Kozlowski (14):
ARM: dts: qcom: sdx55: correct TLMM gpio-ranges
ARM: dts: qcom: sdx65: correct TLMM gpio-ranges
arm64: dts: qcom: msm8953: correct TLMM gpio-ranges
arm64: dts: qcom: sc7180: correct TLMM gpio-ranges
arm64: dts: qcom: sc8280xp: correct TLMM gpio-ranges
arm64: dts: qcom: sdm670: correct TLMM gpio-ranges
arm64: dts: qcom: sdm845: correct TLMM gpio-ranges
arm64: dts: qcom: sm6115: correct TLMM gpio-ranges
arm64: dts: qcom: sm6125: correct TLMM gpio-ranges
arm64: dts: qcom: sm6350: correct TLMM gpio-ranges
arm64: dts: qcom: sm6375: correct TLMM gpio-ranges
arm64: dts: qcom: sm8150: correct TLMM gpio-ranges
arm64: dts: qcom: sm8450: correct TLMM gpio-ranges
arm64: dts: qcom: sm8550: correct TLMM gpio-ranges
arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +-
arch/arm/boot/dts/qcom-sdx65.dtsi | 2 +-
arch/arm64/boot/dts/qcom/msm8953.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm670.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm6375.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +-
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
14 files changed, 14 insertions(+), 14 deletions(-)
--
2.34.1
Correct the number of GPIOs in TLMM pin controller.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
index a9433d1e4f54..f1553e1e40db 100644
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -560,7 +560,7 @@ tlmm: pinctrl@f100000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- gpio-ranges = <&tlmm 0 0 109>;
+ gpio-ranges = <&tlmm 0 0 108>;
};
sram@1468f000 {
--
2.34.1
Correct the number of GPIOs in TLMM pin controller.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm/boot/dts/qcom-sdx65.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
index 619cafb6d9b3..13f98197141d 100644
--- a/arch/arm/boot/dts/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
@@ -427,7 +427,7 @@ tlmm: pinctrl@f100000 {
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&tlmm 0 0 109>;
+ gpio-ranges = <&tlmm 0 0 108>;
interrupt-controller;
interrupt-parent = <&intc>;
#interrupt-cells = <2>;
--
2.34.1
Correct the number of GPIOs in TLMM pin controller.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/msm8953.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index 4e17bc9f8167..610f3e3fc0c2 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -399,7 +399,7 @@ tlmm: pinctrl@1000000 {
reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
- gpio-ranges = <&tlmm 0 0 155>;
+ gpio-ranges = <&tlmm 0 0 142>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
--
2.34.1
Correct the number of GPIOs in TLMM pin controller.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index ebfa21e9ed8a..f1ce996bc10e 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1512,7 +1512,7 @@ tlmm: pinctrl@3500000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- gpio-ranges = <&tlmm 0 0 120>;
+ gpio-ranges = <&tlmm 0 0 119>;
wakeup-parent = <&pdc>;
dp_hot_plug_det: dp-hot-plug-det-state {
--
2.34.1
Correct the number of GPIOs in TLMM pin controller.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index fa2d0d7d1367..17e8c26a9ae6 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -3533,7 +3533,7 @@ tlmm: pinctrl@f100000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- gpio-ranges = <&tlmm 0 0 230>;
+ gpio-ranges = <&tlmm 0 0 228>;
};
apps_smmu: iommu@15000000 {
--
2.34.1
Correct the number of GPIOs in TLMM pin controller.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sdm670.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm670.dtsi b/arch/arm64/boot/dts/qcom/sdm670.dtsi
index ec9946e5f08d..b4c2b6dc1574 100644
--- a/arch/arm64/boot/dts/qcom/sdm670.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm670.dtsi
@@ -796,7 +796,7 @@ tlmm: pinctrl@3400000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- gpio-ranges = <&tlmm 0 0 151>;
+ gpio-ranges = <&tlmm 0 0 150>;
qup_i2c0_default: qup-i2c0-default-state {
pins = "gpio0", "gpio1";
--
2.34.1
Correct the number of GPIOs in TLMM pin controller.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 9ffc0fe07c21..488aab3db294 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2704,7 +2704,7 @@ tlmm: pinctrl@3400000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- gpio-ranges = <&tlmm 0 0 151>;
+ gpio-ranges = <&tlmm 0 0 150>;
wakeup-parent = <&pdc_intc>;
cci0_default: cci0-default-state {
--
2.34.1
Correct the number of GPIOs in TLMM pin controller.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 50cb8a82ecd5..d1bfd264c2d3 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -363,7 +363,7 @@ tlmm: pinctrl@500000 {
reg-names = "west", "south", "east";
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
- gpio-ranges = <&tlmm 0 0 121>;
+ gpio-ranges = <&tlmm 0 0 113>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
--
2.34.1
Correct the number of GPIOs in TLMM pin controller.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 65033227718a..1b7bbef5c575 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -384,7 +384,7 @@ tlmm: pinctrl@500000 {
reg-names = "west", "south", "east";
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
- gpio-ranges = <&tlmm 0 0 134>;
+ gpio-ranges = <&tlmm 0 0 133>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
--
2.34.1
Correct the number of GPIOs in TLMM pin controller.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 8224adb99948..317ed9bd3507 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -1511,7 +1511,7 @@ tlmm: pinctrl@f100000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- gpio-ranges = <&tlmm 0 0 157>;
+ gpio-ranges = <&tlmm 0 0 156>;
sdc2_off_state: sdc2-off-state {
clk-pins {
--
2.34.1
Correct the number of GPIOs in TLMM pin controller.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6375.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
index 31b88c738510..0e161c301804 100644
--- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
@@ -581,7 +581,7 @@ tlmm: pinctrl@500000 {
compatible = "qcom,sm6375-tlmm";
reg = <0 0x00500000 0 0x800000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
- gpio-ranges = <&tlmm 0 0 157>;
+ gpio-ranges = <&tlmm 0 0 156>;
/* TODO: Hook up MPM as wakeup-parent when it's there */
interrupt-controller;
gpio-controller;
--
2.34.1
Correct the number of GPIOs in TLMM pin controller.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index fd20096cfc6e..4cd0aa314140 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -2278,7 +2278,7 @@ tlmm: pinctrl@3100000 {
<0x0 0x03D00000 0x0 0x300000>;
reg-names = "west", "east", "north", "south";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
- gpio-ranges = <&tlmm 0 0 176>;
+ gpio-ranges = <&tlmm 0 0 175>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
--
2.34.1
Correct the number of GPIOs in TLMM pin controller.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 6ff135191ee0..24c7e3378b9d 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -2546,7 +2546,7 @@ tlmm: pinctrl@f000000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- gpio-ranges = <&tlmm 0 0 211>;
+ gpio-ranges = <&tlmm 0 0 210>;
wakeup-parent = <&pdc>;
hub_i2c0_data_clk: hub-i2c0-data-clk-state {
--
2.34.1
Correct the number of GPIOs in TLMM pin controller.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index d66dcd8fe61f..7014bdfd0035 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -3073,7 +3073,7 @@ tlmm: pinctrl@f100000 {
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- gpio-ranges = <&tlmm 0 0 211>;
+ gpio-ranges = <&tlmm 0 0 210>;
wakeup-parent = <&pdc>;
sdc2_default_state: sdc2-default-state {
--
2.34.1
On 01/02/2023 16:50, Krzysztof Kozlowski wrote:
> Hi,
>
> Correct the number of GPIOs in TLMM pin controller.
>
> I really hope I got it right... The last number of gpio-ranges is the number of
> GPIOs. See: Documentation/devicetree/bindings/gpio/gpio.txt
>
> The examples in bindings were fixed here:
> https://lore.kernel.org/linux-arm-msm/[email protected]/T/#t
>
> Not realy tested, but I do not expect troubles, unless I missed some obvious
> stuff (like a number in pinctrl driver).
>
As pointed out by Stephan, this is mostly incorrect and needs fixes.
There will be a v2.
Best regards,
Krzysztof
On Wed, Feb 01, 2023 at 04:50:56PM +0100, Krzysztof Kozlowski wrote:
> Correct the number of GPIOs in TLMM pin controller.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index fa2d0d7d1367..17e8c26a9ae6 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -3533,7 +3533,7 @@ tlmm: pinctrl@f100000 {
> #gpio-cells = <2>;
> interrupt-controller;
> #interrupt-cells = <2>;
> - gpio-ranges = <&tlmm 0 0 230>;
> + gpio-ranges = <&tlmm 0 0 228>;
> };
I verified that this count matches what's in downstream.
Reviewed-by: Brian Masney <[email protected]>
However, I noticed in upstream that we're using this reg property:
reg = <0 0x0f100000 0 0x300000>;
Downstream has a different base address and a wider size. Note: I added
spaces for easy comparison.
reg = < 0x0F000000 0x1000000>;
I don't have access to the appropriate documents to see which is
correct. I assume the base address in upstream is at least correct since
pinctrl is working on this platform.
Brian
On 2.02.2023 23:58, Brian Masney wrote:
> On Wed, Feb 01, 2023 at 04:50:56PM +0100, Krzysztof Kozlowski wrote:
>> Correct the number of GPIOs in TLMM pin controller.
>>
>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> index fa2d0d7d1367..17e8c26a9ae6 100644
>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>> @@ -3533,7 +3533,7 @@ tlmm: pinctrl@f100000 {
>> #gpio-cells = <2>;
>> interrupt-controller;
>> #interrupt-cells = <2>;
>> - gpio-ranges = <&tlmm 0 0 230>;
>> + gpio-ranges = <&tlmm 0 0 228>;
Won't that kill the UFS pins?
>> };
>
> I verified that this count matches what's in downstream.
>
> Reviewed-by: Brian Masney <[email protected]>
>
>
> However, I noticed in upstream that we're using this reg property:
>
> reg = <0 0x0f100000 0 0x300000>;
>
> Downstream has a different base address and a wider size. Note: I added
> spaces for easy comparison.
>
> reg = < 0x0F000000 0x1000000>;
>
> I don't have access to the appropriate documents to see which is
> correct. I assume the base address in upstream is at least correct since
> pinctrl is working on this platform.
Downstream offsets things in the driver
https://git.codelinaro.org/clo/la/kernel/msm-5.4/-/blob/LV.AU.1.2.3.r1-03600-gen3meta.0/drivers/pinctrl/qcom/pinctrl-direwolf.c#L20
Notice how UFS/QDSD pins addresses differ by 0x1000... up- and downstream too.
I'd imagine Bjorn/Johan/whoever did that used magic PDFs instead of not-very-
tested downstream sources.
Another note, the downstream driver may be incomplete/wrong, as Linux was
not exactly the main usecase of 8280xp so the testing there was most likely
only basic.
Konrad
>
> Brian
>
On Fri, Feb 03, 2023 at 12:45:49AM +0100, Konrad Dybcio wrote:
> On 2.02.2023 23:58, Brian Masney wrote:
> > On Wed, Feb 01, 2023 at 04:50:56PM +0100, Krzysztof Kozlowski wrote:
> >> Correct the number of GPIOs in TLMM pin controller.
> >>
> >> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> >> ---
> >> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
> >> 1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >> index fa2d0d7d1367..17e8c26a9ae6 100644
> >> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> >> @@ -3533,7 +3533,7 @@ tlmm: pinctrl@f100000 {
> >> #gpio-cells = <2>;
> >> interrupt-controller;
> >> #interrupt-cells = <2>;
> >> - gpio-ranges = <&tlmm 0 0 230>;
> >> + gpio-ranges = <&tlmm 0 0 228>;
> Won't that kill the UFS pins?
For others quick reference, Konrad is talking about this line from
sa8540p-ride.dts:
reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
I noticed that earlier but assumed this was one based. However, looking
at pinctrl-sc8280xp.c I see gpio0..gpio227 defined.
Brian
On 3.02.2023 00:59, Brian Masney wrote:
> On Fri, Feb 03, 2023 at 12:45:49AM +0100, Konrad Dybcio wrote:
>> On 2.02.2023 23:58, Brian Masney wrote:
>>> On Wed, Feb 01, 2023 at 04:50:56PM +0100, Krzysztof Kozlowski wrote:
>>>> Correct the number of GPIOs in TLMM pin controller.
>>>>
>>>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
>>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>>> index fa2d0d7d1367..17e8c26a9ae6 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>>> @@ -3533,7 +3533,7 @@ tlmm: pinctrl@f100000 {
>>>> #gpio-cells = <2>;
>>>> interrupt-controller;
>>>> #interrupt-cells = <2>;
>>>> - gpio-ranges = <&tlmm 0 0 230>;
>>>> + gpio-ranges = <&tlmm 0 0 228>;
>> Won't that kill the UFS pins?
>
> For others quick reference, Konrad is talking about this line from
> sa8540p-ride.dts:
>
> reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
>
> I noticed that earlier but assumed this was one based. However, looking
> at pinctrl-sc8280xp.c I see gpio0..gpio227 defined.
+ gpio229 is the reset pin for the UFS card slot
Konrad
>
> Brian
>
On Fri, Feb 03, 2023 at 01:05:35AM +0100, Konrad Dybcio wrote:
> On 3.02.2023 00:59, Brian Masney wrote:
> > For others quick reference, Konrad is talking about this line from
> > sa8540p-ride.dts:
> >
> > reset-gpios = <&tlmm 228 GPIO_ACTIVE_LOW>;
> >
> > I noticed that earlier but assumed this was one based. However, looking
> > at pinctrl-sc8280xp.c I see gpio0..gpio227 defined.
>
> + gpio229 is the reset pin for the UFS card slot
We don't have the UFS card slot on the sa8540p exposed. However, it is
available on the sa8295p.
The original DTS in upstream listed 230 pins, however pinctrl-sc8280xp.c
lists 233 pins and the two UFS pins match what we have in DTS.
static const struct pinctrl_pin_desc sc8280xp_pins[] = {
PINCTRL_PIN(0, "GPIO_0"),
...
PINCTRL_PIN(227, "GPIO_227"),
PINCTRL_PIN(228, "UFS_RESET"),
PINCTRL_PIN(229, "UFS1_RESET"),
PINCTRL_PIN(230, "SDC2_CLK"),
PINCTRL_PIN(231, "SDC2_CMD"),
PINCTRL_PIN(232, "SDC2_DATA"),
Rescind-Reviewed-by: Brian Masney <[email protected]>
On 03/02/2023 00:45, Konrad Dybcio wrote:
>
>
> On 2.02.2023 23:58, Brian Masney wrote:
>> On Wed, Feb 01, 2023 at 04:50:56PM +0100, Krzysztof Kozlowski wrote:
>>> Correct the number of GPIOs in TLMM pin controller.
>>>
>>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> index fa2d0d7d1367..17e8c26a9ae6 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
>>> @@ -3533,7 +3533,7 @@ tlmm: pinctrl@f100000 {
>>> #gpio-cells = <2>;
>>> interrupt-controller;
>>> #interrupt-cells = <2>;
>>> - gpio-ranges = <&tlmm 0 0 230>;
>>> + gpio-ranges = <&tlmm 0 0 228>;
> Won't that kill the UFS pins?
This patchset is obsolete and replaced with v2. I alerady replied here
that this was not good approach...
Best regards,
Krzysztof