Hi Vinod,
This patch series adds support for the Direct Memory Access Controller
variant in the Renesas R-Car V3U (R8A779A0) SoC, to both DT bindings and
driver.
Changes compared to v1:
- Add Reviewed-by,
- Put the full loop control of for_each_rcar_dmac_chan() on a single
line, to improve readability,
- Use two separate named regions instead of array,
- Drop rcar_dmac_of_data.chan_reg_block, check for
!rcar_dmac_of_data.chan_offset_base instead,
- Precalculate chan_base in rcar_dmac_probe().
This has been tested on the Renesas Falcon board, using external SPI
loopback (spi-loopback-test) on MSIOF1 and MSIOF2.
Thanks!
Geert Uytterhoeven (4):
dt-bindings: renesas,rcar-dmac: Add r8a779a0 support
dmaengine: rcar-dmac: Add for_each_rcar_dmac_chan() helper
dmaengine: rcar-dmac: Add helpers for clearing DMA channel status
dmaengine: rcar-dmac: Add support for R-Car V3U
.../bindings/dma/renesas,rcar-dmac.yaml | 76 ++++++++-----
drivers/dma/sh/rcar-dmac.c | 105 +++++++++++++-----
2 files changed, 123 insertions(+), 58 deletions(-)
--
2.25.1
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
Extract the code to clear the status of one or all channels into their
own helpers, to prepare for the different handling of the R-Car V3U SoC.
Signed-off-by: Geert Uytterhoeven <[email protected]>
---
v2:
- No changes.
---
drivers/dma/sh/rcar-dmac.c | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
index 537550b4121bbc22..7a0f802c61e5152d 100644
--- a/drivers/dma/sh/rcar-dmac.c
+++ b/drivers/dma/sh/rcar-dmac.c
@@ -336,6 +336,17 @@ static void rcar_dmac_chan_write(struct rcar_dmac_chan *chan, u32 reg, u32 data)
writel(data, chan->iomem + reg);
}
+static void rcar_dmac_chan_clear(struct rcar_dmac *dmac,
+ struct rcar_dmac_chan *chan)
+{
+ rcar_dmac_write(dmac, RCAR_DMACHCLR, BIT(chan->index));
+}
+
+static void rcar_dmac_chan_clear_all(struct rcar_dmac *dmac)
+{
+ rcar_dmac_write(dmac, RCAR_DMACHCLR, dmac->channels_mask);
+}
+
/* -----------------------------------------------------------------------------
* Initialization and configuration
*/
@@ -451,7 +462,7 @@ static int rcar_dmac_init(struct rcar_dmac *dmac)
u16 dmaor;
/* Clear all channels and enable the DMAC globally. */
- rcar_dmac_write(dmac, RCAR_DMACHCLR, dmac->channels_mask);
+ rcar_dmac_chan_clear_all(dmac);
rcar_dmac_write(dmac, RCAR_DMAOR,
RCAR_DMAOR_PRI_FIXED | RCAR_DMAOR_DME);
@@ -1566,7 +1577,7 @@ static irqreturn_t rcar_dmac_isr_channel(int irq, void *dev)
* because channel is already stopped in error case.
* We need to clear register and check DE bit as recovery.
*/
- rcar_dmac_write(dmac, RCAR_DMACHCLR, 1 << chan->index);
+ rcar_dmac_chan_clear(dmac, chan);
rcar_dmac_chcr_de_barrier(chan);
reinit = true;
goto spin_lock_end;
--
2.25.1
On Mon, Jan 25, 2021 at 03:24:30PM +0100, Geert Uytterhoeven wrote:
> Extract the code to clear the status of one or all channels into their
> own helpers, to prepare for the different handling of the R-Car V3U SoC.
>
> Signed-off-by: Geert Uytterhoeven <[email protected]>
Looks good and works fine with I2C + DMA on V3U:
Reviewed-by: Wolfram Sang <[email protected]>
Tested-by: Wolfram Sang <[email protected]>
Document the compatible value for the Direct Memory Access Controller
blocks in the Renesas R-Car V3U (R8A779A0) SoC.
The most visible difference with DMAC blocks on other R-Car SoCs is the
move of the per-channel registers to a separate register block.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
v2:
- Add Reviewed-by.
---
.../bindings/dma/renesas,rcar-dmac.yaml | 76 ++++++++++++-------
1 file changed, 48 insertions(+), 28 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml
index c07eb6f2fc8d2f12..7f2a54bc732d3a19 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml
@@ -14,34 +14,37 @@ allOf:
properties:
compatible:
- items:
- - enum:
- - renesas,dmac-r8a7742 # RZ/G1H
- - renesas,dmac-r8a7743 # RZ/G1M
- - renesas,dmac-r8a7744 # RZ/G1N
- - renesas,dmac-r8a7745 # RZ/G1E
- - renesas,dmac-r8a77470 # RZ/G1C
- - renesas,dmac-r8a774a1 # RZ/G2M
- - renesas,dmac-r8a774b1 # RZ/G2N
- - renesas,dmac-r8a774c0 # RZ/G2E
- - renesas,dmac-r8a774e1 # RZ/G2H
- - renesas,dmac-r8a7790 # R-Car H2
- - renesas,dmac-r8a7791 # R-Car M2-W
- - renesas,dmac-r8a7792 # R-Car V2H
- - renesas,dmac-r8a7793 # R-Car M2-N
- - renesas,dmac-r8a7794 # R-Car E2
- - renesas,dmac-r8a7795 # R-Car H3
- - renesas,dmac-r8a7796 # R-Car M3-W
- - renesas,dmac-r8a77961 # R-Car M3-W+
- - renesas,dmac-r8a77965 # R-Car M3-N
- - renesas,dmac-r8a77970 # R-Car V3M
- - renesas,dmac-r8a77980 # R-Car V3H
- - renesas,dmac-r8a77990 # R-Car E3
- - renesas,dmac-r8a77995 # R-Car D3
- - const: renesas,rcar-dmac
-
- reg:
- maxItems: 1
+ oneOf:
+ - items:
+ - enum:
+ - renesas,dmac-r8a7742 # RZ/G1H
+ - renesas,dmac-r8a7743 # RZ/G1M
+ - renesas,dmac-r8a7744 # RZ/G1N
+ - renesas,dmac-r8a7745 # RZ/G1E
+ - renesas,dmac-r8a77470 # RZ/G1C
+ - renesas,dmac-r8a774a1 # RZ/G2M
+ - renesas,dmac-r8a774b1 # RZ/G2N
+ - renesas,dmac-r8a774c0 # RZ/G2E
+ - renesas,dmac-r8a774e1 # RZ/G2H
+ - renesas,dmac-r8a7790 # R-Car H2
+ - renesas,dmac-r8a7791 # R-Car M2-W
+ - renesas,dmac-r8a7792 # R-Car V2H
+ - renesas,dmac-r8a7793 # R-Car M2-N
+ - renesas,dmac-r8a7794 # R-Car E2
+ - renesas,dmac-r8a7795 # R-Car H3
+ - renesas,dmac-r8a7796 # R-Car M3-W
+ - renesas,dmac-r8a77961 # R-Car M3-W+
+ - renesas,dmac-r8a77965 # R-Car M3-N
+ - renesas,dmac-r8a77970 # R-Car V3M
+ - renesas,dmac-r8a77980 # R-Car V3H
+ - renesas,dmac-r8a77990 # R-Car E3
+ - renesas,dmac-r8a77995 # R-Car D3
+ - const: renesas,rcar-dmac
+
+ - items:
+ - const: renesas,dmac-r8a779a0 # R-Car V3U
+
+ reg: true
interrupts:
minItems: 9
@@ -110,6 +113,23 @@ required:
- power-domains
- resets
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,dmac-r8a779a0
+then:
+ properties:
+ reg:
+ items:
+ - description: Base register block
+ - description: Channel register block
+else:
+ properties:
+ reg:
+ maxItems: 1
+
additionalProperties: false
examples:
--
2.25.1
Hi Geert,
Thank you for the patch.
On Mon, Jan 25, 2021 at 03:24:30PM +0100, Geert Uytterhoeven wrote:
> Extract the code to clear the status of one or all channels into their
> own helpers, to prepare for the different handling of the R-Car V3U SoC.
>
> Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
> ---
> v2:
> - No changes.
> ---
> drivers/dma/sh/rcar-dmac.c | 15 +++++++++++++--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/dma/sh/rcar-dmac.c b/drivers/dma/sh/rcar-dmac.c
> index 537550b4121bbc22..7a0f802c61e5152d 100644
> --- a/drivers/dma/sh/rcar-dmac.c
> +++ b/drivers/dma/sh/rcar-dmac.c
> @@ -336,6 +336,17 @@ static void rcar_dmac_chan_write(struct rcar_dmac_chan *chan, u32 reg, u32 data)
> writel(data, chan->iomem + reg);
> }
>
> +static void rcar_dmac_chan_clear(struct rcar_dmac *dmac,
> + struct rcar_dmac_chan *chan)
> +{
> + rcar_dmac_write(dmac, RCAR_DMACHCLR, BIT(chan->index));
> +}
> +
> +static void rcar_dmac_chan_clear_all(struct rcar_dmac *dmac)
> +{
> + rcar_dmac_write(dmac, RCAR_DMACHCLR, dmac->channels_mask);
> +}
> +
> /* -----------------------------------------------------------------------------
> * Initialization and configuration
> */
> @@ -451,7 +462,7 @@ static int rcar_dmac_init(struct rcar_dmac *dmac)
> u16 dmaor;
>
> /* Clear all channels and enable the DMAC globally. */
> - rcar_dmac_write(dmac, RCAR_DMACHCLR, dmac->channels_mask);
> + rcar_dmac_chan_clear_all(dmac);
> rcar_dmac_write(dmac, RCAR_DMAOR,
> RCAR_DMAOR_PRI_FIXED | RCAR_DMAOR_DME);
>
> @@ -1566,7 +1577,7 @@ static irqreturn_t rcar_dmac_isr_channel(int irq, void *dev)
> * because channel is already stopped in error case.
> * We need to clear register and check DE bit as recovery.
> */
> - rcar_dmac_write(dmac, RCAR_DMACHCLR, 1 << chan->index);
> + rcar_dmac_chan_clear(dmac, chan);
> rcar_dmac_chcr_de_barrier(chan);
> reinit = true;
> goto spin_lock_end;
--
Regards,
Laurent Pinchart
Hi Geert,
Thank you for the patch.
On Mon, Jan 25, 2021 at 03:24:28PM +0100, Geert Uytterhoeven wrote:
> Document the compatible value for the Direct Memory Access Controller
> blocks in the Renesas R-Car V3U (R8A779A0) SoC.
>
> The most visible difference with DMAC blocks on other R-Car SoCs is the
> move of the per-channel registers to a separate register block.
>
> Signed-off-by: Geert Uytterhoeven <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
> ---
> v2:
> - Add Reviewed-by.
> ---
> .../bindings/dma/renesas,rcar-dmac.yaml | 76 ++++++++++++-------
> 1 file changed, 48 insertions(+), 28 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml
> index c07eb6f2fc8d2f12..7f2a54bc732d3a19 100644
> --- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml
> @@ -14,34 +14,37 @@ allOf:
>
> properties:
> compatible:
> - items:
> - - enum:
> - - renesas,dmac-r8a7742 # RZ/G1H
> - - renesas,dmac-r8a7743 # RZ/G1M
> - - renesas,dmac-r8a7744 # RZ/G1N
> - - renesas,dmac-r8a7745 # RZ/G1E
> - - renesas,dmac-r8a77470 # RZ/G1C
> - - renesas,dmac-r8a774a1 # RZ/G2M
> - - renesas,dmac-r8a774b1 # RZ/G2N
> - - renesas,dmac-r8a774c0 # RZ/G2E
> - - renesas,dmac-r8a774e1 # RZ/G2H
> - - renesas,dmac-r8a7790 # R-Car H2
> - - renesas,dmac-r8a7791 # R-Car M2-W
> - - renesas,dmac-r8a7792 # R-Car V2H
> - - renesas,dmac-r8a7793 # R-Car M2-N
> - - renesas,dmac-r8a7794 # R-Car E2
> - - renesas,dmac-r8a7795 # R-Car H3
> - - renesas,dmac-r8a7796 # R-Car M3-W
> - - renesas,dmac-r8a77961 # R-Car M3-W+
> - - renesas,dmac-r8a77965 # R-Car M3-N
> - - renesas,dmac-r8a77970 # R-Car V3M
> - - renesas,dmac-r8a77980 # R-Car V3H
> - - renesas,dmac-r8a77990 # R-Car E3
> - - renesas,dmac-r8a77995 # R-Car D3
> - - const: renesas,rcar-dmac
> -
> - reg:
> - maxItems: 1
> + oneOf:
> + - items:
> + - enum:
> + - renesas,dmac-r8a7742 # RZ/G1H
> + - renesas,dmac-r8a7743 # RZ/G1M
> + - renesas,dmac-r8a7744 # RZ/G1N
> + - renesas,dmac-r8a7745 # RZ/G1E
> + - renesas,dmac-r8a77470 # RZ/G1C
> + - renesas,dmac-r8a774a1 # RZ/G2M
> + - renesas,dmac-r8a774b1 # RZ/G2N
> + - renesas,dmac-r8a774c0 # RZ/G2E
> + - renesas,dmac-r8a774e1 # RZ/G2H
> + - renesas,dmac-r8a7790 # R-Car H2
> + - renesas,dmac-r8a7791 # R-Car M2-W
> + - renesas,dmac-r8a7792 # R-Car V2H
> + - renesas,dmac-r8a7793 # R-Car M2-N
> + - renesas,dmac-r8a7794 # R-Car E2
> + - renesas,dmac-r8a7795 # R-Car H3
> + - renesas,dmac-r8a7796 # R-Car M3-W
> + - renesas,dmac-r8a77961 # R-Car M3-W+
> + - renesas,dmac-r8a77965 # R-Car M3-N
> + - renesas,dmac-r8a77970 # R-Car V3M
> + - renesas,dmac-r8a77980 # R-Car V3H
> + - renesas,dmac-r8a77990 # R-Car E3
> + - renesas,dmac-r8a77995 # R-Car D3
> + - const: renesas,rcar-dmac
> +
> + - items:
> + - const: renesas,dmac-r8a779a0 # R-Car V3U
> +
> + reg: true
>
> interrupts:
> minItems: 9
> @@ -110,6 +113,23 @@ required:
> - power-domains
> - resets
>
> +if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - renesas,dmac-r8a779a0
> +then:
> + properties:
> + reg:
> + items:
> + - description: Base register block
> + - description: Channel register block
> +else:
> + properties:
> + reg:
> + maxItems: 1
> +
> additionalProperties: false
>
> examples:
--
Regards,
Laurent Pinchart