Hi,
Combined patchset of separate v1 sets:
https://lore.kernel.org/linux-samsung-soc/[email protected]/T/#t
https://lore.kernel.org/linux-samsung-soc/[email protected]/T/#t
https://lore.kernel.org/linux-samsung-soc/[email protected]/T/#t
Changes since v1:
1. Patch 7/8: include header to fix clock IDs error in example.
Best regards,
Krzysztof
Krzysztof Kozlowski (8):
dt-bindings: clock: samsung: convert Exynos5250 to dtschema
dt-bindings: clock: samsung: add bindings for Exynos external clock
dt-bindings: clock: samsung: convert Exynos542x to dtschema
dt-bindings: clock: samsung: convert Exynos3250 to dtschema
dt-bindings: clock: samsung: convert Exynos4 to dtschema
dt-bindings: clock: samsung: convert Exynos AudSS to dtschema
dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema
MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry
.../bindings/clock/clk-exynos-audss.txt | 103 ------------------
.../bindings/clock/clk-s5pv210-audss.txt | 53 ---------
.../bindings/clock/exynos3250-clock.txt | 57 ----------
.../bindings/clock/exynos4-clock.txt | 86 ---------------
.../bindings/clock/exynos5250-clock.txt | 41 -------
.../bindings/clock/exynos5420-clock.txt | 42 -------
.../clock/samsung,exynos-audss-clock.yaml | 79 ++++++++++++++
.../bindings/clock/samsung,exynos-clock.yaml | 87 +++++++++++++++
.../clock/samsung,exynos-ext-clock.yaml | 46 ++++++++
.../clock/samsung,s5pv210-audss-clock.yaml | 77 +++++++++++++
MAINTAINERS | 4 +
11 files changed, 293 insertions(+), 382 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
delete mode 100644 Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt
delete mode 100644 Documentation/devicetree/bindings/clock/exynos3250-clock.txt
delete mode 100644 Documentation/devicetree/bindings/clock/exynos4-clock.txt
delete mode 100644 Documentation/devicetree/bindings/clock/exynos5250-clock.txt
delete mode 100644 Documentation/devicetree/bindings/clock/exynos5420-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-ext-clock.yaml
create mode 100644 Documentation/devicetree/bindings/clock/samsung,s5pv210-audss-clock.yaml
--
2.30.2
Convert Samsung Exynos5250 clock controller bindings to DT schema format
using json-schema.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/clock/exynos5250-clock.txt | 41 ----------------
.../bindings/clock/samsung,exynos-clock.yaml | 48 +++++++++++++++++++
MAINTAINERS | 1 +
3 files changed, 49 insertions(+), 41 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/exynos5250-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
deleted file mode 100644
index aff266a12eeb..000000000000
--- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-* Samsung Exynos5250 Clock Controller
-
-The Exynos5250 clock controller generates and supplies clock to various
-controllers within the Exynos5250 SoC.
-
-Required Properties:
-
-- compatible: should be one of the following.
- - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos5250.h header and can be used in device
-tree sources.
-
-Example 1: An example of a clock controller node is listed below.
-
- clock: clock-controller@10010000 {
- compatible = "samsung,exynos5250-clock";
- reg = <0x10010000 0x30000>;
- #clock-cells = <1>;
- };
-
-Example 2: UART controller node that consumes the clock generated by the clock
- controller. Refer to the standard clock bindings for information
- about 'clocks' and 'clock-names' property.
-
- serial@13820000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13820000 0x100>;
- interrupts = <0 54 0>;
- clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
- clock-names = "uart", "clk_uart_baud0";
- };
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
new file mode 100644
index 000000000000..cd6567bd8cc7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC clock controller
+
+maintainers:
+ - Chanwoo Choi <[email protected]>
+ - Krzysztof Kozlowski <[email protected]>
+ - Sylwester Nawrocki <[email protected]>
+ - Tomasz Figa <[email protected]>
+
+description: |
+ All available clocks are defined as preprocessor macros in
+ dt-bindings/clock/ headers.
+
+properties:
+ compatible:
+ const: samsung,exynos5250-clock
+
+ assigned-clocks: true
+ assigned-clock-parents: true
+ assigned-clock-rates: true
+ clocks: true
+
+ "#clock-cells":
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5250.h>
+ clock: clock-controller@10010000 {
+ compatible = "samsung,exynos5250-clock";
+ reg = <0x10010000 0x30000>;
+ #clock-cells = <1>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 36aee8517ab0..2dbacacac3f5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16491,6 +16491,7 @@ L: [email protected]
S: Supported
T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
F: Documentation/devicetree/bindings/clock/exynos*.txt
+F: Documentation/devicetree/bindings/clock/samsung,*.yaml
F: Documentation/devicetree/bindings/clock/samsung,s3c*
F: Documentation/devicetree/bindings/clock/samsung,s5p*
F: drivers/clk/samsung/
--
2.30.2
Cover the S3C and S5Pv210 clock controller binding headers by Samsung
SoC clock controller drivers maintainer entry.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2dbacacac3f5..4477215ef649 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16496,6 +16496,9 @@ F: Documentation/devicetree/bindings/clock/samsung,s3c*
F: Documentation/devicetree/bindings/clock/samsung,s5p*
F: drivers/clk/samsung/
F: include/dt-bindings/clock/exynos*.h
+F: include/dt-bindings/clock/s3c*.h
+F: include/dt-bindings/clock/s5p*.h
+F: include/dt-bindings/clock/samsung,*.h
F: include/linux/clk/samsung.h
F: include/linux/platform_data/clk-s3c2410.h
--
2.30.2
Merge Exynos4210 and Exynos4412 clock controller bindings to existing DT
schema.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/clock/exynos4-clock.txt | 86 -------------------
.../bindings/clock/samsung,exynos-clock.yaml | 29 ++++++-
2 files changed, 28 insertions(+), 87 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/exynos4-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
deleted file mode 100644
index 17bb11365354..000000000000
--- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ /dev/null
@@ -1,86 +0,0 @@
-* Samsung Exynos4 Clock Controller
-
-The Exynos4 clock controller generates and supplies clock to various controllers
-within the Exynos4 SoC. The clock binding described here is applicable to all
-SoC's in the Exynos4 family.
-
-Required Properties:
-
-- compatible: should be one of the following.
- - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
- - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos4.h header and can be used in device
-tree sources.
-
-Example 1: An example of a clock controller node is listed below.
-
- clock: clock-controller@10030000 {
- compatible = "samsung,exynos4210-clock";
- reg = <0x10030000 0x20000>;
- #clock-cells = <1>;
- };
-
-Example 2: UART controller node that consumes the clock generated by the clock
- controller. Refer to the standard clock bindings for information
- about 'clocks' and 'clock-names' property.
-
- serial@13820000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13820000 0x100>;
- interrupts = <0 54 0>;
- clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
- clock-names = "uart", "clk_uart_baud0";
- };
-
-Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP)
-subsystem. Registers for those clocks are located in the ISP power domain.
-Because those registers are also located in a different memory region than
-the main clock controller, a separate clock controller has to be defined for
-handling them.
-
-Required Properties:
-
-- compatible: should be "samsung,exynos4412-isp-clock".
-
-- reg: physical base address of the ISP clock controller and length of memory
- mapped region.
-
-- #clock-cells: should be 1.
-
-- clocks: list of the clock controller input clock identifiers,
- from common clock bindings, should point to CLK_ACLK200 and
- CLK_ACLK400_MCUISP clocks from the main clock controller.
-
-- clock-names: list of the clock controller input clock names,
- as described in clock-bindings.txt, should be "aclk200" and
- "aclk400_mcuisp".
-
-- power-domains: a phandle to ISP power domain node as described by
- generic PM domain bindings.
-
-Example 3: The clock controllers bindings for Exynos4412 SoCs.
-
- clock: clock-controller@10030000 {
- compatible = "samsung,exynos4412-clock";
- reg = <0x10030000 0x18000>;
- #clock-cells = <1>;
- };
-
- isp_clock: clock-controller@10048000 {
- compatible = "samsung,exynos4412-isp-clock";
- reg = <0x10048000 0x1000>;
- #clock-cells = <1>;
- power-domains = <&pd_isp>;
- clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
- clock-names = "aclk200", "aclk400_mcuisp";
- };
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
index c7b07fcd3fa1..ea73201f259b 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
@@ -23,6 +23,9 @@ properties:
- samsung,exynos3250-cmu
- samsung,exynos3250-cmu-dmc
- samsung,exynos3250-cmu-isp
+ - samsung,exynos4210-clock
+ - samsung,exynos4412-clock
+ - samsung,exynos4412-isp-clock
- samsung,exynos5250-clock
- samsung,exynos5420-clock
- samsung,exynos5800-clock
@@ -35,11 +38,18 @@ properties:
assigned-clocks: true
assigned-clock-parents: true
assigned-clock-rates: true
- clocks: true
+ clocks:
+ description: |
+ For samsung,exynos4412-isp-clock, the input clocks should be CLK_ACLK200
+ and CLK_ACLK400_MCUISP from the main clock controller.
+
+ clock-names: true
"#clock-cells":
const: 1
+ power-domains: true
+
reg:
maxItems: 1
@@ -50,6 +60,23 @@ required:
additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos4412-isp-clock
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: aclk200
+ - const: aclk400_mcuisp
+ required:
+ - clocks
+ - clock-names
+ - power-domains
+
examples:
- |
#include <dt-bindings/clock/exynos5250.h>
--
2.30.2
Convert Samsung Exynos Audio SubSystem clock controller bindings to DT
schema format using json-schema.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/clock/clk-exynos-audss.txt | 103 ------------------
.../clock/samsung,exynos-audss-clock.yaml | 79 ++++++++++++++
2 files changed, 79 insertions(+), 103 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
deleted file mode 100644
index 6030afb10b5c..000000000000
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ /dev/null
@@ -1,103 +0,0 @@
-* Samsung Audio Subsystem Clock Controller
-
-The Samsung Audio Subsystem clock controller generates and supplies clocks
-to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
-binding described here is applicable to all SoCs in Exynos family.
-
-Required Properties:
-
-- compatible: should be one of the following:
- - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
- - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
- SoCs.
- - "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
- SoCs.
- - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
- SoCs.
-- reg: physical base address and length of the controller's register set.
-
-- #clock-cells: should be 1.
-
-- clocks:
- - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
- is used if not specified.
- - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
- is used if not specified.
- - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
- specified.
- - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
- not specified.
- - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
- specified.
-
-- clock-names: Aliases for the above clocks. They should be "pll_ref",
- "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
-
-Optional Properties:
-
- - power-domains: a phandle to respective power domain node as described by
- generic PM domain bindings (see power/power_domain.txt for more
- information).
-
-The following is the list of clocks generated by the controller. Each clock is
-assigned an identifier and client nodes use this identifier to specify the
-clock which they consume. Some of the clocks are available only on a particular
-Exynos4 SoC and this is specified where applicable.
-
-Provided clocks:
-
-Clock ID SoC (if specific)
------------------------------------------------
-
-mout_audss 0
-mout_i2s 1
-dout_srp 2
-dout_aud_bus 3
-dout_i2s 4
-srp_clk 5
-i2s_bus 6
-sclk_i2s 7
-pcm_bus 8
-sclk_pcm 9
-adma 10 Exynos5420
-
-Example 1: An example of a clock controller node using the default input
- clock names is listed below.
-
-clock_audss: audss-clock-controller@3810000 {
- compatible = "samsung,exynos5250-audss-clock";
- reg = <0x03810000 0x0C>;
- #clock-cells = <1>;
-};
-
-Example 2: An example of a clock controller node with the input clocks
- specified.
-
-clock_audss: audss-clock-controller@3810000 {
- compatible = "samsung,exynos5250-audss-clock";
- reg = <0x03810000 0x0C>;
- #clock-cells = <1>;
- clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
- <&ext_i2s_clk>;
- clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
-};
-
-Example 3: I2S controller node that consumes the clock generated by the clock
- controller. Refer to the standard clock bindings for information
- about 'clocks' and 'clock-names' property.
-
-i2s0: i2s@3830000 {
- compatible = "samsung,i2s-v5";
- reg = <0x03830000 0x100>;
- dmas = <&pdma0 10
- &pdma0 9
- &pdma0 8>;
- dma-names = "tx", "rx", "tx-sec";
- clocks = <&clock_audss EXYNOS_I2S_BUS>,
- <&clock_audss EXYNOS_I2S_BUS>,
- <&clock_audss EXYNOS_SCLK_I2S>,
- <&clock_audss EXYNOS_MOUT_AUDSS>,
- <&clock_audss EXYNOS_MOUT_I2S>;
- clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
- "mout_audss", "mout_i2s";
-};
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
new file mode 100644
index 000000000000..d60b29fa22e7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC Audio SubSystem clock controller
+
+maintainers:
+ - Chanwoo Choi <[email protected]>
+ - Krzysztof Kozlowski <[email protected]>
+ - Sylwester Nawrocki <[email protected]>
+ - Tomasz Figa <[email protected]>
+
+description: |
+ All available clocks are defined as preprocessor macros in
+ include/dt-bindings/clock/exynos-audss-clk.h header.
+
+properties:
+ compatible:
+ enum:
+ - samsung,exynos4210-audss-clock
+ - samsung,exynos5250-audss-clock
+ - samsung,exynos5410-audss-clock
+ - samsung,exynos5420-audss-clock
+
+ clocks:
+ minItems: 2
+ items:
+ - description:
+ Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is
+ used if not specified.
+ - description:
+ Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" is
+ used if not specified.
+ - description:
+ Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if not
+ specified.
+ - description:
+ PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not specified.
+ - description:
+ External i2s clock, parent of mout_i2s. "cdclk0" is used if not
+ specified.
+
+ clock-names:
+ minItems: 2
+ items:
+ - const: pll_ref
+ - const: pll_in
+ - const: sclk_audio
+ - const: sclk_pcm_in
+ - const: cdclk
+
+ "#clock-cells":
+ const: 1
+
+ power-domains: true
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - "#clock-cells"
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@3810000 {
+ compatible = "samsung,exynos5250-audss-clock";
+ reg = <0x03810000 0x0c>;
+ #clock-cells = <1>;
+ clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, <&ext_i2s_clk>;
+ clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
+ };
--
2.30.2
Merge Exynos542x clock controller bindings to existing DT schema.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../bindings/clock/exynos5420-clock.txt | 42 -------------------
.../bindings/clock/samsung,exynos-clock.yaml | 11 ++++-
2 files changed, 10 insertions(+), 43 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/clock/exynos5420-clock.txt
diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
deleted file mode 100644
index 717a7b1531c7..000000000000
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-* Samsung Exynos5420 Clock Controller
-
-The Exynos5420 clock controller generates and supplies clock to various
-controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
-
-Required Properties:
-
-- compatible: should be one of the following.
- - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
- - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-Each clock is assigned an identifier and client nodes can use this identifier
-to specify the clock which they consume.
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/exynos5420.h header and can be used in device
-tree sources.
-
-Example 1: An example of a clock controller node is listed below.
-
- clock: clock-controller@10010000 {
- compatible = "samsung,exynos5420-clock";
- reg = <0x10010000 0x30000>;
- #clock-cells = <1>;
- };
-
-Example 2: UART controller node that consumes the clock generated by the clock
- controller. Refer to the standard clock bindings for information
- about 'clocks' and 'clock-names' property.
-
- serial@13820000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13820000 0x100>;
- interrupts = <0 54 0>;
- clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
- clock-names = "uart", "clk_uart_baud0";
- };
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
index cd6567bd8cc7..b0f58a1cf6cb 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
@@ -18,7 +18,16 @@ description: |
properties:
compatible:
- const: samsung,exynos5250-clock
+ oneOf:
+ - enum:
+ - samsung,exynos5250-clock
+ - samsung,exynos5420-clock
+ - samsung,exynos5800-clock
+ - items:
+ - enum:
+ - samsung,exynos5420-clock
+ - samsung,exynos5800-clock
+ - const: syscon
assigned-clocks: true
assigned-clock-parents: true
--
2.30.2
On Tue, 10 Aug 2021 at 12:32, Krzysztof Kozlowski
<[email protected]> wrote:
>
> Convert Samsung Exynos Audio SubSystem clock controller bindings to DT
> schema format using json-schema.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/clock/clk-exynos-audss.txt | 103 ------------------
> .../clock/samsung,exynos-audss-clock.yaml | 79 ++++++++++++++
> 2 files changed, 79 insertions(+), 103 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
> deleted file mode 100644
> index 6030afb10b5c..000000000000
> --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
> +++ /dev/null
> @@ -1,103 +0,0 @@
> -* Samsung Audio Subsystem Clock Controller
> -
> -The Samsung Audio Subsystem clock controller generates and supplies clocks
> -to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
> -binding described here is applicable to all SoCs in Exynos family.
> -
> -Required Properties:
> -
> -- compatible: should be one of the following:
> - - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
> - - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
> - SoCs.
> - - "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
> - SoCs.
> - - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
> - SoCs.
> -- reg: physical base address and length of the controller's register set.
> -
> -- #clock-cells: should be 1.
> -
> -- clocks:
> - - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
> - is used if not specified.
> - - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
> - is used if not specified.
> - - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
> - specified.
> - - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
> - not specified.
> - - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
> - specified.
> -
> -- clock-names: Aliases for the above clocks. They should be "pll_ref",
> - "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
> -
> -Optional Properties:
> -
> - - power-domains: a phandle to respective power domain node as described by
> - generic PM domain bindings (see power/power_domain.txt for more
> - information).
> -
> -The following is the list of clocks generated by the controller. Each clock is
> -assigned an identifier and client nodes use this identifier to specify the
> -clock which they consume. Some of the clocks are available only on a particular
> -Exynos4 SoC and this is specified where applicable.
> -
> -Provided clocks:
> -
> -Clock ID SoC (if specific)
> ------------------------------------------------
> -
> -mout_audss 0
> -mout_i2s 1
> -dout_srp 2
> -dout_aud_bus 3
> -dout_i2s 4
> -srp_clk 5
> -i2s_bus 6
> -sclk_i2s 7
> -pcm_bus 8
> -sclk_pcm 9
> -adma 10 Exynos5420
> -
> -Example 1: An example of a clock controller node using the default input
> - clock names is listed below.
> -
> -clock_audss: audss-clock-controller@3810000 {
> - compatible = "samsung,exynos5250-audss-clock";
> - reg = <0x03810000 0x0C>;
> - #clock-cells = <1>;
> -};
> -
> -Example 2: An example of a clock controller node with the input clocks
> - specified.
> -
> -clock_audss: audss-clock-controller@3810000 {
> - compatible = "samsung,exynos5250-audss-clock";
> - reg = <0x03810000 0x0C>;
> - #clock-cells = <1>;
> - clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
> - <&ext_i2s_clk>;
> - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
> -};
> -
> -Example 3: I2S controller node that consumes the clock generated by the clock
> - controller. Refer to the standard clock bindings for information
> - about 'clocks' and 'clock-names' property.
> -
> -i2s0: i2s@3830000 {
> - compatible = "samsung,i2s-v5";
> - reg = <0x03830000 0x100>;
> - dmas = <&pdma0 10
> - &pdma0 9
> - &pdma0 8>;
> - dma-names = "tx", "rx", "tx-sec";
> - clocks = <&clock_audss EXYNOS_I2S_BUS>,
> - <&clock_audss EXYNOS_I2S_BUS>,
> - <&clock_audss EXYNOS_SCLK_I2S>,
> - <&clock_audss EXYNOS_MOUT_AUDSS>,
> - <&clock_audss EXYNOS_MOUT_I2S>;
> - clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
> - "mout_audss", "mout_i2s";
> -};
Seems like some examples and "Provided clocks" table were dropped in
in yaml binding. Also there is no description for example present in
yaml file. Is that some redundant info and was dropped intentionally?
I'm just worrying about losing some useful info during the conversion.
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
> new file mode 100644
> index 000000000000..d60b29fa22e7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
> @@ -0,0 +1,79 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung Exynos SoC Audio SubSystem clock controller
> +
> +maintainers:
> + - Chanwoo Choi <[email protected]>
> + - Krzysztof Kozlowski <[email protected]>
> + - Sylwester Nawrocki <[email protected]>
> + - Tomasz Figa <[email protected]>
> +
> +description: |
> + All available clocks are defined as preprocessor macros in
> + include/dt-bindings/clock/exynos-audss-clk.h header.
> +
> +properties:
> + compatible:
> + enum:
> + - samsung,exynos4210-audss-clock
> + - samsung,exynos5250-audss-clock
> + - samsung,exynos5410-audss-clock
> + - samsung,exynos5420-audss-clock
> +
> + clocks:
> + minItems: 2
> + items:
> + - description:
> + Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is
> + used if not specified.
> + - description:
> + Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" is
> + used if not specified.
> + - description:
> + Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if not
> + specified.
> + - description:
> + PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not specified.
> + - description:
> + External i2s clock, parent of mout_i2s. "cdclk0" is used if not
> + specified.
> +
> + clock-names:
> + minItems: 2
> + items:
> + - const: pll_ref
> + - const: pll_in
> + - const: sclk_audio
> + - const: sclk_pcm_in
> + - const: cdclk
> +
> + "#clock-cells":
> + const: 1
> +
> + power-domains: true
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - clocks
> + - clock-names
> + - "#clock-cells"
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller@3810000 {
> + compatible = "samsung,exynos5250-audss-clock";
> + reg = <0x03810000 0x0c>;
> + #clock-cells = <1>;
> + clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, <&ext_i2s_clk>;
> + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
> + };
> --
> 2.30.2
>
On Tue, 10 Aug 2021 at 12:32, Krzysztof Kozlowski
<[email protected]> wrote:
>
> Convert Samsung Exynos5250 clock controller bindings to DT schema format
> using json-schema.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/clock/exynos5250-clock.txt | 41 ----------------
> .../bindings/clock/samsung,exynos-clock.yaml | 48 +++++++++++++++++++
> MAINTAINERS | 1 +
> 3 files changed, 49 insertions(+), 41 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> deleted file mode 100644
> index aff266a12eeb..000000000000
> --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> +++ /dev/null
> @@ -1,41 +0,0 @@
> -* Samsung Exynos5250 Clock Controller
> -
> -The Exynos5250 clock controller generates and supplies clock to various
> -controllers within the Exynos5250 SoC.
> -
> -Required Properties:
> -
> -- compatible: should be one of the following.
> - - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
> -
> -- reg: physical base address of the controller and length of memory mapped
> - region.
> -
> -- #clock-cells: should be 1.
> -
> -Each clock is assigned an identifier and client nodes can use this identifier
> -to specify the clock which they consume.
> -
> -All available clocks are defined as preprocessor macros in
> -dt-bindings/clock/exynos5250.h header and can be used in device
> -tree sources.
> -
> -Example 1: An example of a clock controller node is listed below.
> -
> - clock: clock-controller@10010000 {
> - compatible = "samsung,exynos5250-clock";
> - reg = <0x10010000 0x30000>;
> - #clock-cells = <1>;
> - };
> -
> -Example 2: UART controller node that consumes the clock generated by the clock
> - controller. Refer to the standard clock bindings for information
> - about 'clocks' and 'clock-names' property.
> -
> - serial@13820000 {
> - compatible = "samsung,exynos4210-uart";
> - reg = <0x13820000 0x100>;
> - interrupts = <0 54 0>;
> - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
> - clock-names = "uart", "clk_uart_baud0";
> - };
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
> new file mode 100644
> index 000000000000..cd6567bd8cc7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
> @@ -0,0 +1,48 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/samsung,exynos-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung Exynos SoC clock controller
> +
> +maintainers:
> + - Chanwoo Choi <[email protected]>
> + - Krzysztof Kozlowski <[email protected]>
> + - Sylwester Nawrocki <[email protected]>
> + - Tomasz Figa <[email protected]>
> +
> +description: |
> + All available clocks are defined as preprocessor macros in
> + dt-bindings/clock/ headers.
> +
> +properties:
> + compatible:
> + const: samsung,exynos5250-clock
> +
> + assigned-clocks: true
> + assigned-clock-parents: true
> + assigned-clock-rates: true
> + clocks: true
> +
> + "#clock-cells":
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - "#clock-cells"
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/exynos5250.h>
> + clock: clock-controller@10010000 {
> + compatible = "samsung,exynos5250-clock";
> + reg = <0x10010000 0x30000>;
> + #clock-cells = <1>;
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 36aee8517ab0..2dbacacac3f5 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -16491,6 +16491,7 @@ L: [email protected]
> S: Supported
> T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
> F: Documentation/devicetree/bindings/clock/exynos*.txt
Are there any exynos*.txt bindings actually left after this series? If
no, maybe it's worth to remove this line while at it.
> +F: Documentation/devicetree/bindings/clock/samsung,*.yaml
> F: Documentation/devicetree/bindings/clock/samsung,s3c*
> F: Documentation/devicetree/bindings/clock/samsung,s5p*
> F: drivers/clk/samsung/
> --
> 2.30.2
>
Hi Krzysztof,
On Tue, 10 Aug 2021 at 12:32, Krzysztof Kozlowski
<[email protected]> wrote:
>
> Hi,
>
> Combined patchset of separate v1 sets:
>
> https://lore.kernel.org/linux-samsung-soc/[email protected]/T/#t
> https://lore.kernel.org/linux-samsung-soc/[email protected]/T/#t
> https://lore.kernel.org/linux-samsung-soc/[email protected]/T/#t
>
> Changes since v1:
> 1. Patch 7/8: include header to fix clock IDs error in example.
>
> Best regards,
> Krzysztof
>
>
> Krzysztof Kozlowski (8):
> dt-bindings: clock: samsung: convert Exynos5250 to dtschema
> dt-bindings: clock: samsung: add bindings for Exynos external clock
> dt-bindings: clock: samsung: convert Exynos542x to dtschema
> dt-bindings: clock: samsung: convert Exynos3250 to dtschema
> dt-bindings: clock: samsung: convert Exynos4 to dtschema
> dt-bindings: clock: samsung: convert Exynos AudSS to dtschema
> dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema
> MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry
>
> .../bindings/clock/clk-exynos-audss.txt | 103 ------------------
> .../bindings/clock/clk-s5pv210-audss.txt | 53 ---------
> .../bindings/clock/exynos3250-clock.txt | 57 ----------
> .../bindings/clock/exynos4-clock.txt | 86 ---------------
> .../bindings/clock/exynos5250-clock.txt | 41 -------
> .../bindings/clock/exynos5420-clock.txt | 42 -------
> .../clock/samsung,exynos-audss-clock.yaml | 79 ++++++++++++++
> .../bindings/clock/samsung,exynos-clock.yaml | 87 +++++++++++++++
> .../clock/samsung,exynos-ext-clock.yaml | 46 ++++++++
> .../clock/samsung,s5pv210-audss-clock.yaml | 77 +++++++++++++
> MAINTAINERS | 4 +
> 11 files changed, 293 insertions(+), 382 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
> delete mode 100644 Documentation/devicetree/bindings/clock/clk-s5pv210-audss.txt
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos3250-clock.txt
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos4-clock.txt
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-ext-clock.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,s5pv210-audss-clock.yaml
>
> --
For the whole series:
Reviewed-by: Sam Protsenko <[email protected]>
Thanks!
> 2.30.2
>
On 10/08/2021 19:51, Sam Protsenko wrote:
> On Tue, 10 Aug 2021 at 12:32, Krzysztof Kozlowski
> <[email protected]> wrote:
>>
>> Convert Samsung Exynos5250 clock controller bindings to DT schema format
>> using json-schema.
>>
>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>> ---
>> .../bindings/clock/exynos5250-clock.txt | 41 ----------------
>> .../bindings/clock/samsung,exynos-clock.yaml | 48 +++++++++++++++++++
>> MAINTAINERS | 1 +
>> 3 files changed, 49 insertions(+), 41 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/clock/exynos5250-clock.txt
>> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
>> deleted file mode 100644
>> index aff266a12eeb..000000000000
>> --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
>> +++ /dev/null
>> @@ -1,41 +0,0 @@
>> -* Samsung Exynos5250 Clock Controller
>> -
>> -The Exynos5250 clock controller generates and supplies clock to various
>> -controllers within the Exynos5250 SoC.
>> -
>> -Required Properties:
>> -
>> -- compatible: should be one of the following.
>> - - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
>> -
>> -- reg: physical base address of the controller and length of memory mapped
>> - region.
>> -
>> -- #clock-cells: should be 1.
>> -
>> -Each clock is assigned an identifier and client nodes can use this identifier
>> -to specify the clock which they consume.
>> -
>> -All available clocks are defined as preprocessor macros in
>> -dt-bindings/clock/exynos5250.h header and can be used in device
>> -tree sources.
>> -
>> -Example 1: An example of a clock controller node is listed below.
>> -
>> - clock: clock-controller@10010000 {
>> - compatible = "samsung,exynos5250-clock";
>> - reg = <0x10010000 0x30000>;
>> - #clock-cells = <1>;
>> - };
>> -
>> -Example 2: UART controller node that consumes the clock generated by the clock
>> - controller. Refer to the standard clock bindings for information
>> - about 'clocks' and 'clock-names' property.
>> -
>> - serial@13820000 {
>> - compatible = "samsung,exynos4210-uart";
>> - reg = <0x13820000 0x100>;
>> - interrupts = <0 54 0>;
>> - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
>> - clock-names = "uart", "clk_uart_baud0";
>> - };
>> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
>> new file mode 100644
>> index 000000000000..cd6567bd8cc7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
>> @@ -0,0 +1,48 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/samsung,exynos-clock.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Samsung Exynos SoC clock controller
>> +
>> +maintainers:
>> + - Chanwoo Choi <[email protected]>
>> + - Krzysztof Kozlowski <[email protected]>
>> + - Sylwester Nawrocki <[email protected]>
>> + - Tomasz Figa <[email protected]>
>> +
>> +description: |
>> + All available clocks are defined as preprocessor macros in
>> + dt-bindings/clock/ headers.
>> +
>> +properties:
>> + compatible:
>> + const: samsung,exynos5250-clock
>> +
>> + assigned-clocks: true
>> + assigned-clock-parents: true
>> + assigned-clock-rates: true
>> + clocks: true
>> +
>> + "#clock-cells":
>> + const: 1
>> +
>> + reg:
>> + maxItems: 1
>> +
>> +required:
>> + - compatible
>> + - "#clock-cells"
>> + - reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/exynos5250.h>
>> + clock: clock-controller@10010000 {
>> + compatible = "samsung,exynos5250-clock";
>> + reg = <0x10010000 0x30000>;
>> + #clock-cells = <1>;
>> + };
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 36aee8517ab0..2dbacacac3f5 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -16491,6 +16491,7 @@ L: [email protected]
>> S: Supported
>> T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
>> F: Documentation/devicetree/bindings/clock/exynos*.txt
>
> Are there any exynos*.txt bindings actually left after this series? If
> no, maybe it's worth to remove this line while at it.
Yes, there are. These are the bindings which expect specific external
fixed clock and I don't know yet how to model it in dtschema.
Best regards,
Krzysztof
On 10/08/2021 19:46, Sam Protsenko wrote:
> On Tue, 10 Aug 2021 at 12:32, Krzysztof Kozlowski
> <[email protected]> wrote:
>>
>> Convert Samsung Exynos Audio SubSystem clock controller bindings to DT
>> schema format using json-schema.
>>
>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>> ---
>> .../bindings/clock/clk-exynos-audss.txt | 103 ------------------
>> .../clock/samsung,exynos-audss-clock.yaml | 79 ++++++++++++++
>> 2 files changed, 79 insertions(+), 103 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
>> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
>> deleted file mode 100644
>> index 6030afb10b5c..000000000000
>> --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
>> +++ /dev/null
>> @@ -1,103 +0,0 @@
>> -* Samsung Audio Subsystem Clock Controller
>> -
>> -The Samsung Audio Subsystem clock controller generates and supplies clocks
>> -to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
>> -binding described here is applicable to all SoCs in Exynos family.
>> -
>> -Required Properties:
>> -
>> -- compatible: should be one of the following:
>> - - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
>> - - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
>> - SoCs.
>> - - "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
>> - SoCs.
>> - - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
>> - SoCs.
>> -- reg: physical base address and length of the controller's register set.
>> -
>> -- #clock-cells: should be 1.
>> -
>> -- clocks:
>> - - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
>> - is used if not specified.
>> - - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
>> - is used if not specified.
>> - - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
>> - specified.
>> - - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
>> - not specified.
>> - - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
>> - specified.
>> -
>> -- clock-names: Aliases for the above clocks. They should be "pll_ref",
>> - "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
>> -
>> -Optional Properties:
>> -
>> - - power-domains: a phandle to respective power domain node as described by
>> - generic PM domain bindings (see power/power_domain.txt for more
>> - information).
>> -
>> -The following is the list of clocks generated by the controller. Each clock is
>> -assigned an identifier and client nodes use this identifier to specify the
>> -clock which they consume. Some of the clocks are available only on a particular
>> -Exynos4 SoC and this is specified where applicable.
>> -
>> -Provided clocks:
>> -
>> -Clock ID SoC (if specific)
>> ------------------------------------------------
>> -
>> -mout_audss 0
>> -mout_i2s 1
>> -dout_srp 2
>> -dout_aud_bus 3
>> -dout_i2s 4
>> -srp_clk 5
>> -i2s_bus 6
>> -sclk_i2s 7
>> -pcm_bus 8
>> -sclk_pcm 9
>> -adma 10 Exynos5420
>> -
>> -Example 1: An example of a clock controller node using the default input
>> - clock names is listed below.
>> -
>> -clock_audss: audss-clock-controller@3810000 {
>> - compatible = "samsung,exynos5250-audss-clock";
>> - reg = <0x03810000 0x0C>;
>> - #clock-cells = <1>;
>> -};
>> -
>> -Example 2: An example of a clock controller node with the input clocks
>> - specified.
>> -
>> -clock_audss: audss-clock-controller@3810000 {
>> - compatible = "samsung,exynos5250-audss-clock";
>> - reg = <0x03810000 0x0C>;
>> - #clock-cells = <1>;
>> - clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
>> - <&ext_i2s_clk>;
>> - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
>> -};
>> -
>> -Example 3: I2S controller node that consumes the clock generated by the clock
>> - controller. Refer to the standard clock bindings for information
>> - about 'clocks' and 'clock-names' property.
>> -
>> -i2s0: i2s@3830000 {
>> - compatible = "samsung,i2s-v5";
>> - reg = <0x03830000 0x100>;
>> - dmas = <&pdma0 10
>> - &pdma0 9
>> - &pdma0 8>;
>> - dma-names = "tx", "rx", "tx-sec";
>> - clocks = <&clock_audss EXYNOS_I2S_BUS>,
>> - <&clock_audss EXYNOS_I2S_BUS>,
>> - <&clock_audss EXYNOS_SCLK_I2S>,
>> - <&clock_audss EXYNOS_MOUT_AUDSS>,
>> - <&clock_audss EXYNOS_MOUT_I2S>;
>> - clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
>> - "mout_audss", "mout_i2s";
>> -};
>
> Seems like some examples and "Provided clocks" table were dropped in
> in yaml binding. Also there is no description for example present in
> yaml file. Is that some redundant info and was dropped intentionally?
> I'm just worrying about losing some useful info during the conversion.
I don't see any point of having a clock consumer example in a clock
provider binding.
Best regards,
Krzysztof
On Tue, Aug 10, 2021 at 11:31:38AM +0200, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos5250 clock controller bindings to DT schema format
> using json-schema.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/clock/exynos5250-clock.txt | 41 ----------------
> .../bindings/clock/samsung,exynos-clock.yaml | 48 +++++++++++++++++++
> MAINTAINERS | 1 +
> 3 files changed, 49 insertions(+), 41 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> deleted file mode 100644
> index aff266a12eeb..000000000000
> --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
> +++ /dev/null
> @@ -1,41 +0,0 @@
> -* Samsung Exynos5250 Clock Controller
> -
> -The Exynos5250 clock controller generates and supplies clock to various
> -controllers within the Exynos5250 SoC.
> -
> -Required Properties:
> -
> -- compatible: should be one of the following.
> - - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
> -
> -- reg: physical base address of the controller and length of memory mapped
> - region.
> -
> -- #clock-cells: should be 1.
> -
> -Each clock is assigned an identifier and client nodes can use this identifier
> -to specify the clock which they consume.
> -
> -All available clocks are defined as preprocessor macros in
> -dt-bindings/clock/exynos5250.h header and can be used in device
> -tree sources.
> -
> -Example 1: An example of a clock controller node is listed below.
> -
> - clock: clock-controller@10010000 {
> - compatible = "samsung,exynos5250-clock";
> - reg = <0x10010000 0x30000>;
> - #clock-cells = <1>;
> - };
> -
> -Example 2: UART controller node that consumes the clock generated by the clock
> - controller. Refer to the standard clock bindings for information
> - about 'clocks' and 'clock-names' property.
> -
> - serial@13820000 {
> - compatible = "samsung,exynos4210-uart";
> - reg = <0x13820000 0x100>;
> - interrupts = <0 54 0>;
> - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
> - clock-names = "uart", "clk_uart_baud0";
> - };
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
> new file mode 100644
> index 000000000000..cd6567bd8cc7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
> @@ -0,0 +1,48 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/samsung,exynos-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung Exynos SoC clock controller
> +
> +maintainers:
> + - Chanwoo Choi <[email protected]>
> + - Krzysztof Kozlowski <[email protected]>
> + - Sylwester Nawrocki <[email protected]>
> + - Tomasz Figa <[email protected]>
> +
> +description: |
> + All available clocks are defined as preprocessor macros in
> + dt-bindings/clock/ headers.
> +
> +properties:
> + compatible:
> + const: samsung,exynos5250-clock
> +
> + assigned-clocks: true
> + assigned-clock-parents: true
> + assigned-clock-rates: true
These can be dropped. They are always allowed if 'clocks' is present.
> + clocks: true
This needs to define how many.
> +
> + "#clock-cells":
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - "#clock-cells"
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/exynos5250.h>
> + clock: clock-controller@10010000 {
> + compatible = "samsung,exynos5250-clock";
> + reg = <0x10010000 0x30000>;
> + #clock-cells = <1>;
> + };
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 36aee8517ab0..2dbacacac3f5 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -16491,6 +16491,7 @@ L: [email protected]
> S: Supported
> T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
> F: Documentation/devicetree/bindings/clock/exynos*.txt
> +F: Documentation/devicetree/bindings/clock/samsung,*.yaml
> F: Documentation/devicetree/bindings/clock/samsung,s3c*
> F: Documentation/devicetree/bindings/clock/samsung,s5p*
> F: drivers/clk/samsung/
> --
> 2.30.2
>
>
On Tue, Aug 10, 2021 at 11:31:40AM +0200, Krzysztof Kozlowski wrote:
> Merge Exynos542x clock controller bindings to existing DT schema.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/clock/exynos5420-clock.txt | 42 -------------------
> .../bindings/clock/samsung,exynos-clock.yaml | 11 ++++-
> 2 files changed, 10 insertions(+), 43 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos5420-clock.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> deleted file mode 100644
> index 717a7b1531c7..000000000000
> --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -* Samsung Exynos5420 Clock Controller
> -
> -The Exynos5420 clock controller generates and supplies clock to various
> -controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
> -
> -Required Properties:
> -
> -- compatible: should be one of the following.
> - - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
> - - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
> -
> -- reg: physical base address of the controller and length of memory mapped
> - region.
> -
> -- #clock-cells: should be 1.
> -
> -Each clock is assigned an identifier and client nodes can use this identifier
> -to specify the clock which they consume.
> -
> -All available clocks are defined as preprocessor macros in
> -dt-bindings/clock/exynos5420.h header and can be used in device
> -tree sources.
> -
> -Example 1: An example of a clock controller node is listed below.
> -
> - clock: clock-controller@10010000 {
> - compatible = "samsung,exynos5420-clock";
> - reg = <0x10010000 0x30000>;
> - #clock-cells = <1>;
> - };
> -
> -Example 2: UART controller node that consumes the clock generated by the clock
> - controller. Refer to the standard clock bindings for information
> - about 'clocks' and 'clock-names' property.
> -
> - serial@13820000 {
> - compatible = "samsung,exynos4210-uart";
> - reg = <0x13820000 0x100>;
> - interrupts = <0 54 0>;
> - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
> - clock-names = "uart", "clk_uart_baud0";
> - };
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
> index cd6567bd8cc7..b0f58a1cf6cb 100644
> --- a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
> @@ -18,7 +18,16 @@ description: |
>
> properties:
> compatible:
> - const: samsung,exynos5250-clock
> + oneOf:
> + - enum:
> + - samsung,exynos5250-clock
> + - samsung,exynos5420-clock
> + - samsung,exynos5800-clock
> + - items:
> + - enum:
> + - samsung,exynos5420-clock
> + - samsung,exynos5800-clock
Is there a reason these are supported with or without 'syscon'?
> + - const: syscon
>
> assigned-clocks: true
> assigned-clock-parents: true
> --
> 2.30.2
>
>
On Tue, Aug 10, 2021 at 11:31:42AM +0200, Krzysztof Kozlowski wrote:
> Merge Exynos4210 and Exynos4412 clock controller bindings to existing DT
> schema.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/clock/exynos4-clock.txt | 86 -------------------
> .../bindings/clock/samsung,exynos-clock.yaml | 29 ++++++-
> 2 files changed, 28 insertions(+), 87 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/exynos4-clock.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
> deleted file mode 100644
> index 17bb11365354..000000000000
> --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
> +++ /dev/null
> @@ -1,86 +0,0 @@
> -* Samsung Exynos4 Clock Controller
> -
> -The Exynos4 clock controller generates and supplies clock to various controllers
> -within the Exynos4 SoC. The clock binding described here is applicable to all
> -SoC's in the Exynos4 family.
> -
> -Required Properties:
> -
> -- compatible: should be one of the following.
> - - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
> - - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
> -
> -- reg: physical base address of the controller and length of memory mapped
> - region.
> -
> -- #clock-cells: should be 1.
> -
> -Each clock is assigned an identifier and client nodes can use this identifier
> -to specify the clock which they consume.
> -
> -All available clocks are defined as preprocessor macros in
> -dt-bindings/clock/exynos4.h header and can be used in device
> -tree sources.
> -
> -Example 1: An example of a clock controller node is listed below.
> -
> - clock: clock-controller@10030000 {
> - compatible = "samsung,exynos4210-clock";
> - reg = <0x10030000 0x20000>;
> - #clock-cells = <1>;
> - };
> -
> -Example 2: UART controller node that consumes the clock generated by the clock
> - controller. Refer to the standard clock bindings for information
> - about 'clocks' and 'clock-names' property.
> -
> - serial@13820000 {
> - compatible = "samsung,exynos4210-uart";
> - reg = <0x13820000 0x100>;
> - interrupts = <0 54 0>;
> - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
> - clock-names = "uart", "clk_uart_baud0";
> - };
> -
> -Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP)
> -subsystem. Registers for those clocks are located in the ISP power domain.
> -Because those registers are also located in a different memory region than
> -the main clock controller, a separate clock controller has to be defined for
> -handling them.
> -
> -Required Properties:
> -
> -- compatible: should be "samsung,exynos4412-isp-clock".
> -
> -- reg: physical base address of the ISP clock controller and length of memory
> - mapped region.
> -
> -- #clock-cells: should be 1.
> -
> -- clocks: list of the clock controller input clock identifiers,
> - from common clock bindings, should point to CLK_ACLK200 and
> - CLK_ACLK400_MCUISP clocks from the main clock controller.
> -
> -- clock-names: list of the clock controller input clock names,
> - as described in clock-bindings.txt, should be "aclk200" and
> - "aclk400_mcuisp".
> -
> -- power-domains: a phandle to ISP power domain node as described by
> - generic PM domain bindings.
> -
> -Example 3: The clock controllers bindings for Exynos4412 SoCs.
> -
> - clock: clock-controller@10030000 {
> - compatible = "samsung,exynos4412-clock";
> - reg = <0x10030000 0x18000>;
> - #clock-cells = <1>;
> - };
> -
> - isp_clock: clock-controller@10048000 {
> - compatible = "samsung,exynos4412-isp-clock";
> - reg = <0x10048000 0x1000>;
> - #clock-cells = <1>;
> - power-domains = <&pd_isp>;
> - clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
> - clock-names = "aclk200", "aclk400_mcuisp";
> - };
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
> index c7b07fcd3fa1..ea73201f259b 100644
> --- a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
> @@ -23,6 +23,9 @@ properties:
> - samsung,exynos3250-cmu
> - samsung,exynos3250-cmu-dmc
> - samsung,exynos3250-cmu-isp
> + - samsung,exynos4210-clock
> + - samsung,exynos4412-clock
> + - samsung,exynos4412-isp-clock
> - samsung,exynos5250-clock
> - samsung,exynos5420-clock
> - samsung,exynos5800-clock
> @@ -35,11 +38,18 @@ properties:
> assigned-clocks: true
> assigned-clock-parents: true
> assigned-clock-rates: true
> - clocks: true
> + clocks:
> + description: |
> + For samsung,exynos4412-isp-clock, the input clocks should be CLK_ACLK200
> + and CLK_ACLK400_MCUISP from the main clock controller.
> +
> + clock-names: true
>
> "#clock-cells":
> const: 1
>
> + power-domains: true
> +
How many?
Now all the flavors can have a power domain? Maybe this should be a
separate binding given this and the if/then below.
> reg:
> maxItems: 1
>
> @@ -50,6 +60,23 @@ required:
>
> additionalProperties: false
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos4412-isp-clock
> + then:
> + properties:
> + clock-names:
> + items:
> + - const: aclk200
> + - const: aclk400_mcuisp
> + required:
> + - clocks
> + - clock-names
> + - power-domains
> +
> examples:
> - |
> #include <dt-bindings/clock/exynos5250.h>
> --
> 2.30.2
>
>
On Wed, Aug 11, 2021 at 08:46:46AM +0200, Krzysztof Kozlowski wrote:
> On 10/08/2021 19:46, Sam Protsenko wrote:
> > On Tue, 10 Aug 2021 at 12:32, Krzysztof Kozlowski
> > <[email protected]> wrote:
> >>
> >> Convert Samsung Exynos Audio SubSystem clock controller bindings to DT
> >> schema format using json-schema.
> >>
> >> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> >> ---
> >> .../bindings/clock/clk-exynos-audss.txt | 103 ------------------
> >> .../clock/samsung,exynos-audss-clock.yaml | 79 ++++++++++++++
> >> 2 files changed, 79 insertions(+), 103 deletions(-)
> >> delete mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
> >> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
> >>
> >> diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
> >> deleted file mode 100644
> >> index 6030afb10b5c..000000000000
> >> --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
> >> +++ /dev/null
> >> @@ -1,103 +0,0 @@
> >> -* Samsung Audio Subsystem Clock Controller
> >> -
> >> -The Samsung Audio Subsystem clock controller generates and supplies clocks
> >> -to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
> >> -binding described here is applicable to all SoCs in Exynos family.
> >> -
> >> -Required Properties:
> >> -
> >> -- compatible: should be one of the following:
> >> - - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
> >> - - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
> >> - SoCs.
> >> - - "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
> >> - SoCs.
> >> - - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
> >> - SoCs.
> >> -- reg: physical base address and length of the controller's register set.
> >> -
> >> -- #clock-cells: should be 1.
> >> -
> >> -- clocks:
> >> - - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
> >> - is used if not specified.
> >> - - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
> >> - is used if not specified.
> >> - - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
> >> - specified.
> >> - - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
> >> - not specified.
> >> - - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
> >> - specified.
> >> -
> >> -- clock-names: Aliases for the above clocks. They should be "pll_ref",
> >> - "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
> >> -
> >> -Optional Properties:
> >> -
> >> - - power-domains: a phandle to respective power domain node as described by
> >> - generic PM domain bindings (see power/power_domain.txt for more
> >> - information).
> >> -
> >> -The following is the list of clocks generated by the controller. Each clock is
> >> -assigned an identifier and client nodes use this identifier to specify the
> >> -clock which they consume. Some of the clocks are available only on a particular
> >> -Exynos4 SoC and this is specified where applicable.
> >> -
> >> -Provided clocks:
> >> -
> >> -Clock ID SoC (if specific)
> >> ------------------------------------------------
> >> -
> >> -mout_audss 0
> >> -mout_i2s 1
> >> -dout_srp 2
> >> -dout_aud_bus 3
> >> -dout_i2s 4
> >> -srp_clk 5
> >> -i2s_bus 6
> >> -sclk_i2s 7
> >> -pcm_bus 8
> >> -sclk_pcm 9
> >> -adma 10 Exynos5420
> >> -
> >> -Example 1: An example of a clock controller node using the default input
> >> - clock names is listed below.
> >> -
> >> -clock_audss: audss-clock-controller@3810000 {
> >> - compatible = "samsung,exynos5250-audss-clock";
> >> - reg = <0x03810000 0x0C>;
> >> - #clock-cells = <1>;
> >> -};
> >> -
> >> -Example 2: An example of a clock controller node with the input clocks
> >> - specified.
> >> -
> >> -clock_audss: audss-clock-controller@3810000 {
> >> - compatible = "samsung,exynos5250-audss-clock";
> >> - reg = <0x03810000 0x0C>;
> >> - #clock-cells = <1>;
> >> - clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
> >> - <&ext_i2s_clk>;
> >> - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
> >> -};
> >> -
> >> -Example 3: I2S controller node that consumes the clock generated by the clock
> >> - controller. Refer to the standard clock bindings for information
> >> - about 'clocks' and 'clock-names' property.
> >> -
> >> -i2s0: i2s@3830000 {
> >> - compatible = "samsung,i2s-v5";
> >> - reg = <0x03830000 0x100>;
> >> - dmas = <&pdma0 10
> >> - &pdma0 9
> >> - &pdma0 8>;
> >> - dma-names = "tx", "rx", "tx-sec";
> >> - clocks = <&clock_audss EXYNOS_I2S_BUS>,
> >> - <&clock_audss EXYNOS_I2S_BUS>,
> >> - <&clock_audss EXYNOS_SCLK_I2S>,
> >> - <&clock_audss EXYNOS_MOUT_AUDSS>,
> >> - <&clock_audss EXYNOS_MOUT_I2S>;
> >> - clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
> >> - "mout_audss", "mout_i2s";
> >> -};
> >
> > Seems like some examples and "Provided clocks" table were dropped in
> > in yaml binding. Also there is no description for example present in
> > yaml file. Is that some redundant info and was dropped intentionally?
> > I'm just worrying about losing some useful info during the conversion.
>
> I don't see any point of having a clock consumer example in a clock
> provider binding.
+1
Just another one to get wrong...
On Tue, Aug 10, 2021 at 11:31:43AM +0200, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos Audio SubSystem clock controller bindings to DT
> schema format using json-schema.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> .../bindings/clock/clk-exynos-audss.txt | 103 ------------------
> .../clock/samsung,exynos-audss-clock.yaml | 79 ++++++++++++++
> 2 files changed, 79 insertions(+), 103 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
> deleted file mode 100644
> index 6030afb10b5c..000000000000
> --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
> +++ /dev/null
> @@ -1,103 +0,0 @@
> -* Samsung Audio Subsystem Clock Controller
> -
> -The Samsung Audio Subsystem clock controller generates and supplies clocks
> -to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
> -binding described here is applicable to all SoCs in Exynos family.
> -
> -Required Properties:
> -
> -- compatible: should be one of the following:
> - - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
> - - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
> - SoCs.
> - - "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
> - SoCs.
> - - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
> - SoCs.
> -- reg: physical base address and length of the controller's register set.
> -
> -- #clock-cells: should be 1.
> -
> -- clocks:
> - - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
> - is used if not specified.
> - - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
> - is used if not specified.
> - - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
> - specified.
> - - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
> - not specified.
> - - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
> - specified.
> -
> -- clock-names: Aliases for the above clocks. They should be "pll_ref",
> - "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
> -
> -Optional Properties:
> -
> - - power-domains: a phandle to respective power domain node as described by
> - generic PM domain bindings (see power/power_domain.txt for more
> - information).
> -
> -The following is the list of clocks generated by the controller. Each clock is
> -assigned an identifier and client nodes use this identifier to specify the
> -clock which they consume. Some of the clocks are available only on a particular
> -Exynos4 SoC and this is specified where applicable.
> -
> -Provided clocks:
> -
> -Clock ID SoC (if specific)
> ------------------------------------------------
> -
> -mout_audss 0
> -mout_i2s 1
> -dout_srp 2
> -dout_aud_bus 3
> -dout_i2s 4
> -srp_clk 5
> -i2s_bus 6
> -sclk_i2s 7
> -pcm_bus 8
> -sclk_pcm 9
> -adma 10 Exynos5420
> -
> -Example 1: An example of a clock controller node using the default input
> - clock names is listed below.
> -
> -clock_audss: audss-clock-controller@3810000 {
> - compatible = "samsung,exynos5250-audss-clock";
> - reg = <0x03810000 0x0C>;
> - #clock-cells = <1>;
> -};
> -
> -Example 2: An example of a clock controller node with the input clocks
> - specified.
> -
> -clock_audss: audss-clock-controller@3810000 {
> - compatible = "samsung,exynos5250-audss-clock";
> - reg = <0x03810000 0x0C>;
> - #clock-cells = <1>;
> - clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
> - <&ext_i2s_clk>;
> - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
> -};
> -
> -Example 3: I2S controller node that consumes the clock generated by the clock
> - controller. Refer to the standard clock bindings for information
> - about 'clocks' and 'clock-names' property.
> -
> -i2s0: i2s@3830000 {
> - compatible = "samsung,i2s-v5";
> - reg = <0x03830000 0x100>;
> - dmas = <&pdma0 10
> - &pdma0 9
> - &pdma0 8>;
> - dma-names = "tx", "rx", "tx-sec";
> - clocks = <&clock_audss EXYNOS_I2S_BUS>,
> - <&clock_audss EXYNOS_I2S_BUS>,
> - <&clock_audss EXYNOS_SCLK_I2S>,
> - <&clock_audss EXYNOS_MOUT_AUDSS>,
> - <&clock_audss EXYNOS_MOUT_I2S>;
> - clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
> - "mout_audss", "mout_i2s";
> -};
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
> new file mode 100644
> index 000000000000..d60b29fa22e7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
> @@ -0,0 +1,79 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung Exynos SoC Audio SubSystem clock controller
> +
> +maintainers:
> + - Chanwoo Choi <[email protected]>
> + - Krzysztof Kozlowski <[email protected]>
> + - Sylwester Nawrocki <[email protected]>
> + - Tomasz Figa <[email protected]>
> +
> +description: |
> + All available clocks are defined as preprocessor macros in
> + include/dt-bindings/clock/exynos-audss-clk.h header.
> +
> +properties:
> + compatible:
> + enum:
> + - samsung,exynos4210-audss-clock
> + - samsung,exynos5250-audss-clock
> + - samsung,exynos5410-audss-clock
> + - samsung,exynos5420-audss-clock
> +
> + clocks:
> + minItems: 2
> + items:
> + - description:
> + Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is
> + used if not specified.
> + - description:
> + Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" is
> + used if not specified.
> + - description:
> + Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if not
> + specified.
> + - description:
> + PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not specified.
> + - description:
> + External i2s clock, parent of mout_i2s. "cdclk0" is used if not
> + specified.
> +
> + clock-names:
> + minItems: 2
> + items:
> + - const: pll_ref
> + - const: pll_in
> + - const: sclk_audio
> + - const: sclk_pcm_in
> + - const: cdclk
> +
> + "#clock-cells":
> + const: 1
> +
> + power-domains: true
How many?
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - clocks
> + - clock-names
> + - "#clock-cells"
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + clock-controller@3810000 {
> + compatible = "samsung,exynos5250-audss-clock";
> + reg = <0x03810000 0x0c>;
> + #clock-cells = <1>;
> + clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>, <&ext_i2s_clk>;
> + clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
> + };
> --
> 2.30.2
>
>
On 17/08/2021 22:16, Rob Herring wrote:
> On Tue, Aug 10, 2021 at 11:31:38AM +0200, Krzysztof Kozlowski wrote:
>> Convert Samsung Exynos5250 clock controller bindings to DT schema format
>> using json-schema.
>>
>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>> ---
>> .../bindings/clock/exynos5250-clock.txt | 41 ----------------
>> .../bindings/clock/samsung,exynos-clock.yaml | 48 +++++++++++++++++++
>> MAINTAINERS | 1 +
>> 3 files changed, 49 insertions(+), 41 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/clock/exynos5250-clock.txt
>> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
>> deleted file mode 100644
>> index aff266a12eeb..000000000000
>> --- a/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
>> +++ /dev/null
>> @@ -1,41 +0,0 @@
>> -* Samsung Exynos5250 Clock Controller
>> -
>> -The Exynos5250 clock controller generates and supplies clock to various
>> -controllers within the Exynos5250 SoC.
>> -
>> -Required Properties:
>> -
>> -- compatible: should be one of the following.
>> - - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
>> -
>> -- reg: physical base address of the controller and length of memory mapped
>> - region.
>> -
>> -- #clock-cells: should be 1.
>> -
>> -Each clock is assigned an identifier and client nodes can use this identifier
>> -to specify the clock which they consume.
>> -
>> -All available clocks are defined as preprocessor macros in
>> -dt-bindings/clock/exynos5250.h header and can be used in device
>> -tree sources.
>> -
>> -Example 1: An example of a clock controller node is listed below.
>> -
>> - clock: clock-controller@10010000 {
>> - compatible = "samsung,exynos5250-clock";
>> - reg = <0x10010000 0x30000>;
>> - #clock-cells = <1>;
>> - };
>> -
>> -Example 2: UART controller node that consumes the clock generated by the clock
>> - controller. Refer to the standard clock bindings for information
>> - about 'clocks' and 'clock-names' property.
>> -
>> - serial@13820000 {
>> - compatible = "samsung,exynos4210-uart";
>> - reg = <0x13820000 0x100>;
>> - interrupts = <0 54 0>;
>> - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
>> - clock-names = "uart", "clk_uart_baud0";
>> - };
>> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
>> new file mode 100644
>> index 000000000000..cd6567bd8cc7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
>> @@ -0,0 +1,48 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/samsung,exynos-clock.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Samsung Exynos SoC clock controller
>> +
>> +maintainers:
>> + - Chanwoo Choi <[email protected]>
>> + - Krzysztof Kozlowski <[email protected]>
>> + - Sylwester Nawrocki <[email protected]>
>> + - Tomasz Figa <[email protected]>
>> +
>> +description: |
>> + All available clocks are defined as preprocessor macros in
>> + dt-bindings/clock/ headers.
>> +
>> +properties:
>> + compatible:
>> + const: samsung,exynos5250-clock
>> +
>> + assigned-clocks: true
>> + assigned-clock-parents: true
>> + assigned-clock-rates: true
>
> These can be dropped. They are always allowed if 'clocks' is present.
>
>> + clocks: true
>
> This needs to define how many.
>
Right, thanks.
Best regards,
Krzysztof
On 17/08/2021 22:21, Rob Herring wrote:
> On Tue, Aug 10, 2021 at 11:31:40AM +0200, Krzysztof Kozlowski wrote:
>> Merge Exynos542x clock controller bindings to existing DT schema.
>>
>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>> ---
>> .../bindings/clock/exynos5420-clock.txt | 42 -------------------
>> .../bindings/clock/samsung,exynos-clock.yaml | 11 ++++-
>> 2 files changed, 10 insertions(+), 43 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/clock/exynos5420-clock.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
>> deleted file mode 100644
>> index 717a7b1531c7..000000000000
>> --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
>> +++ /dev/null
>> @@ -1,42 +0,0 @@
>> -* Samsung Exynos5420 Clock Controller
>> -
>> -The Exynos5420 clock controller generates and supplies clock to various
>> -controllers within the Exynos5420 SoC and for the Exynos5800 SoC.
>> -
>> -Required Properties:
>> -
>> -- compatible: should be one of the following.
>> - - "samsung,exynos5420-clock" - controller compatible with Exynos5420 SoC.
>> - - "samsung,exynos5800-clock" - controller compatible with Exynos5800 SoC.
>> -
>> -- reg: physical base address of the controller and length of memory mapped
>> - region.
>> -
>> -- #clock-cells: should be 1.
>> -
>> -Each clock is assigned an identifier and client nodes can use this identifier
>> -to specify the clock which they consume.
>> -
>> -All available clocks are defined as preprocessor macros in
>> -dt-bindings/clock/exynos5420.h header and can be used in device
>> -tree sources.
>> -
>> -Example 1: An example of a clock controller node is listed below.
>> -
>> - clock: clock-controller@10010000 {
>> - compatible = "samsung,exynos5420-clock";
>> - reg = <0x10010000 0x30000>;
>> - #clock-cells = <1>;
>> - };
>> -
>> -Example 2: UART controller node that consumes the clock generated by the clock
>> - controller. Refer to the standard clock bindings for information
>> - about 'clocks' and 'clock-names' property.
>> -
>> - serial@13820000 {
>> - compatible = "samsung,exynos4210-uart";
>> - reg = <0x13820000 0x100>;
>> - interrupts = <0 54 0>;
>> - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
>> - clock-names = "uart", "clk_uart_baud0";
>> - };
>> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
>> index cd6567bd8cc7..b0f58a1cf6cb 100644
>> --- a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
>> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
>> @@ -18,7 +18,16 @@ description: |
>>
>> properties:
>> compatible:
>> - const: samsung,exynos5250-clock
>> + oneOf:
>> + - enum:
>> + - samsung,exynos5250-clock
>> + - samsung,exynos5420-clock
>> + - samsung,exynos5800-clock
>> + - items:
>> + - enum:
>> + - samsung,exynos5420-clock
>> + - samsung,exynos5800-clock
>
> Is there a reason these are supported with or without 'syscon'?
>
Yes, the syscon is optional and needed only by the Exynos5422 DMC driver
(exynos5422-dmc.txt/samsung,exynos5422-dmc.yaml with
samsung,exynos5422-dmc compatible). Without that driver, there is no
need for syscon.
Best regards,
Krzysztof
On 17/08/2021 22:24, Rob Herring wrote:
> On Tue, Aug 10, 2021 at 11:31:42AM +0200, Krzysztof Kozlowski wrote:
>> Merge Exynos4210 and Exynos4412 clock controller bindings to existing DT
>> schema.
>>
>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>> ---
>> .../bindings/clock/exynos4-clock.txt | 86 -------------------
>> .../bindings/clock/samsung,exynos-clock.yaml | 29 ++++++-
>> 2 files changed, 28 insertions(+), 87 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/clock/exynos4-clock.txt
>>
>> diff --git a/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/Documentation/devicetree/bindings/clock/exynos4-clock.txt
>> deleted file mode 100644
>> index 17bb11365354..000000000000
>> --- a/Documentation/devicetree/bindings/clock/exynos4-clock.txt
>> +++ /dev/null
>> @@ -1,86 +0,0 @@
>> -* Samsung Exynos4 Clock Controller
>> -
>> -The Exynos4 clock controller generates and supplies clock to various controllers
>> -within the Exynos4 SoC. The clock binding described here is applicable to all
>> -SoC's in the Exynos4 family.
>> -
>> -Required Properties:
>> -
>> -- compatible: should be one of the following.
>> - - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
>> - - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
>> -
>> -- reg: physical base address of the controller and length of memory mapped
>> - region.
>> -
>> -- #clock-cells: should be 1.
>> -
>> -Each clock is assigned an identifier and client nodes can use this identifier
>> -to specify the clock which they consume.
>> -
>> -All available clocks are defined as preprocessor macros in
>> -dt-bindings/clock/exynos4.h header and can be used in device
>> -tree sources.
>> -
>> -Example 1: An example of a clock controller node is listed below.
>> -
>> - clock: clock-controller@10030000 {
>> - compatible = "samsung,exynos4210-clock";
>> - reg = <0x10030000 0x20000>;
>> - #clock-cells = <1>;
>> - };
>> -
>> -Example 2: UART controller node that consumes the clock generated by the clock
>> - controller. Refer to the standard clock bindings for information
>> - about 'clocks' and 'clock-names' property.
>> -
>> - serial@13820000 {
>> - compatible = "samsung,exynos4210-uart";
>> - reg = <0x13820000 0x100>;
>> - interrupts = <0 54 0>;
>> - clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
>> - clock-names = "uart", "clk_uart_baud0";
>> - };
>> -
>> -Exynos4412 SoC contains some additional clocks for FIMC-ISP (Camera ISP)
>> -subsystem. Registers for those clocks are located in the ISP power domain.
>> -Because those registers are also located in a different memory region than
>> -the main clock controller, a separate clock controller has to be defined for
>> -handling them.
>> -
>> -Required Properties:
>> -
>> -- compatible: should be "samsung,exynos4412-isp-clock".
>> -
>> -- reg: physical base address of the ISP clock controller and length of memory
>> - mapped region.
>> -
>> -- #clock-cells: should be 1.
>> -
>> -- clocks: list of the clock controller input clock identifiers,
>> - from common clock bindings, should point to CLK_ACLK200 and
>> - CLK_ACLK400_MCUISP clocks from the main clock controller.
>> -
>> -- clock-names: list of the clock controller input clock names,
>> - as described in clock-bindings.txt, should be "aclk200" and
>> - "aclk400_mcuisp".
>> -
>> -- power-domains: a phandle to ISP power domain node as described by
>> - generic PM domain bindings.
>> -
>> -Example 3: The clock controllers bindings for Exynos4412 SoCs.
>> -
>> - clock: clock-controller@10030000 {
>> - compatible = "samsung,exynos4412-clock";
>> - reg = <0x10030000 0x18000>;
>> - #clock-cells = <1>;
>> - };
>> -
>> - isp_clock: clock-controller@10048000 {
>> - compatible = "samsung,exynos4412-isp-clock";
>> - reg = <0x10048000 0x1000>;
>> - #clock-cells = <1>;
>> - power-domains = <&pd_isp>;
>> - clocks = <&clock CLK_ACLK200>, <&clock CLK_ACLK400_MCUISP>;
>> - clock-names = "aclk200", "aclk400_mcuisp";
>> - };
>> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
>> index c7b07fcd3fa1..ea73201f259b 100644
>> --- a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
>> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml
>> @@ -23,6 +23,9 @@ properties:
>> - samsung,exynos3250-cmu
>> - samsung,exynos3250-cmu-dmc
>> - samsung,exynos3250-cmu-isp
>> + - samsung,exynos4210-clock
>> + - samsung,exynos4412-clock
>> + - samsung,exynos4412-isp-clock
>> - samsung,exynos5250-clock
>> - samsung,exynos5420-clock
>> - samsung,exynos5800-clock
>> @@ -35,11 +38,18 @@ properties:
>> assigned-clocks: true
>> assigned-clock-parents: true
>> assigned-clock-rates: true
>> - clocks: true
>> + clocks:
>> + description: |
>> + For samsung,exynos4412-isp-clock, the input clocks should be CLK_ACLK200
>> + and CLK_ACLK400_MCUISP from the main clock controller.
>> +
>> + clock-names: true
>>
>> "#clock-cells":
>> const: 1
>>
>> + power-domains: true
>> +
>
> How many?
I'll add it.
>
> Now all the flavors can have a power domain? Maybe this should be a
> separate binding given this and the if/then below.
If you ask about the hardware specifically - almost all flavors could
have a power domain.
There are actually several clock controllers in every SoC responsible
for different parts (e.g. display, GPU, audio, video encoder) and most
of them could have a power domain.
However the clock controller bindings and drivers for all ARMv7 Exynos
SoCs were designed as one device with one device node. Inside the driver
spawns sub-controllers but still there is one device node.
Therefore the answer, if you ask about bindings and hardware-driver
model, is that only some of the flavors will have a power domain.
If you think that having to separate bindings, without that "allOf: if:"
below, is simpler then I can split it.
>
>> reg:
>> maxItems: 1
>>
>> @@ -50,6 +60,23 @@ required:
>>
>> additionalProperties: false
>>
>> +allOf:
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + const: samsung,exynos4412-isp-clock
>> + then:
>> + properties:
>> + clock-names:
>> + items:
>> + - const: aclk200
>> + - const: aclk400_mcuisp
>> + required:
>> + - clocks
>> + - clock-names
>> + - power-domains
>> +
>> examples:
>> - |
>> #include <dt-bindings/clock/exynos5250.h>
>> --
>> 2.30.2
>>
>>
Best regards,
Krzysztof
On 17/08/2021 22:26, Rob Herring wrote:
> On Tue, Aug 10, 2021 at 11:31:43AM +0200, Krzysztof Kozlowski wrote:
>> Convert Samsung Exynos Audio SubSystem clock controller bindings to DT
>> schema format using json-schema.
>>
>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>> ---
>> .../bindings/clock/clk-exynos-audss.txt | 103 ------------------
>> .../clock/samsung,exynos-audss-clock.yaml | 79 ++++++++++++++
>> 2 files changed, 79 insertions(+), 103 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
>> create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
>> deleted file mode 100644
>> index 6030afb10b5c..000000000000
>> --- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
>> +++ /dev/null
>> @@ -1,103 +0,0 @@
>> -* Samsung Audio Subsystem Clock Controller
>> -
>> -The Samsung Audio Subsystem clock controller generates and supplies clocks
>> -to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
>> -binding described here is applicable to all SoCs in Exynos family.
>> -
>> -Required Properties:
>> -
>> -- compatible: should be one of the following:
>> - - "samsung,exynos4210-audss-clock" - controller compatible with all Exynos4 SoCs.
>> - - "samsung,exynos5250-audss-clock" - controller compatible with Exynos5250
>> - SoCs.
>> - - "samsung,exynos5410-audss-clock" - controller compatible with Exynos5410
>> - SoCs.
>> - - "samsung,exynos5420-audss-clock" - controller compatible with Exynos5420
>> - SoCs.
>> -- reg: physical base address and length of the controller's register set.
>> -
>> -- #clock-cells: should be 1.
>> -
>> -- clocks:
>> - - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
>> - is used if not specified.
>> - - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
>> - is used if not specified.
>> - - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
>> - specified.
>> - - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
>> - not specified.
>> - - sclk_pcm_in: PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not
>> - specified.
>> -
>> -- clock-names: Aliases for the above clocks. They should be "pll_ref",
>> - "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
>> -
>> -Optional Properties:
>> -
>> - - power-domains: a phandle to respective power domain node as described by
>> - generic PM domain bindings (see power/power_domain.txt for more
>> - information).
>> -
>> -The following is the list of clocks generated by the controller. Each clock is
>> -assigned an identifier and client nodes use this identifier to specify the
>> -clock which they consume. Some of the clocks are available only on a particular
>> -Exynos4 SoC and this is specified where applicable.
>> -
>> -Provided clocks:
>> -
>> -Clock ID SoC (if specific)
>> ------------------------------------------------
>> -
>> -mout_audss 0
>> -mout_i2s 1
>> -dout_srp 2
>> -dout_aud_bus 3
>> -dout_i2s 4
>> -srp_clk 5
>> -i2s_bus 6
>> -sclk_i2s 7
>> -pcm_bus 8
>> -sclk_pcm 9
>> -adma 10 Exynos5420
>> -
>> -Example 1: An example of a clock controller node using the default input
>> - clock names is listed below.
>> -
>> -clock_audss: audss-clock-controller@3810000 {
>> - compatible = "samsung,exynos5250-audss-clock";
>> - reg = <0x03810000 0x0C>;
>> - #clock-cells = <1>;
>> -};
>> -
>> -Example 2: An example of a clock controller node with the input clocks
>> - specified.
>> -
>> -clock_audss: audss-clock-controller@3810000 {
>> - compatible = "samsung,exynos5250-audss-clock";
>> - reg = <0x03810000 0x0C>;
>> - #clock-cells = <1>;
>> - clocks = <&clock 1>, <&clock 7>, <&clock 138>, <&clock 160>,
>> - <&ext_i2s_clk>;
>> - clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
>> -};
>> -
>> -Example 3: I2S controller node that consumes the clock generated by the clock
>> - controller. Refer to the standard clock bindings for information
>> - about 'clocks' and 'clock-names' property.
>> -
>> -i2s0: i2s@3830000 {
>> - compatible = "samsung,i2s-v5";
>> - reg = <0x03830000 0x100>;
>> - dmas = <&pdma0 10
>> - &pdma0 9
>> - &pdma0 8>;
>> - dma-names = "tx", "rx", "tx-sec";
>> - clocks = <&clock_audss EXYNOS_I2S_BUS>,
>> - <&clock_audss EXYNOS_I2S_BUS>,
>> - <&clock_audss EXYNOS_SCLK_I2S>,
>> - <&clock_audss EXYNOS_MOUT_AUDSS>,
>> - <&clock_audss EXYNOS_MOUT_I2S>;
>> - clock-names = "iis", "i2s_opclk0", "i2s_opclk1",
>> - "mout_audss", "mout_i2s";
>> -};
>> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
>> new file mode 100644
>> index 000000000000..d60b29fa22e7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-audss-clock.yaml
>> @@ -0,0 +1,79 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/samsung,exynos-audss-clock.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Samsung Exynos SoC Audio SubSystem clock controller
>> +
>> +maintainers:
>> + - Chanwoo Choi <[email protected]>
>> + - Krzysztof Kozlowski <[email protected]>
>> + - Sylwester Nawrocki <[email protected]>
>> + - Tomasz Figa <[email protected]>
>> +
>> +description: |
>> + All available clocks are defined as preprocessor macros in
>> + include/dt-bindings/clock/exynos-audss-clk.h header.
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - samsung,exynos4210-audss-clock
>> + - samsung,exynos5250-audss-clock
>> + - samsung,exynos5410-audss-clock
>> + - samsung,exynos5420-audss-clock
>> +
>> + clocks:
>> + minItems: 2
>> + items:
>> + - description:
>> + Fixed rate PLL reference clock, parent of mout_audss. "fin_pll" is
>> + used if not specified.
>> + - description:
>> + Input PLL to the AudioSS block, parent of mout_audss. "fout_epll" is
>> + used if not specified.
>> + - description:
>> + Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if not
>> + specified.
>> + - description:
>> + PCM clock, parent of sclk_pcm. "sclk_pcm0" is used if not specified.
>> + - description:
>> + External i2s clock, parent of mout_i2s. "cdclk0" is used if not
>> + specified.
>> +
>> + clock-names:
>> + minItems: 2
>> + items:
>> + - const: pll_ref
>> + - const: pll_in
>> + - const: sclk_audio
>> + - const: sclk_pcm_in
>> + - const: cdclk
>> +
>> + "#clock-cells":
>> + const: 1
>> +
>> + power-domains: true
>
> How many?
>
I'll fix it, thanks for review.
Best regards,
Krzysztof