LinuxLists.cc - [PATCH 0/9] drm/i915/gvt: Constify static structs

2021-12-04 10:55:45

Subject: [PATCH 0/9] drm/i915/gvt: Constify static structs

Constify a number of static structs that are never modified to allow the
compiler to put them in read-only memory. In order to do this, constify a
number of local variables and pointers in structs.

This is most important for structs that contain function pointers, and
the patches for those structs are placed first in the series.

Rikard Falkeborn (9):
drm/i915/gvt: Constify intel_gvt_gtt_pte_ops
drm/i915/gvt: Constify intel_gvt_gtt_pte_ops
drm/i915/gvt: Constify intel_gvt_irq_ops
drm/i915/gvt: Constify intel_gvt_sched_policy_ops
drm/i915/gvt: Constify gvt_mmio_block
drm/i915/gvt: Constify cmd_interrupt_events
drm/i915/gvt: Constify formats
drm/i915/gvt: Constify gtt_type_table_entry
drm/i915/gvt: Constify vgpu_types

drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c | 24 ++++-----
drivers/gpu/drm/i915/gvt/gtt.c | 68 ++++++++++++-------------
drivers/gpu/drm/i915/gvt/gtt.h | 4 +-
drivers/gpu/drm/i915/gvt/gvt.h | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 12 ++---
drivers/gpu/drm/i915/gvt/interrupt.c | 10 ++--
drivers/gpu/drm/i915/gvt/interrupt.h | 2 +-
drivers/gpu/drm/i915/gvt/sched_policy.c | 2 +-
drivers/gpu/drm/i915/gvt/scheduler.h | 2 +-
drivers/gpu/drm/i915/gvt/vgpu.c | 4 +-
11 files changed, 66 insertions(+), 66 deletions(-)

--
2.34.1

2021-12-04 10:55:52

by Rikard Falkeborn

[permalink] [raw]

Subject: [PATCH 1/9] drm/i915/gvt: Constify intel_gvt_gtt_pte_ops

2021-12-04 10:55:56

by Rikard Falkeborn

[permalink] [raw]

Subject: [PATCH 2/9] drm/i915/gvt: Constify intel_gvt_gtt_pte_ops

These are never modified, so make them const to allow the compiler to
put them in read-only memory.

Signed-off-by: Rikard Falkeborn <[email protected]>
---
drivers/gpu/drm/i915/gvt/gtt.c | 62 +++++++++++++++++-----------------
drivers/gpu/drm/i915/gvt/gtt.h | 2 +-
2 files changed, 32 insertions(+), 32 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 6efa48727052..c8cd6bf28ea8 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -499,7 +499,7 @@ DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));

-static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
+static const struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
.get_entry = gtt_get_entry64,
.set_entry = gtt_set_entry64,
.clear_present = gtt_entry_clear_present,
@@ -526,7 +526,7 @@ static const struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
};

/* Update entry type per pse and ips bit. */
-static void update_entry_type_for_real(struct intel_gvt_gtt_pte_ops *pte_ops,
+static void update_entry_type_for_real(const struct intel_gvt_gtt_pte_ops *pte_ops,
struct intel_gvt_gtt_entry *entry, bool ips)
{
switch (entry->type) {
@@ -553,7 +553,7 @@ static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index,
bool guest)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);

@@ -580,7 +580,7 @@ static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index,
bool guest)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
mm->ppgtt_mm.shadow_pdps,
@@ -596,7 +596,7 @@ static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm,
static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

@@ -608,7 +608,7 @@ static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

@@ -619,7 +619,7 @@ static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;

GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);

@@ -629,7 +629,7 @@ static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *entry, unsigned long index)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
unsigned long offset = index;

GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
@@ -655,7 +655,7 @@ static inline int ppgtt_spt_get_entry(
bool guest)
{
struct intel_gvt *gvt = spt->vgpu->gvt;
- struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
int ret;

e->type = get_entry_type(type);
@@ -684,7 +684,7 @@ static inline int ppgtt_spt_set_entry(
bool guest)
{
struct intel_gvt *gvt = spt->vgpu->gvt;
- struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;

if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
return -EINVAL;
@@ -947,7 +947,7 @@ static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
struct intel_gvt_gtt_entry *e)
{
struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
struct intel_vgpu_ppgtt_spt *s;
enum intel_gvt_gtt_type cur_pt_type;

@@ -984,7 +984,7 @@ static inline void ppgtt_invalidate_pte(struct intel_vgpu_ppgtt_spt *spt,
struct intel_gvt_gtt_entry *entry)
{
struct intel_vgpu *vgpu = spt->vgpu;
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
unsigned long pfn;
int type;

@@ -1072,7 +1072,7 @@ static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt);
static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
{
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
struct intel_vgpu_ppgtt_spt *spt = NULL;
bool ips = false;
int ret;
@@ -1136,7 +1136,7 @@ static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
{
- struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;

se->type = ge->type;
se->val64 = ge->val64;
@@ -1159,7 +1159,7 @@ static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
struct intel_gvt_gtt_entry *entry)
{
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
unsigned long pfn;

if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M))
@@ -1176,7 +1176,7 @@ static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
struct intel_gvt_gtt_entry *se)
{
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
struct intel_vgpu_ppgtt_spt *sub_spt;
struct intel_gvt_gtt_entry sub_se;
unsigned long start_gfn;
@@ -1223,7 +1223,7 @@ static int split_64KB_gtt_entry(struct intel_vgpu *vgpu,
struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
struct intel_gvt_gtt_entry *se)
{
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
struct intel_gvt_gtt_entry entry = *se;
unsigned long start_gfn;
dma_addr_t dma_addr;
@@ -1254,7 +1254,7 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
struct intel_gvt_gtt_entry *ge)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
struct intel_gvt_gtt_entry se = *ge;
unsigned long gfn, page_size = PAGE_SIZE;
dma_addr_t dma_addr;
@@ -1308,7 +1308,7 @@ static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt)
{
struct intel_vgpu *vgpu = spt->vgpu;
struct intel_gvt *gvt = vgpu->gvt;
- struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
struct intel_vgpu_ppgtt_spt *s;
struct intel_gvt_gtt_entry se, ge;
unsigned long gfn, i;
@@ -1351,7 +1351,7 @@ static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_ppgtt_spt *spt,
struct intel_gvt_gtt_entry *se, unsigned long index)
{
struct intel_vgpu *vgpu = spt->vgpu;
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
int ret;

trace_spt_guest_change(spt->vgpu->id, "remove", spt,
@@ -1432,7 +1432,7 @@ static int sync_oos_page(struct intel_vgpu *vgpu,
{
const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
struct intel_gvt *gvt = vgpu->gvt;
- struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
struct intel_gvt_gtt_entry old, new;
int index;
@@ -1603,7 +1603,7 @@ static int ppgtt_handle_guest_write_page_table(
{
struct intel_vgpu *vgpu = spt->vgpu;
int type = spt->shadow_page.type;
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
struct intel_gvt_gtt_entry old_se;
int new_present;
int i, ret;
@@ -1720,7 +1720,7 @@ static int ppgtt_handle_guest_write_page_table_bytes(
u64 pa, void *p_data, int bytes)
{
struct intel_vgpu *vgpu = spt->vgpu;
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
struct intel_gvt_gtt_entry we, se;
unsigned long index;
@@ -1785,7 +1785,7 @@ static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
struct intel_vgpu *vgpu = mm->vgpu;
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_gtt *gtt = &gvt->gtt;
- struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
struct intel_gvt_gtt_entry se;
int index;

@@ -1815,7 +1815,7 @@ static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
struct intel_vgpu *vgpu = mm->vgpu;
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_gtt *gtt = &gvt->gtt;
- struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
struct intel_vgpu_ppgtt_spt *spt;
struct intel_gvt_gtt_entry ge, se;
int index, ret;
@@ -2067,7 +2067,7 @@ static inline int ppgtt_get_next_level_entry(struct intel_vgpu_mm *mm,
struct intel_gvt_gtt_entry *e, unsigned long index, bool guest)
{
struct intel_vgpu *vgpu = mm->vgpu;
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
struct intel_vgpu_ppgtt_spt *s;

s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
@@ -2096,7 +2096,7 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma)
{
struct intel_vgpu *vgpu = mm->vgpu;
struct intel_gvt *gvt = vgpu->gvt;
- struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
const struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
unsigned long gpa = INTEL_GVT_INVALID_ADDR;
unsigned long gma_index[4];
@@ -2221,7 +2221,7 @@ int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
static void ggtt_invalidate_pte(struct intel_vgpu *vgpu,
struct intel_gvt_gtt_entry *entry)
{
- struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
unsigned long pfn;

pfn = pte_ops->get_pfn(entry);
@@ -2236,7 +2236,7 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
struct intel_gvt *gvt = vgpu->gvt;
const struct intel_gvt_device_info *info = &gvt->device_info;
struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
- struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
unsigned long gma, gfn;
struct intel_gvt_gtt_entry e = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
@@ -2391,7 +2391,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
{
struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
struct intel_vgpu_gtt *gtt = &vgpu->gtt;
- struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
int page_entry_num = I915_GTT_PAGE_SIZE >>
vgpu->gvt->device_info.gtt_entry_size_shift;
void *scratch_pt;
@@ -2822,7 +2822,7 @@ void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu)
void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old)
{
struct intel_gvt *gvt = vgpu->gvt;
- struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE};
struct intel_gvt_gtt_entry old_entry;
u32 index;
diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
index d0d598322404..a3b0f59ec8bd 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.h
+++ b/drivers/gpu/drm/i915/gvt/gtt.h
@@ -91,7 +91,7 @@ struct intel_gvt_gtt_gma_ops {
};

struct intel_gvt_gtt {
- struct intel_gvt_gtt_pte_ops *pte_ops;
+ const struct intel_gvt_gtt_pte_ops *pte_ops;
const struct intel_gvt_gtt_gma_ops *gma_ops;
int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm);
void (*mm_free_page_table)(struct intel_vgpu_mm *mm);
--
2.34.1

2021-12-04 10:56:05

by Rikard Falkeborn

[permalink] [raw]

Subject: [PATCH 3/9] drm/i915/gvt: Constify intel_gvt_irq_ops

2021-12-04 10:56:08

by Rikard Falkeborn

[permalink] [raw]

Subject: [PATCH 4/9] drm/i915/gvt: Constify intel_gvt_sched_policy_ops

2021-12-04 10:56:19

by Rikard Falkeborn

[permalink] [raw]

Subject: [PATCH 5/9] drm/i915/gvt: Constify gvt_mmio_block

These are never modified, so make them const to allow the compiler to
put it in read-only memory.

Signed-off-by: Rikard Falkeborn <[email protected]>
---
drivers/gpu/drm/i915/gvt/gvt.h | 2 +-
drivers/gpu/drm/i915/gvt/handlers.c | 12 ++++++------
2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
index 0c0615602343..0ebffc327528 100644
--- a/drivers/gpu/drm/i915/gvt/gvt.h
+++ b/drivers/gpu/drm/i915/gvt/gvt.h
@@ -272,7 +272,7 @@ struct intel_gvt_mmio {
/* Value of command write of this reg needs to be patched */
#define F_CMD_WRITE_PATCH (1 << 8)

- struct gvt_mmio_block *mmio_block;
+ const struct gvt_mmio_block *mmio_block;
unsigned int num_mmio_block;

DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index cde0a477fb49..5e85a77da257 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -3627,11 +3627,11 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
return 0;
}

-static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
- unsigned int offset)
+static const struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
+ unsigned int offset)
{
unsigned long device = intel_gvt_get_device_type(gvt);
- struct gvt_mmio_block *block = gvt->mmio.mmio_block;
+ const struct gvt_mmio_block *block = gvt->mmio.mmio_block;
int num = gvt->mmio.num_mmio_block;
int i;

@@ -3670,7 +3670,7 @@ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
* accessible (should have no F_CMD_ACCESS flag).
* otherwise, need to update cmd_reg_handler in cmd_parser.c
*/
-static struct gvt_mmio_block mmio_blocks[] = {
+static const struct gvt_mmio_block mmio_blocks[] = {
{D_SKL_PLUS, _MMIO(DMC_MMIO_START_RANGE), 0x3000, NULL, NULL},
{D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
{D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
@@ -3753,7 +3753,7 @@ int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
void *data)
{
- struct gvt_mmio_block *block = gvt->mmio.mmio_block;
+ const struct gvt_mmio_block *block = gvt->mmio.mmio_block;
struct intel_gvt_mmio_info *e;
int i, j, ret;

@@ -3871,7 +3871,7 @@ int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
struct intel_gvt *gvt = vgpu->gvt;
struct intel_gvt_mmio_info *mmio_info;
- struct gvt_mmio_block *mmio_block;
+ const struct gvt_mmio_block *mmio_block;
gvt_mmio_func func;
int ret;

--
2.34.1

2021-12-04 10:56:26

by Rikard Falkeborn

[permalink] [raw]

Subject: [PATCH 6/9] drm/i915/gvt: Constify cmd_interrupt_events

It is never modified, so make it const to allow the compiler to put it
in read-only memory.

Signed-off-by: Rikard Falkeborn <[email protected]>
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index c4118b808268..ce9307546e7f 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -1144,7 +1144,7 @@ struct cmd_interrupt_event {
int mi_user_interrupt;
};

-static struct cmd_interrupt_event cmd_interrupt_events[] = {
+static const struct cmd_interrupt_event cmd_interrupt_events[] = {
[RCS0] = {
.pipe_control_notify = RCS_PIPE_CONTROL,
.mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
--
2.34.1

2021-12-04 10:56:30

by Rikard Falkeborn

[permalink] [raw]

Subject: [PATCH 7/9] drm/i915/gvt: Constify formats

These are never modified, so make them const to allow the compiler to
put them in read-only memory. WHile at it, make the description const
char* since it is never modified.

Signed-off-by: Rikard Falkeborn <[email protected]>
---
drivers/gpu/drm/i915/gvt/fb_decoder.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 11a8baba6822..3c8736ae8fed 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -40,12 +40,12 @@

#define PRIMARY_FORMAT_NUM 16
struct pixel_format {
- int drm_format; /* Pixel format in DRM definition */
- int bpp; /* Bits per pixel, 0 indicates invalid */
- char *desc; /* The description */
+ int drm_format; /* Pixel format in DRM definition */
+ int bpp; /* Bits per pixel, 0 indicates invalid */
+ const char *desc; /* The description */
};

-static struct pixel_format bdw_pixel_formats[] = {
+static const struct pixel_format bdw_pixel_formats[] = {
{DRM_FORMAT_C8, 8, "8-bit Indexed"},
{DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
{DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
@@ -58,7 +58,7 @@ static struct pixel_format bdw_pixel_formats[] = {
{0, 0, NULL},
};

-static struct pixel_format skl_pixel_formats[] = {
+static const struct pixel_format skl_pixel_formats[] = {
{DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
{DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
{DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
@@ -278,14 +278,14 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,

#define CURSOR_FORMAT_NUM (1 << 6)
struct cursor_mode_format {
- int drm_format; /* Pixel format in DRM definition */
- u8 bpp; /* Bits per pixel; 0 indicates invalid */
- u32 width; /* In pixel */
- u32 height; /* In lines */
- char *desc; /* The description */
+ int drm_format; /* Pixel format in DRM definition */
+ u8 bpp; /* Bits per pixel; 0 indicates invalid */
+ u32 width; /* In pixel */
+ u32 height; /* In lines */
+ const char *desc; /* The description */
};

-static struct cursor_mode_format cursor_pixel_formats[] = {
+static const struct cursor_mode_format cursor_pixel_formats[] = {
{DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
{DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
{DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
@@ -391,7 +391,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,

#define SPRITE_FORMAT_NUM (1 << 3)

-static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
+static const struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
[0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
[0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
[0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
--
2.34.1

2021-12-04 10:57:11

by Rikard Falkeborn

[permalink] [raw]

Subject: [PATCH 9/9] drm/i915/gvt: Constify vgpu_types

It is never modified, so make it const to allow the compiler to put it
in read-only memory. While at it, make name a const char*.

Signed-off-by: Rikard Falkeborn <[email protected]>
---
drivers/gpu/drm/i915/gvt/vgpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
index fa6b92615799..8dddd0a940a1 100644
--- a/drivers/gpu/drm/i915/gvt/vgpu.c
+++ b/drivers/gpu/drm/i915/gvt/vgpu.c
@@ -77,7 +77,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
#define VGPU_WEIGHT(vgpu_num) \
(VGPU_MAX_WEIGHT / (vgpu_num))

-static struct {
+static const struct {
unsigned int low_mm;
unsigned int high_mm;
unsigned int fence;
@@ -88,7 +88,7 @@ static struct {
*/
unsigned int weight;
enum intel_vgpu_edid edid;
- char *name;
+ const char *name;
} vgpu_types[] = {
/* Fixed vGPU type table */
{ MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },
--
2.34.1

2021-12-04 10:57:32

by Rikard Falkeborn

[permalink] [raw]

Subject: [PATCH 8/9] drm/i915/gvt: Constify gtt_type_table_entry

It is never modified, so make it const to allow the compiler to put it
in read-only memory.

Signed-off-by: Rikard Falkeborn <[email protected]>
---
drivers/gpu/drm/i915/gvt/gtt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index c8cd6bf28ea8..614156856f16 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -185,7 +185,7 @@ struct gtt_type_table_entry {
.pse_entry_type = pse_type, \
}

-static struct gtt_type_table_entry gtt_type_table[] = {
+static const struct gtt_type_table_entry gtt_type_table[] = {
GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
GTT_TYPE_INVALID,
--
2.34.1

2021-12-10 08:11:39

by Wang, Zhi A

[permalink] [raw]

Subject: Re: [PATCH 2/9] drm/i915/gvt: Constify intel_gvt_gtt_pte_ops

On 12/4/2021 12:55 PM, Rikard Falkeborn wrote:
> These are never modified, so make them const to allow the compiler to
> put them in read-only memory.
>
> Signed-off-by: Rikard Falkeborn <[email protected]>
> ---
> drivers/gpu/drm/i915/gvt/gtt.c | 62 +++++++++++++++++-----------------
> drivers/gpu/drm/i915/gvt/gtt.h | 2 +-
> 2 files changed, 32 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index 6efa48727052..c8cd6bf28ea8 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -499,7 +499,7 @@ DEFINE_PPGTT_GMA_TO_INDEX(gen8, l3_pdp, (gma >> 30 & 0x3));
> DEFINE_PPGTT_GMA_TO_INDEX(gen8, l4_pdp, (gma >> 30 & 0x1ff));
> DEFINE_PPGTT_GMA_TO_INDEX(gen8, pml4, (gma >> 39 & 0x1ff));
>
> -static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
> +static const struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops = {
> .get_entry = gtt_get_entry64,
> .set_entry = gtt_set_entry64,
> .clear_present = gtt_entry_clear_present,
> @@ -526,7 +526,7 @@ static const struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops = {
> };
>
> /* Update entry type per pse and ips bit. */
> -static void update_entry_type_for_real(struct intel_gvt_gtt_pte_ops *pte_ops,
> +static void update_entry_type_for_real(const struct intel_gvt_gtt_pte_ops *pte_ops,
> struct intel_gvt_gtt_entry *entry, bool ips)
> {
> switch (entry->type) {
> @@ -553,7 +553,7 @@ static void _ppgtt_get_root_entry(struct intel_vgpu_mm *mm,
> struct intel_gvt_gtt_entry *entry, unsigned long index,
> bool guest)
> {
> - struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
>
> GEM_BUG_ON(mm->type != INTEL_GVT_MM_PPGTT);
>
> @@ -580,7 +580,7 @@ static void _ppgtt_set_root_entry(struct intel_vgpu_mm *mm,
> struct intel_gvt_gtt_entry *entry, unsigned long index,
> bool guest)
> {
> - struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
>
> pte_ops->set_entry(guest ? mm->ppgtt_mm.guest_pdps :
> mm->ppgtt_mm.shadow_pdps,
> @@ -596,7 +596,7 @@ static inline void ppgtt_set_shadow_root_entry(struct intel_vgpu_mm *mm,
> static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
> struct intel_gvt_gtt_entry *entry, unsigned long index)
> {
> - struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
>
> GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
>
> @@ -608,7 +608,7 @@ static void ggtt_get_guest_entry(struct intel_vgpu_mm *mm,
> static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
> struct intel_gvt_gtt_entry *entry, unsigned long index)
> {
> - struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
>
> GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
>
> @@ -619,7 +619,7 @@ static void ggtt_set_guest_entry(struct intel_vgpu_mm *mm,
> static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
> struct intel_gvt_gtt_entry *entry, unsigned long index)
> {
> - struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
>
> GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
>
> @@ -629,7 +629,7 @@ static void ggtt_get_host_entry(struct intel_vgpu_mm *mm,
> static void ggtt_set_host_entry(struct intel_vgpu_mm *mm,
> struct intel_gvt_gtt_entry *entry, unsigned long index)
> {
> - struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
> unsigned long offset = index;
>
> GEM_BUG_ON(mm->type != INTEL_GVT_MM_GGTT);
> @@ -655,7 +655,7 @@ static inline int ppgtt_spt_get_entry(
> bool guest)
> {
> struct intel_gvt *gvt = spt->vgpu->gvt;
> - struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
> int ret;
>
> e->type = get_entry_type(type);
> @@ -684,7 +684,7 @@ static inline int ppgtt_spt_set_entry(
> bool guest)
> {
> struct intel_gvt *gvt = spt->vgpu->gvt;
> - struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
>
> if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
> return -EINVAL;
> @@ -947,7 +947,7 @@ static int ppgtt_invalidate_spt_by_shadow_entry(struct intel_vgpu *vgpu,
> struct intel_gvt_gtt_entry *e)
> {
> struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
> - struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> struct intel_vgpu_ppgtt_spt *s;
> enum intel_gvt_gtt_type cur_pt_type;
>
> @@ -984,7 +984,7 @@ static inline void ppgtt_invalidate_pte(struct intel_vgpu_ppgtt_spt *spt,
> struct intel_gvt_gtt_entry *entry)
> {
> struct intel_vgpu *vgpu = spt->vgpu;
> - struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> unsigned long pfn;
> int type;
>
> @@ -1072,7 +1072,7 @@ static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt);
> static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
> struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we)
> {
> - struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> struct intel_vgpu_ppgtt_spt *spt = NULL;
> bool ips = false;
> int ret;
> @@ -1136,7 +1136,7 @@ static struct intel_vgpu_ppgtt_spt *ppgtt_populate_spt_by_guest_entry(
> static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
> struct intel_vgpu_ppgtt_spt *s, struct intel_gvt_gtt_entry *ge)
> {
> - struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
>
> se->type = ge->type;
> se->val64 = ge->val64;
> @@ -1159,7 +1159,7 @@ static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry *se,
> static int is_2MB_gtt_possible(struct intel_vgpu *vgpu,
> struct intel_gvt_gtt_entry *entry)
> {
> - struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> unsigned long pfn;
>
> if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M))
> @@ -1176,7 +1176,7 @@ static int split_2MB_gtt_entry(struct intel_vgpu *vgpu,
> struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
> struct intel_gvt_gtt_entry *se)
> {
> - struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> struct intel_vgpu_ppgtt_spt *sub_spt;
> struct intel_gvt_gtt_entry sub_se;
> unsigned long start_gfn;
> @@ -1223,7 +1223,7 @@ static int split_64KB_gtt_entry(struct intel_vgpu *vgpu,
> struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
> struct intel_gvt_gtt_entry *se)
> {
> - struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> struct intel_gvt_gtt_entry entry = *se;
> unsigned long start_gfn;
> dma_addr_t dma_addr;
> @@ -1254,7 +1254,7 @@ static int ppgtt_populate_shadow_entry(struct intel_vgpu *vgpu,
> struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
> struct intel_gvt_gtt_entry *ge)
> {
> - struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
> struct intel_gvt_gtt_entry se = *ge;
> unsigned long gfn, page_size = PAGE_SIZE;
> dma_addr_t dma_addr;
> @@ -1308,7 +1308,7 @@ static int ppgtt_populate_spt(struct intel_vgpu_ppgtt_spt *spt)
> {
> struct intel_vgpu *vgpu = spt->vgpu;
> struct intel_gvt *gvt = vgpu->gvt;
> - struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
> struct intel_vgpu_ppgtt_spt *s;
> struct intel_gvt_gtt_entry se, ge;
> unsigned long gfn, i;
> @@ -1351,7 +1351,7 @@ static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_ppgtt_spt *spt,
> struct intel_gvt_gtt_entry *se, unsigned long index)
> {
> struct intel_vgpu *vgpu = spt->vgpu;
> - struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> int ret;
>
> trace_spt_guest_change(spt->vgpu->id, "remove", spt,
> @@ -1432,7 +1432,7 @@ static int sync_oos_page(struct intel_vgpu *vgpu,
> {
> const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
> struct intel_gvt *gvt = vgpu->gvt;
> - struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
> struct intel_vgpu_ppgtt_spt *spt = oos_page->spt;
> struct intel_gvt_gtt_entry old, new;
> int index;
> @@ -1603,7 +1603,7 @@ static int ppgtt_handle_guest_write_page_table(
> {
> struct intel_vgpu *vgpu = spt->vgpu;
> int type = spt->shadow_page.type;
> - struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> struct intel_gvt_gtt_entry old_se;
> int new_present;
> int i, ret;
> @@ -1720,7 +1720,7 @@ static int ppgtt_handle_guest_write_page_table_bytes(
> u64 pa, void *p_data, int bytes)
> {
> struct intel_vgpu *vgpu = spt->vgpu;
> - struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
> struct intel_gvt_gtt_entry we, se;
> unsigned long index;
> @@ -1785,7 +1785,7 @@ static void invalidate_ppgtt_mm(struct intel_vgpu_mm *mm)
> struct intel_vgpu *vgpu = mm->vgpu;
> struct intel_gvt *gvt = vgpu->gvt;
> struct intel_gvt_gtt *gtt = &gvt->gtt;
> - struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
> struct intel_gvt_gtt_entry se;
> int index;
>
> @@ -1815,7 +1815,7 @@ static int shadow_ppgtt_mm(struct intel_vgpu_mm *mm)
> struct intel_vgpu *vgpu = mm->vgpu;
> struct intel_gvt *gvt = vgpu->gvt;
> struct intel_gvt_gtt *gtt = &gvt->gtt;
> - struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
> struct intel_vgpu_ppgtt_spt *spt;
> struct intel_gvt_gtt_entry ge, se;
> int index, ret;
> @@ -2067,7 +2067,7 @@ static inline int ppgtt_get_next_level_entry(struct intel_vgpu_mm *mm,
> struct intel_gvt_gtt_entry *e, unsigned long index, bool guest)
> {
> struct intel_vgpu *vgpu = mm->vgpu;
> - struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> struct intel_vgpu_ppgtt_spt *s;
>
> s = intel_vgpu_find_spt_by_mfn(vgpu, ops->get_pfn(e));
> @@ -2096,7 +2096,7 @@ unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm *mm, unsigned long gma)
> {
> struct intel_vgpu *vgpu = mm->vgpu;
> struct intel_gvt *gvt = vgpu->gvt;
> - struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
> const struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
> unsigned long gpa = INTEL_GVT_INVALID_ADDR;
> unsigned long gma_index[4];
> @@ -2221,7 +2221,7 @@ int intel_vgpu_emulate_ggtt_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
> static void ggtt_invalidate_pte(struct intel_vgpu *vgpu,
> struct intel_gvt_gtt_entry *entry)
> {
> - struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
> unsigned long pfn;
>
> pfn = pte_ops->get_pfn(entry);
> @@ -2236,7 +2236,7 @@ static int emulate_ggtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
> struct intel_gvt *gvt = vgpu->gvt;
> const struct intel_gvt_device_info *info = &gvt->device_info;
> struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
> - struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
> unsigned long g_gtt_index = off >> info->gtt_entry_size_shift;
> unsigned long gma, gfn;
> struct intel_gvt_gtt_entry e = {.val64 = 0, .type = GTT_TYPE_GGTT_PTE};
> @@ -2391,7 +2391,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
> {
> struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
> struct intel_vgpu_gtt *gtt = &vgpu->gtt;
> - struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
> int page_entry_num = I915_GTT_PAGE_SIZE >>
> vgpu->gvt->device_info.gtt_entry_size_shift;
> void *scratch_pt;
> @@ -2822,7 +2822,7 @@ void intel_vgpu_invalidate_ppgtt(struct intel_vgpu *vgpu)
> void intel_vgpu_reset_ggtt(struct intel_vgpu *vgpu, bool invalidate_old)
> {
> struct intel_gvt *gvt = vgpu->gvt;
> - struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
> + const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
> struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE};
> struct intel_gvt_gtt_entry old_entry;
> u32 index;
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
> index d0d598322404..a3b0f59ec8bd 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.h
> +++ b/drivers/gpu/drm/i915/gvt/gtt.h
> @@ -91,7 +91,7 @@ struct intel_gvt_gtt_gma_ops {
> };
>
> struct intel_gvt_gtt {
> - struct intel_gvt_gtt_pte_ops *pte_ops;
> + const struct intel_gvt_gtt_pte_ops *pte_ops;
> const struct intel_gvt_gtt_gma_ops *gma_ops;
> int (*mm_alloc_page_table)(struct intel_vgpu_mm *mm);
> void (*mm_free_page_table)(struct intel_vgpu_mm *mm);

Reviewed-by: Zhi Wang <[email protected]>

2021-12-10 08:11:53

by Wang, Zhi A

[permalink] [raw]

Subject: Re: [PATCH 3/9] drm/i915/gvt: Constify intel_gvt_irq_ops

2021-12-10 08:12:09

by Wang, Zhi A

[permalink] [raw]

Subject: Re: [PATCH 4/9] drm/i915/gvt: Constify intel_gvt_sched_policy_ops

2021-12-10 08:12:24

by Wang, Zhi A

[permalink] [raw]

Subject: Re: [PATCH 5/9] drm/i915/gvt: Constify gvt_mmio_block

On 12/4/2021 12:55 PM, Rikard Falkeborn wrote:
> These are never modified, so make them const to allow the compiler to
> put it in read-only memory.
>
> Signed-off-by: Rikard Falkeborn <[email protected]>
> ---
> drivers/gpu/drm/i915/gvt/gvt.h | 2 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 12 ++++++------
> 2 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
> index 0c0615602343..0ebffc327528 100644
> --- a/drivers/gpu/drm/i915/gvt/gvt.h
> +++ b/drivers/gpu/drm/i915/gvt/gvt.h
> @@ -272,7 +272,7 @@ struct intel_gvt_mmio {
> /* Value of command write of this reg needs to be patched */
> #define F_CMD_WRITE_PATCH (1 << 8)
>
> - struct gvt_mmio_block *mmio_block;
> + const struct gvt_mmio_block *mmio_block;
> unsigned int num_mmio_block;
>
> DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index cde0a477fb49..5e85a77da257 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -3627,11 +3627,11 @@ static int init_bxt_mmio_info(struct intel_gvt *gvt)
> return 0;
> }
>
> -static struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
> - unsigned int offset)
> +static const struct gvt_mmio_block *find_mmio_block(struct intel_gvt *gvt,
> + unsigned int offset)
> {
> unsigned long device = intel_gvt_get_device_type(gvt);
> - struct gvt_mmio_block *block = gvt->mmio.mmio_block;
> + const struct gvt_mmio_block *block = gvt->mmio.mmio_block;
> int num = gvt->mmio.num_mmio_block;
> int i;
>
> @@ -3670,7 +3670,7 @@ void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
> * accessible (should have no F_CMD_ACCESS flag).
> * otherwise, need to update cmd_reg_handler in cmd_parser.c
> */
> -static struct gvt_mmio_block mmio_blocks[] = {
> +static const struct gvt_mmio_block mmio_blocks[] = {
> {D_SKL_PLUS, _MMIO(DMC_MMIO_START_RANGE), 0x3000, NULL, NULL},
> {D_ALL, _MMIO(MCHBAR_MIRROR_BASE_SNB), 0x40000, NULL, NULL},
> {D_ALL, _MMIO(VGT_PVINFO_PAGE), VGT_PVINFO_SIZE,
> @@ -3753,7 +3753,7 @@ int intel_gvt_for_each_tracked_mmio(struct intel_gvt *gvt,
> int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
> void *data)
> {
> - struct gvt_mmio_block *block = gvt->mmio.mmio_block;
> + const struct gvt_mmio_block *block = gvt->mmio.mmio_block;
> struct intel_gvt_mmio_info *e;
> int i, j, ret;
>
> @@ -3871,7 +3871,7 @@ int intel_vgpu_mmio_reg_rw(struct intel_vgpu *vgpu, unsigned int offset,
> struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
> struct intel_gvt *gvt = vgpu->gvt;
> struct intel_gvt_mmio_info *mmio_info;
> - struct gvt_mmio_block *mmio_block;
> + const struct gvt_mmio_block *mmio_block;
> gvt_mmio_func func;
> int ret;
>

Reviewed-by: Zhi Wang <[email protected]>

2021-12-10 08:12:39

by Wang, Zhi A

[permalink] [raw]

Subject: Re: [PATCH 6/9] drm/i915/gvt: Constify cmd_interrupt_events

On 12/4/2021 12:55 PM, Rikard Falkeborn wrote:
> It is never modified, so make it const to allow the compiler to put it
> in read-only memory.
>
> Signed-off-by: Rikard Falkeborn <[email protected]>
> ---
> drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index c4118b808268..ce9307546e7f 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -1144,7 +1144,7 @@ struct cmd_interrupt_event {
> int mi_user_interrupt;
> };
>
> -static struct cmd_interrupt_event cmd_interrupt_events[] = {
> +static const struct cmd_interrupt_event cmd_interrupt_events[] = {
> [RCS0] = {
> .pipe_control_notify = RCS_PIPE_CONTROL,
> .mi_flush_dw = INTEL_GVT_EVENT_RESERVED,

Reviewed-by: Zhi Wang <[email protected]>

2021-12-10 08:20:27

by Wang, Zhi A

[permalink] [raw]

Subject: Re: [PATCH 7/9] drm/i915/gvt: Constify formats

On 12/4/2021 12:55 PM, Rikard Falkeborn wrote:
> These are never modified, so make them const to allow the compiler to
> put them in read-only memory. WHile at it, make the description const
> char* since it is never modified.
>
> Signed-off-by: Rikard Falkeborn <[email protected]>
> ---
> drivers/gpu/drm/i915/gvt/fb_decoder.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> index 11a8baba6822..3c8736ae8fed 100644
> --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
> +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> @@ -40,12 +40,12 @@
>
> #define PRIMARY_FORMAT_NUM 16
> struct pixel_format {
> - int drm_format; /* Pixel format in DRM definition */
> - int bpp; /* Bits per pixel, 0 indicates invalid */
> - char *desc; /* The description */
> + int drm_format; /* Pixel format in DRM definition */
> + int bpp; /* Bits per pixel, 0 indicates invalid */
> + const char *desc; /* The description */
> };
Thanks so much for this. According to the code of i915, we prefer using
one space as seperator.
>
> -static struct pixel_format bdw_pixel_formats[] = {
> +static const struct pixel_format bdw_pixel_formats[] = {
> {DRM_FORMAT_C8, 8, "8-bit Indexed"},
> {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
> {DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
> @@ -58,7 +58,7 @@ static struct pixel_format bdw_pixel_formats[] = {
> {0, 0, NULL},
> };
>
> -static struct pixel_format skl_pixel_formats[] = {
> +static const struct pixel_format skl_pixel_formats[] = {
> {DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
> {DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
> {DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
> @@ -278,14 +278,14 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
>
> #define CURSOR_FORMAT_NUM (1 << 6)
> struct cursor_mode_format {
> - int drm_format; /* Pixel format in DRM definition */
> - u8 bpp; /* Bits per pixel; 0 indicates invalid */
> - u32 width; /* In pixel */
> - u32 height; /* In lines */
> - char *desc; /* The description */
> + int drm_format; /* Pixel format in DRM definition */
> + u8 bpp; /* Bits per pixel; 0 indicates invalid */
> + u32 width; /* In pixel */
> + u32 height; /* In lines */
> + const char *desc; /* The description */
> };
The same comment as above.
> -static struct cursor_mode_format cursor_pixel_formats[] = {
> +static const struct cursor_mode_format cursor_pixel_formats[] = {
> {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
> {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
> {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
> @@ -391,7 +391,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
>
> #define SPRITE_FORMAT_NUM (1 << 3)
>
> -static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
> +static const struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
> [0x0] = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
> [0x1] = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
> [0x2] = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},

The rest of the patch looks good to me.

2021-12-10 08:20:41

by Wang, Zhi A

[permalink] [raw]

Subject: Re: [PATCH 8/9] drm/i915/gvt: Constify gtt_type_table_entry

On 12/4/2021 12:55 PM, Rikard Falkeborn wrote:
> It is never modified, so make it const to allow the compiler to put it
> in read-only memory.
>
> Signed-off-by: Rikard Falkeborn <[email protected]>
> ---
> drivers/gpu/drm/i915/gvt/gtt.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
> index c8cd6bf28ea8..614156856f16 100644
> --- a/drivers/gpu/drm/i915/gvt/gtt.c
> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
> @@ -185,7 +185,7 @@ struct gtt_type_table_entry {
> .pse_entry_type = pse_type, \
> }
>
> -static struct gtt_type_table_entry gtt_type_table[] = {
> +static const struct gtt_type_table_entry gtt_type_table[] = {
> GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
> GTT_TYPE_PPGTT_ROOT_L4_ENTRY,
> GTT_TYPE_INVALID,

Reviewed-by: Zhi Wang <[email protected]>

2021-12-10 08:20:59

by Wang, Zhi A

[permalink] [raw]

Subject: Re: [PATCH 9/9] drm/i915/gvt: Constify vgpu_types

On 12/4/2021 12:55 PM, Rikard Falkeborn wrote:
> It is never modified, so make it const to allow the compiler to put it
> in read-only memory. While at it, make name a const char*.
>
> Signed-off-by: Rikard Falkeborn <[email protected]>
> ---
> drivers/gpu/drm/i915/gvt/vgpu.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
> index fa6b92615799..8dddd0a940a1 100644
> --- a/drivers/gpu/drm/i915/gvt/vgpu.c
> +++ b/drivers/gpu/drm/i915/gvt/vgpu.c
> @@ -77,7 +77,7 @@ void populate_pvinfo_page(struct intel_vgpu *vgpu)
> #define VGPU_WEIGHT(vgpu_num) \
> (VGPU_MAX_WEIGHT / (vgpu_num))
>
> -static struct {
> +static const struct {
> unsigned int low_mm;
> unsigned int high_mm;
> unsigned int fence;
> @@ -88,7 +88,7 @@ static struct {
> */
> unsigned int weight;
> enum intel_vgpu_edid edid;
> - char *name;
> + const char *name;
> } vgpu_types[] = {
> /* Fixed vGPU type table */
> { MB_TO_BYTES(64), MB_TO_BYTES(384), 4, VGPU_WEIGHT(8), GVT_EDID_1024_768, "8" },

Reviewed-by: Zhi Wang <[email protected]>

2021-12-10 08:59:35

by Wang, Zhi A

[permalink] [raw]

Subject: Re: [PATCH 1/9] drm/i915/gvt: Constify intel_gvt_gtt_pte_ops

2021-12-10 09:01:01

by Wang, Zhi A

[permalink] [raw]

Subject: Re: [PATCH 0/9] drm/i915/gvt: Constify static structs

On 12/4/2021 12:55 PM, Rikard Falkeborn wrote:
> Constify a number of static structs that are never modified to allow the
> compiler to put them in read-only memory. In order to do this, constify a
> number of local variables and pointers in structs.
>
> This is most important for structs that contain function pointers, and
> the patches for those structs are placed first in the series.
>
> Rikard Falkeborn (9):
> drm/i915/gvt: Constify intel_gvt_gtt_pte_ops
> drm/i915/gvt: Constify intel_gvt_gtt_pte_ops
> drm/i915/gvt: Constify intel_gvt_irq_ops
> drm/i915/gvt: Constify intel_gvt_sched_policy_ops
> drm/i915/gvt: Constify gvt_mmio_block
> drm/i915/gvt: Constify cmd_interrupt_events
> drm/i915/gvt: Constify formats
> drm/i915/gvt: Constify gtt_type_table_entry
> drm/i915/gvt: Constify vgpu_types
>
> drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
> drivers/gpu/drm/i915/gvt/fb_decoder.c | 24 ++++-----
> drivers/gpu/drm/i915/gvt/gtt.c | 68 ++++++++++++-------------
> drivers/gpu/drm/i915/gvt/gtt.h | 4 +-
> drivers/gpu/drm/i915/gvt/gvt.h | 2 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 12 ++---
> drivers/gpu/drm/i915/gvt/interrupt.c | 10 ++--
> drivers/gpu/drm/i915/gvt/interrupt.h | 2 +-
> drivers/gpu/drm/i915/gvt/sched_policy.c | 2 +-
> drivers/gpu/drm/i915/gvt/scheduler.h | 2 +-
> drivers/gpu/drm/i915/gvt/vgpu.c | 4 +-
> 11 files changed, 66 insertions(+), 66 deletions(-)
>
Thanks so much for the contribuition. You only need to refine the PATCH
2 a little bit and re-send it.

2021-12-12 13:21:16

by Rikard Falkeborn

[permalink] [raw]

Subject: Re: [PATCH 7/9] drm/i915/gvt: Constify formats

On Fri, Dec 10, 2021 at 08:20:22AM +0000, Wang, Zhi A wrote:
> On 12/4/2021 12:55 PM, Rikard Falkeborn wrote:
> > These are never modified, so make them const to allow the compiler to
> > put them in read-only memory. WHile at it, make the description const
> > char* since it is never modified.
> >
> > Signed-off-by: Rikard Falkeborn <[email protected]>
> > ---
> > drivers/gpu/drm/i915/gvt/fb_decoder.c | 24 ++++++++++++------------
> > 1 file changed, 12 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> > index 11a8baba6822..3c8736ae8fed 100644
> > --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
> > +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> > @@ -40,12 +40,12 @@
> >
> > #define PRIMARY_FORMAT_NUM 16
> > struct pixel_format {
> > - int drm_format; /* Pixel format in DRM definition */
> > - int bpp; /* Bits per pixel, 0 indicates invalid */
> > - char *desc; /* The description */
> > + int drm_format; /* Pixel format in DRM definition */
> > + int bpp; /* Bits per pixel, 0 indicates invalid */
> > + const char *desc; /* The description */
> > };
> Thanks so much for this. According to the code of i915, we prefer using
> one space as seperator.
> >

Thanks for reviewing. Just to clarify, is this how you want it to look:

struct pixel_format {
int drm_format; /* Pixel format in DRM definition */
int bpp; /* Bits per pixel, 0 indicates invalid */
char *desc; /* The description */
};

Rikard

2021-12-12 13:25:42

by Rikard Falkeborn

[permalink] [raw]

Subject: Re: [PATCH 0/9] drm/i915/gvt: Constify static structs

On Fri, Dec 10, 2021 at 09:00:56AM +0000, Wang, Zhi A wrote:
> On 12/4/2021 12:55 PM, Rikard Falkeborn wrote:
> > Constify a number of static structs that are never modified to allow the
> > compiler to put them in read-only memory. In order to do this, constify a
> > number of local variables and pointers in structs.
> >
> > This is most important for structs that contain function pointers, and
> > the patches for those structs are placed first in the series.
> >
> > Rikard Falkeborn (9):
> > drm/i915/gvt: Constify intel_gvt_gtt_pte_ops
> > drm/i915/gvt: Constify intel_gvt_gtt_pte_ops
> > drm/i915/gvt: Constify intel_gvt_irq_ops
> > drm/i915/gvt: Constify intel_gvt_sched_policy_ops
> > drm/i915/gvt: Constify gvt_mmio_block
> > drm/i915/gvt: Constify cmd_interrupt_events
> > drm/i915/gvt: Constify formats
> > drm/i915/gvt: Constify gtt_type_table_entry
> > drm/i915/gvt: Constify vgpu_types
> >
> > drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
> > drivers/gpu/drm/i915/gvt/fb_decoder.c | 24 ++++-----
> > drivers/gpu/drm/i915/gvt/gtt.c | 68 ++++++++++++-------------
> > drivers/gpu/drm/i915/gvt/gtt.h | 4 +-
> > drivers/gpu/drm/i915/gvt/gvt.h | 2 +-
> > drivers/gpu/drm/i915/gvt/handlers.c | 12 ++---
> > drivers/gpu/drm/i915/gvt/interrupt.c | 10 ++--
> > drivers/gpu/drm/i915/gvt/interrupt.h | 2 +-
> > drivers/gpu/drm/i915/gvt/sched_policy.c | 2 +-
> > drivers/gpu/drm/i915/gvt/scheduler.h | 2 +-
> > drivers/gpu/drm/i915/gvt/vgpu.c | 4 +-
> > 11 files changed, 66 insertions(+), 66 deletions(-)
> >
> Thanks so much for the contribuition. You only need to refine the PATCH
> 2 a little bit and re-send it.
>

Thanks for reviewing. Just to clarify, did you mean patch 7 (since
that's the one you commented on)? And is it enough to send just that
patch or do you want the entire series resent?

Rikard

2021-12-16 19:21:26

by Wang, Zhi A

[permalink] [raw]

Subject: Re: [PATCH 0/9] drm/i915/gvt: Constify static structs

On 12/12/2021 3:25 PM, Rikard Falkeborn worte:
> On Fri, Dec 10, 2021 at 09:00:56AM +0000, Wang, Zhi A wrote:
>> On 12/4/2021 12:55 PM, Rikard Falkeborn wrote:
>>> Constify a number of static structs that are never modified to allow the
>>> compiler to put them in read-only memory. In order to do this, constify a
>>> number of local variables and pointers in structs.
>>>
>>> This is most important for structs that contain function pointers, and
>>> the patches for those structs are placed first in the series.
>>>
>>> Rikard Falkeborn (9):
>>> drm/i915/gvt: Constify intel_gvt_gtt_pte_ops
>>> drm/i915/gvt: Constify intel_gvt_gtt_pte_ops
>>> drm/i915/gvt: Constify intel_gvt_irq_ops
>>> drm/i915/gvt: Constify intel_gvt_sched_policy_ops
>>> drm/i915/gvt: Constify gvt_mmio_block
>>> drm/i915/gvt: Constify cmd_interrupt_events
>>> drm/i915/gvt: Constify formats
>>> drm/i915/gvt: Constify gtt_type_table_entry
>>> drm/i915/gvt: Constify vgpu_types
>>>
>>> drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +-
>>> drivers/gpu/drm/i915/gvt/fb_decoder.c | 24 ++++-----
>>> drivers/gpu/drm/i915/gvt/gtt.c | 68 ++++++++++++-------------
>>> drivers/gpu/drm/i915/gvt/gtt.h | 4 +-
>>> drivers/gpu/drm/i915/gvt/gvt.h | 2 +-
>>> drivers/gpu/drm/i915/gvt/handlers.c | 12 ++---
>>> drivers/gpu/drm/i915/gvt/interrupt.c | 10 ++--
>>> drivers/gpu/drm/i915/gvt/interrupt.h | 2 +-
>>> drivers/gpu/drm/i915/gvt/sched_policy.c | 2 +-
>>> drivers/gpu/drm/i915/gvt/scheduler.h | 2 +-
>>> drivers/gpu/drm/i915/gvt/vgpu.c | 4 +-
>>> 11 files changed, 66 insertions(+), 66 deletions(-)
>>>
>> Thanks so much for the contribuition. You only need to refine the PATCH
>> 2 a little bit and re-send it.
>>
> Thanks for reviewing. Just to clarify, did you mean patch 7 (since
> that's the one you commented on)? And is it enough to send just that
> patch or do you want the entire series resent?
>
> Rikard

Hi Rikard, no worries then. I have already corrected them and queue
them in the gvt-next branch, you can double check them if you like. They
are going through a QA test cycle first and later start their journey to
the upstream. All good. :) Thanks so much for the contribution again.

Zhi.