Add support for sm8150 in the Qualcomm Limits Management Hardware(LMh)
driver. Also add required device tree entries and dt-binding.
Thara Gopinath (3):
thermal: qcom: lmh: Add support for sm8150
arm64: dts: qcom: sm8150: Add support for LMh node
dt-bindings: thermal: Add sm8150 compatible string for LMh
.../devicetree/bindings/thermal/qcom-lmh.yaml | 1 +
arch/arm64/boot/dts/qcom/sm8150.dtsi | 24 +++++++
drivers/thermal/qcom/lmh.c | 62 +++++++++++--------
3 files changed, 60 insertions(+), 27 deletions(-)
--
2.25.1
Add compatible to support LMh for sm8150 SoC.
sm8150 does not require explicit enabling for various LMh subsystems.
Add a variable indicating the same as match data which is set for sdm845.
Execute the piece of code enabling various LMh subsystems only if
enable algorithm match data is present.
Signed-off-by: Thara Gopinath <[email protected]>
---
v2->v3:
- use of_device_get_match_data to get the data from match table
rather than using of_match_device and subsequent ->data, as per
Bjorn's review comments.
- Minor fixes as per Bjorn's review comments.
v1->v2:
- Added LMH_ENABLE_ALGOS of_device_id match data to indicate
whether LMh subsytems need explicit enabling or not.
drivers/thermal/qcom/lmh.c | 62 +++++++++++++++++++++-----------------
1 file changed, 35 insertions(+), 27 deletions(-)
diff --git a/drivers/thermal/qcom/lmh.c b/drivers/thermal/qcom/lmh.c
index eafa7526eb8b..c7f91cbdccc7 100644
--- a/drivers/thermal/qcom/lmh.c
+++ b/drivers/thermal/qcom/lmh.c
@@ -28,6 +28,8 @@
#define LMH_REG_DCVS_INTR_CLR 0x8
+#define LMH_ENABLE_ALGOS 1
+
struct lmh_hw_data {
void __iomem *base;
struct irq_domain *domain;
@@ -90,6 +92,7 @@ static int lmh_probe(struct platform_device *pdev)
struct device_node *cpu_node;
struct lmh_hw_data *lmh_data;
int temp_low, temp_high, temp_arm, cpu_id, ret;
+ unsigned int enable_alg;
u32 node_id;
lmh_data = devm_kzalloc(dev, sizeof(*lmh_data), GFP_KERNEL);
@@ -141,32 +144,36 @@ static int lmh_probe(struct platform_device *pdev)
if (!qcom_scm_lmh_dcvsh_available())
return -EINVAL;
- ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1,
- LMH_NODE_DCVS, node_id, 0);
- if (ret)
- dev_err(dev, "Error %d enabling current subfunction\n", ret);
-
- ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_REL, LMH_ALGO_MODE_ENABLE, 1,
- LMH_NODE_DCVS, node_id, 0);
- if (ret)
- dev_err(dev, "Error %d enabling reliability subfunction\n", ret);
-
- ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_BCL, LMH_ALGO_MODE_ENABLE, 1,
- LMH_NODE_DCVS, node_id, 0);
- if (ret)
- dev_err(dev, "Error %d enabling BCL subfunction\n", ret);
-
- ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_ALGO_MODE_ENABLE, 1,
- LMH_NODE_DCVS, node_id, 0);
- if (ret) {
- dev_err(dev, "Error %d enabling thermal subfunction\n", ret);
- return ret;
- }
-
- ret = qcom_scm_lmh_profile_change(0x1);
- if (ret) {
- dev_err(dev, "Error %d changing profile\n", ret);
- return ret;
+ enable_alg = (uintptr_t)of_device_get_match_data(dev);
+
+ if (enable_alg) {
+ ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1,
+ LMH_NODE_DCVS, node_id, 0);
+ if (ret)
+ dev_err(dev, "Error %d enabling current subfunction\n", ret);
+
+ ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_REL, LMH_ALGO_MODE_ENABLE, 1,
+ LMH_NODE_DCVS, node_id, 0);
+ if (ret)
+ dev_err(dev, "Error %d enabling reliability subfunction\n", ret);
+
+ ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_BCL, LMH_ALGO_MODE_ENABLE, 1,
+ LMH_NODE_DCVS, node_id, 0);
+ if (ret)
+ dev_err(dev, "Error %d enabling BCL subfunction\n", ret);
+
+ ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_ALGO_MODE_ENABLE, 1,
+ LMH_NODE_DCVS, node_id, 0);
+ if (ret) {
+ dev_err(dev, "Error %d enabling thermal subfunction\n", ret);
+ return ret;
+ }
+
+ ret = qcom_scm_lmh_profile_change(0x1);
+ if (ret) {
+ dev_err(dev, "Error %d changing profile\n", ret);
+ return ret;
+ }
}
/* Set default thermal trips */
@@ -213,7 +220,8 @@ static int lmh_probe(struct platform_device *pdev)
}
static const struct of_device_id lmh_table[] = {
- { .compatible = "qcom,sdm845-lmh", },
+ { .compatible = "qcom,sdm845-lmh", .data = (void *)LMH_ENABLE_ALGOS},
+ { .compatible = "qcom,sm8150-lmh", },
{}
};
MODULE_DEVICE_TABLE(of, lmh_table);
--
2.25.1
Extend the LMh dt binding document to include compatible string
supporting sm8150 SoC.
Signed-off-by: Thara Gopinath <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/thermal/qcom-lmh.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
index 289e9a845600..a9b7388ca9ac 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
@@ -19,6 +19,7 @@ properties:
compatible:
enum:
- qcom,sdm845-lmh
+ - qcom,sm8150-lmh
reg:
items:
--
2.25.1
Add LMh nodes for cpu cluster0 and cpu cluster1 for sm8150 SoC.
Signed-off-by: Thara Gopinath <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 81b4ff2cc4cd..e755d7ab78dd 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -3650,6 +3650,30 @@ cpufreq_hw: cpufreq@18323000 {
#freq-domain-cells = <1>;
};
+ lmh_cluster1: lmh@18350800 {
+ compatible = "qcom,sm8150-lmh";
+ reg = <0 0x18350800 0 0x400>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&CPU4>;
+ qcom,lmh-temp-arm-millicelsius = <60000>;
+ qcom,lmh-temp-low-millicelsius = <84500>;
+ qcom,lmh-temp-high-millicelsius = <85000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ lmh_cluster0: lmh@18358800 {
+ compatible = "qcom,sm8150-lmh";
+ reg = <0 0x18358800 0 0x400>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ cpus = <&CPU0>;
+ qcom,lmh-temp-arm-millicelsius = <60000>;
+ qcom,lmh-temp-low-millicelsius = <84500>;
+ qcom,lmh-temp-high-millicelsius = <85000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
wifi: wifi@18800000 {
compatible = "qcom,wcn3990-wifi";
reg = <0 0x18800000 0 0x800000>;
--
2.25.1
On Thu 06 Jan 09:31 PST 2022, Thara Gopinath wrote:
> Add compatible to support LMh for sm8150 SoC.
> sm8150 does not require explicit enabling for various LMh subsystems.
> Add a variable indicating the same as match data which is set for sdm845.
> Execute the piece of code enabling various LMh subsystems only if
> enable algorithm match data is present.
>
> Signed-off-by: Thara Gopinath <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Thanks Thara,
Bjorn
> ---
>
> v2->v3:
> - use of_device_get_match_data to get the data from match table
> rather than using of_match_device and subsequent ->data, as per
> Bjorn's review comments.
> - Minor fixes as per Bjorn's review comments.
>
> v1->v2:
> - Added LMH_ENABLE_ALGOS of_device_id match data to indicate
> whether LMh subsytems need explicit enabling or not.
> drivers/thermal/qcom/lmh.c | 62 +++++++++++++++++++++-----------------
> 1 file changed, 35 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/thermal/qcom/lmh.c b/drivers/thermal/qcom/lmh.c
> index eafa7526eb8b..c7f91cbdccc7 100644
> --- a/drivers/thermal/qcom/lmh.c
> +++ b/drivers/thermal/qcom/lmh.c
> @@ -28,6 +28,8 @@
>
> #define LMH_REG_DCVS_INTR_CLR 0x8
>
> +#define LMH_ENABLE_ALGOS 1
> +
> struct lmh_hw_data {
> void __iomem *base;
> struct irq_domain *domain;
> @@ -90,6 +92,7 @@ static int lmh_probe(struct platform_device *pdev)
> struct device_node *cpu_node;
> struct lmh_hw_data *lmh_data;
> int temp_low, temp_high, temp_arm, cpu_id, ret;
> + unsigned int enable_alg;
> u32 node_id;
>
> lmh_data = devm_kzalloc(dev, sizeof(*lmh_data), GFP_KERNEL);
> @@ -141,32 +144,36 @@ static int lmh_probe(struct platform_device *pdev)
> if (!qcom_scm_lmh_dcvsh_available())
> return -EINVAL;
>
> - ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1,
> - LMH_NODE_DCVS, node_id, 0);
> - if (ret)
> - dev_err(dev, "Error %d enabling current subfunction\n", ret);
> -
> - ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_REL, LMH_ALGO_MODE_ENABLE, 1,
> - LMH_NODE_DCVS, node_id, 0);
> - if (ret)
> - dev_err(dev, "Error %d enabling reliability subfunction\n", ret);
> -
> - ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_BCL, LMH_ALGO_MODE_ENABLE, 1,
> - LMH_NODE_DCVS, node_id, 0);
> - if (ret)
> - dev_err(dev, "Error %d enabling BCL subfunction\n", ret);
> -
> - ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_ALGO_MODE_ENABLE, 1,
> - LMH_NODE_DCVS, node_id, 0);
> - if (ret) {
> - dev_err(dev, "Error %d enabling thermal subfunction\n", ret);
> - return ret;
> - }
> -
> - ret = qcom_scm_lmh_profile_change(0x1);
> - if (ret) {
> - dev_err(dev, "Error %d changing profile\n", ret);
> - return ret;
> + enable_alg = (uintptr_t)of_device_get_match_data(dev);
> +
> + if (enable_alg) {
> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_CRNT, LMH_ALGO_MODE_ENABLE, 1,
> + LMH_NODE_DCVS, node_id, 0);
> + if (ret)
> + dev_err(dev, "Error %d enabling current subfunction\n", ret);
> +
> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_REL, LMH_ALGO_MODE_ENABLE, 1,
> + LMH_NODE_DCVS, node_id, 0);
> + if (ret)
> + dev_err(dev, "Error %d enabling reliability subfunction\n", ret);
> +
> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_BCL, LMH_ALGO_MODE_ENABLE, 1,
> + LMH_NODE_DCVS, node_id, 0);
> + if (ret)
> + dev_err(dev, "Error %d enabling BCL subfunction\n", ret);
> +
> + ret = qcom_scm_lmh_dcvsh(LMH_SUB_FN_THERMAL, LMH_ALGO_MODE_ENABLE, 1,
> + LMH_NODE_DCVS, node_id, 0);
> + if (ret) {
> + dev_err(dev, "Error %d enabling thermal subfunction\n", ret);
> + return ret;
> + }
> +
> + ret = qcom_scm_lmh_profile_change(0x1);
> + if (ret) {
> + dev_err(dev, "Error %d changing profile\n", ret);
> + return ret;
> + }
> }
>
> /* Set default thermal trips */
> @@ -213,7 +220,8 @@ static int lmh_probe(struct platform_device *pdev)
> }
>
> static const struct of_device_id lmh_table[] = {
> - { .compatible = "qcom,sdm845-lmh", },
> + { .compatible = "qcom,sdm845-lmh", .data = (void *)LMH_ENABLE_ALGOS},
> + { .compatible = "qcom,sm8150-lmh", },
> {}
> };
> MODULE_DEVICE_TABLE(of, lmh_table);
> --
> 2.25.1
>
On Thu 06 Jan 09:31 PST 2022, Thara Gopinath wrote:
> Extend the LMh dt binding document to include compatible string
> supporting sm8150 SoC.
>
> Signed-off-by: Thara Gopinath <[email protected]>
> Acked-by: Rob Herring <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Regards,
Bjorn
> ---
> Documentation/devicetree/bindings/thermal/qcom-lmh.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
> index 289e9a845600..a9b7388ca9ac 100644
> --- a/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
> +++ b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
> @@ -19,6 +19,7 @@ properties:
> compatible:
> enum:
> - qcom,sdm845-lmh
> + - qcom,sm8150-lmh
>
> reg:
> items:
> --
> 2.25.1
>
On Thu 06 Jan 09:31 PST 2022, Thara Gopinath wrote:
> Add LMh nodes for cpu cluster0 and cpu cluster1 for sm8150 SoC.
>
> Signed-off-by: Thara Gopinath <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Daniel, will you please apply patch 1 and 3 through your tree and I can
take this through the qcom dts tree.
Thanks,
Bjorn
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 81b4ff2cc4cd..e755d7ab78dd 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -3650,6 +3650,30 @@ cpufreq_hw: cpufreq@18323000 {
> #freq-domain-cells = <1>;
> };
>
> + lmh_cluster1: lmh@18350800 {
> + compatible = "qcom,sm8150-lmh";
> + reg = <0 0x18350800 0 0x400>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + cpus = <&CPU4>;
> + qcom,lmh-temp-arm-millicelsius = <60000>;
> + qcom,lmh-temp-low-millicelsius = <84500>;
> + qcom,lmh-temp-high-millicelsius = <85000>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + lmh_cluster0: lmh@18358800 {
> + compatible = "qcom,sm8150-lmh";
> + reg = <0 0x18358800 0 0x400>;
> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + cpus = <&CPU0>;
> + qcom,lmh-temp-arm-millicelsius = <60000>;
> + qcom,lmh-temp-low-millicelsius = <84500>;
> + qcom,lmh-temp-high-millicelsius = <85000>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> wifi: wifi@18800000 {
> compatible = "qcom,wcn3990-wifi";
> reg = <0 0x18800000 0 0x800000>;
> --
> 2.25.1
>
On Thu, 6 Jan 2022 12:31:37 -0500, Thara Gopinath wrote:
> Add LMh nodes for cpu cluster0 and cpu cluster1 for sm8150 SoC.
>
>
Applied, thanks!
[2/3] arm64: dts: qcom: sm8150: Add support for LMh node
commit: 2ffcfe791d05e19feb105419efc030fc8ae1e527
Best regards,
--
Bjorn Andersson <[email protected]>
On 07/01/2022 00:32, Bjorn Andersson wrote:
> On Thu 06 Jan 09:31 PST 2022, Thara Gopinath wrote:
>
>> Extend the LMh dt binding document to include compatible string
>> supporting sm8150 SoC.
>>
>> Signed-off-by: Thara Gopinath <[email protected]>
>> Acked-by: Rob Herring <[email protected]>
Applied, thanks
--
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On 07/01/2022 00:32, Bjorn Andersson wrote:
> On Thu 06 Jan 09:31 PST 2022, Thara Gopinath wrote:
>
>> Add compatible to support LMh for sm8150 SoC.
>> sm8150 does not require explicit enabling for various LMh subsystems.
>> Add a variable indicating the same as match data which is set for sdm845.
>> Execute the piece of code enabling various LMh subsystems only if
>> enable algorithm match data is present.
>>
>> Signed-off-by: Thara Gopinath <[email protected]>
>
> Reviewed-by: Bjorn Andersson <[email protected]>
Applied, thanks
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog