This try to complete the ipq8064 dtsi and introduce 2 new dtsi
ipq8064-v2 and ipq8065. While some node are still missing (cpufreq node,
l2 scale node, fab scale node) this would add most of the missing node
to make ipq8064 actually usable.
Some of the changes are the fix for the pci IO that cause any secondary
wifi card with ath10k to fail init.
Adds regulators definition for RPM.
Adds many missing gsbi nodes used by all the devices.
Enable the usb phy by default as they are actually enabled internally by
xlate only if the dwc3 driver is used.
Add opp table and declare idle state for ipq8064.
Fix some dtc warning.
This also add the ipq8064-v2.0 dtsi and the ipq8065 dtsi used by more
recent devices based on this SoC.
Ansuel Smith (17):
ARM: dts: qcom: add multiple missing pin definition for ipq8064
ARM: dts: qcom: add gsbi6 missing definition for ipq8064
ARM: dts: qcom: add missing rpm regulators and cells for ipq8064
ARM: dts: qcom: add missing snps,dwmac compatible for gmac ipq8064
ARM: dts: qcom: enable usb phy by default for ipq8064
ARM: dts: qcom: reduce pci IO size to 64K for ipq8064
ARM: dts: qcom: fix dtc warning for missing #address-cells for ipq8064
ARM: dts: qcom: add smem node for ipq8064
ARM: dts: qcom: add saw for l2 cache and kraitcc for ipq8064
ARM: dts: qcom: add sic non secure node for ipq8064
ARM: dts: qcom: fix and add some missing gsbi node for ipq8064
ARM: dts: qcom: add opp table for cpu and l2 for ipq8064
ARM: dts: qcom: add speedbin efuse nvmem binding
ARM: dts: qcom: add multiple missing binding for cpu and l2 for
ipq8064
ARM: dts: qcom: remove redundant binding from ipq8064 rb3011 dts
ARM: dts: qcom: add ipq8064-v2.0 dtsi
ARM: dts: qcom: add ipq8065 dtsi
arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 17 --
arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 70 +++++
arch/arm/boot/dts/qcom-ipq8064.dtsi | 344 +++++++++++++++++++++-
arch/arm/boot/dts/qcom-ipq8065.dtsi | 168 +++++++++++
4 files changed, 568 insertions(+), 31 deletions(-)
create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
create mode 100644 arch/arm/boot/dts/qcom-ipq8065.dtsi
--
2.33.1
Add missing definition for mdio0 pins used for gpio-bitbang driver,i2c4
pins and rgmii2 pins for ipq8064.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 34 +++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 11481313bdb6..cc6ca9013ab1 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -382,6 +382,15 @@ mux {
};
};
+ i2c4_pins: i2c4_pinmux {
+ mux {
+ pins = "gpio12", "gpio13";
+ function = "gsbi4";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ };
+
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
@@ -424,6 +433,8 @@ mux {
pullups {
pins = "gpio39";
+ function = "nand";
+ drive-strength = <10>;
bias-pull-up;
};
@@ -431,9 +442,32 @@ hold {
pins = "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45",
"gpio46", "gpio47";
+ function = "nand";
+ drive-strength = <10>;
bias-bus-hold;
};
};
+
+ mdio0_pins: mdio0_pins {
+ mux {
+ pins = "gpio0", "gpio1";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ rgmii2_pins: rgmii2_pins {
+ mux {
+ pins = "gpio27", "gpio28", "gpio29",
+ "gpio30", "gpio31", "gpio32",
+ "gpio51", "gpio52", "gpio59",
+ "gpio60", "gpio61", "gpio62";
+ function = "rgmii2";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
};
intc: interrupt-controller@2000000 {
--
2.33.1
Add gsbi6 missing definition for ipq8064.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index cc6ca9013ab1..094125605bea 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -665,6 +665,33 @@ spi@1a280000 {
};
};
+ gsbi6: gsbi@16500000 {
+ status = "disabled";
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <6>;
+ reg = <0x16500000 0x100>;
+ clocks = <&gcc GSBI6_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+
+ gsbi6_i2c: i2c@16580000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16580000 0x1000>;
+ interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
gsbi7: gsbi@16600000 {
status = "disabled";
compatible = "qcom,gsbi-v1.0.0";
--
2.33.1
Add missing snps,dwmac compatible for gmac ipq8064 dtsi.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 824cf13dd037..7cf85b4f6ec8 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1061,7 +1061,7 @@ stmmac_axi_setup: stmmac-axi-config {
gmac0: ethernet@37000000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37000000 0x200000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -1085,7 +1085,7 @@ gmac0: ethernet@37000000 {
gmac1: ethernet@37200000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37200000 0x200000>;
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -1109,7 +1109,7 @@ gmac1: ethernet@37200000 {
gmac2: ethernet@37400000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37400000 0x200000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
@@ -1133,7 +1133,7 @@ gmac2: ethernet@37400000 {
gmac3: ethernet@37600000 {
device_type = "network";
- compatible = "qcom,ipq806x-gmac";
+ compatible = "qcom,ipq806x-gmac", "snps,dwmac";
reg = <0x37600000 0x200000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq";
--
2.33.1
Enable usb phy by default. When the usb phy were pushed, half of them
were flagged as disabled by mistake. Fix this to correctly init dwc3
node on any ipq8064 based SoC.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 7cf85b4f6ec8..441309bb64c8 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -1161,8 +1161,6 @@ hs_phy_0: phy@100f8800 {
clocks = <&gcc USB30_0_UTMI_CLK>;
clock-names = "ref";
#phy-cells = <0>;
-
- status = "disabled";
};
ss_phy_0: phy@100f8830 {
@@ -1171,8 +1169,6 @@ ss_phy_0: phy@100f8830 {
clocks = <&gcc USB30_0_MASTER_CLK>;
clock-names = "ref";
#phy-cells = <0>;
-
- status = "disabled";
};
usb3_0: usb3@100f8800 {
--
2.33.1
Add cells definition for rpm node and add missing regulators for the 4
regulator present on ipq8064. There regulators are controlled by rpm and
to correctly works gsbi4_i2c require to be NEVER disabled or rpm will
reject any regulator change request.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 35 +++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 094125605bea..824cf13dd037 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -829,10 +829,45 @@ rpm: rpm@108000 {
clocks = <&gcc RPM_MSG_RAM_H_CLK>;
clock-names = "ram";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
rpmcc: clock-controller {
compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
#clock-cells = <1>;
};
+
+ regulators {
+ compatible = "qcom,rpm-smb208-regulators";
+
+ smb208_s1a: s1a {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s1b: s1b {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2a: s2a {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2b: s2b {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+ };
};
tcsr: syscon@1a400000 {
--
2.33.1
The current value for pci IO is problematic for ath10k wifi card
commonly connected to ipq8064 SoC.
The current value is probably a typo and is actually uncommon to find
1MB IO space even on a x86 arch. Also with recent changes to the pci
driver, pci1 and pci2 now fails to function as any connected device
fails any reg read/write. Reduce this to 64K as it should be more than
enough and 3 * 64K of total IO space doesn't exceed the IO_SPACE_LIMIT
hardcoded for the ARM arch.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 441309bb64c8..c8763997e0f7 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -904,7 +904,7 @@ pcie0: pci@1b500000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
+ ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
@@ -955,7 +955,7 @@ pcie1: pci@1b700000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
+ ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
@@ -1006,7 +1006,7 @@ pcie2: pci@1b900000 {
#address-cells = <3>;
#size-cells = <2>;
- ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
+ ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
--
2.33.1
Add missing smem node for ipq8064.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 856968a96498..8c2d4dac0ebd 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -892,6 +892,11 @@ lcc: clock-controller@28000000 {
#reset-cells = <1>;
};
+ sfpb_mutex_block: syscon@1200600 {
+ compatible = "syscon";
+ reg = <0x01200600 0x100>;
+ };
+
pcie0: pci@1b500000 {
compatible = "qcom,pcie-ipq8064";
reg = <0x1b500000 0x1000
@@ -1316,4 +1321,17 @@ sdcc3: mmc@12180000 {
};
};
};
+
+ sfpb_mutex: sfpb-mutex {
+ compatible = "qcom,sfpb-mutex";
+ syscon = <&sfpb_mutex_block 4 4>;
+
+ #hwlock-cells = <1>;
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem>;
+ hwlocks = <&sfpb_mutex 3>;
+ };
};
--
2.33.1
Add saw compatible for l2 cache and kraitcc node for ipq8064 dtsi.
Also declare clock-output-names for acc0 and acc1.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 8c2d4dac0ebd..a45e4c799b27 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -504,11 +504,13 @@ IRQ_TYPE_EDGE_RISING)>,
acc0: clock-controller@2088000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+ clock-output-names = "acpu0_aux";
};
acc1: clock-controller@2098000 {
compatible = "qcom,kpss-acc-v1";
reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+ clock-output-names = "acpu1_aux";
};
adm_dma: dma-controller@18300000 {
@@ -532,17 +534,23 @@ adm_dma: dma-controller@18300000 {
};
saw0: regulator@2089000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
regulator;
};
saw1: regulator@2099000 {
- compatible = "qcom,saw2";
+ compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
regulator;
};
+ saw_l2: regulator@02012000 {
+ compatible = "qcom,saw2", "syscon";
+ reg = <0x02012000 0x1000>;
+ regulator;
+ };
+
gsbi2: gsbi@12480000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <2>;
@@ -885,6 +893,11 @@ l2cc: clock-controller@2011000 {
clock-output-names = "acpu_l2_aux";
};
+ kraitcc: clock-controller {
+ compatible = "qcom,krait-cc-v1";
+ #clock-cells = <1>;
+ };
+
lcc: clock-controller@28000000 {
compatible = "qcom,lcc-ipq8064";
reg = <0x28000000 0x1000>;
--
2.33.1
Add some tag for gsbi to make them usable for ipq8064 SoC. Add missing
gsbi7 i2c node and gsbi1 node.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 50 ++++++++++++++++++++++++++++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index b82beb297291..6f9075489e58 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -556,6 +556,41 @@ sic_non_secure: sic-non-secure@12100000 {
reg = <0x12100000 0x10000>;
};
+ gsbi1: gsbi@12440000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ cell-index = <1>;
+ reg = <0x12440000 0x100>;
+ clocks = <&gcc GSBI1_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ status = "disabled";
+
+ syscon-tcsr = <&tcsr>;
+
+ gsbi1_serial: serial@12450000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x12450000 0x100>,
+ <0x12400000 0x03>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+ };
+
+ gsbi1_i2c: i2c@12460000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x12460000 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
gsbi2: gsbi@12480000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <2>;
@@ -579,7 +614,7 @@ gsbi2_serial: serial@12490000 {
status = "disabled";
};
- i2c@124a0000 {
+ gsbi2_i2c: i2c@124a0000 {
compatible = "qcom,i2c-qup-v1.1.1";
reg = <0x124a0000 0x1000>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
@@ -728,6 +763,19 @@ gsbi7_serial: serial@16640000 {
clock-names = "core", "iface";
status = "disabled";
};
+
+ gsbi7_i2c: i2c@16680000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x16680000 0x1000>;
+ interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
+ clock-names = "core", "iface";
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
rng@1a500000 {
--
2.33.1
Add missing sic non secure node for ipq8064.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index a45e4c799b27..b82beb297291 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -551,6 +551,11 @@ saw_l2: regulator@02012000 {
regulator;
};
+ sic_non_secure: sic-non-secure@12100000 {
+ compatible = "syscon";
+ reg = <0x12100000 0x10000>;
+ };
+
gsbi2: gsbi@12480000 {
compatible = "qcom,gsbi-v1.0.0";
cell-index = <2>;
--
2.33.1
Fix dtc warning for missing #address-cells for ipq8064.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index c8763997e0f7..856968a96498 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -352,6 +352,7 @@ qcom_pinmux: pinmux@800000 {
gpio-ranges = <&qcom_pinmux 0 0 69>;
#gpio-cells = <2>;
interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
@@ -473,6 +474,7 @@ mux {
intc: interrupt-controller@2000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <3>;
reg = <0x02000000 0x1000>,
<0x02002000 0x1000>;
--
2.33.1
Add multiple binding for cpu node, l2 node and add idle-states
definition for ipq8064 dtsi.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 1e6297d6f302..34f4fc249a52 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -30,6 +30,16 @@ cpu0: cpu@0 {
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
+ clocks = <&kraitcc 0>, <&kraitcc 4>;
+ clock-names = "cpu", "l2";
+ clock-latency = <100000>;
+ cpu-supply = <&smb208_s2a>;
+ operating-points-v2 = <&opp_table0>;
+ voltage-tolerance = <5>;
+ cooling-min-state = <0>;
+ cooling-max-state = <10>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SPC>;
};
cpu1: cpu@1 {
@@ -40,11 +50,37 @@ cpu1: cpu@1 {
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
+ clocks = <&kraitcc 1>, <&kraitcc 4>;
+ clock-names = "cpu", "l2";
+ clock-latency = <100000>;
+ cpu-supply = <&smb208_s2b>;
+ operating-points-v2 = <&opp_table0>;
+ voltage-tolerance = <5>;
+ cooling-min-state = <0>;
+ cooling-max-state = <10>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SPC>;
+ };
+
+ idle-states {
+ CPU_SPC: spc {
+ compatible = "qcom,idle-state-spc";
+ status = "disabled";
+ entry-latency-us = <400>;
+ exit-latency-us = <900>;
+ min-residency-us = <3000>;
+ };
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
+ qcom,saw = <&saw_l2>;
+
+ clocks = <&kraitcc 4>;
+ clock-names = "l2";
+ l2-supply = <&smb208_s1a>;
+ operating-points-v2 = <&opp_table_l2>;
};
};
--
2.33.1
Add opp table for cpu and l2 cache. The l2 cache won't work as it would
require a dedicated cpufreq driver to scale cache with core.
Opp-level is set based on the logic of
0: idle level
1: normal level
2: turbo level
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++
1 file changed, 99 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 6f9075489e58..1e6297d6f302 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -48,6 +48,105 @@ L2: l2-cache {
};
};
+ opp_table_l2: opp_table_l2 {
+ compatible = "operating-points-v2";
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <100000>;
+ opp-level = <0>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1150000>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+ };
+
+ opp_table0: opp_table0 {
+ compatible = "operating-points-v2-kryo-cpu";
+ nvmem-cells = <&speedbin_efuse>;
+
+ /*
+ * Voltage thresholds are <target min max>
+ */
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <0>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <1>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
+ opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
+ opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+ };
+
thermal-zones {
sensor0-thermal {
polling-delay-passive = <0>;
--
2.33.1
Add speedbin efuse nvmem binding needed for the opp table for the CPU
freqs.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 1e6297d6f302..a1a809134d9e 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -956,6 +956,9 @@ tsens_calib: calib@400 {
tsens_calib_backup: calib_backup@410 {
reg = <0x410 0xb>;
};
+ speedbin_efuse: speedbin@0c0 {
+ reg = <0x0c0 0x4>;
+ };
};
gcc: clock-controller@900000 {
--
2.33.1
Mdio0_pins are now declared in ipq8064 dtsi. Usb phy are enabled by
default.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
index 596d129d4a95..d495b81b587b 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
@@ -255,10 +255,6 @@ &gsbi7_serial {
status = "okay";
};
-&hs_phy_1 {
- status = "okay";
-};
-
&nand {
status = "okay";
@@ -305,15 +301,6 @@ mux {
};
};
- mdio0_pins: mdio0_pins {
- mux {
- pins = "gpio0", "gpio1";
- function = "gpio";
- drive-strength = <8>;
- bias-disable;
- };
- };
-
mdio1_pins: mdio1_pins {
mux {
pins = "gpio10", "gpio11";
@@ -354,10 +341,6 @@ mux {
};
};
-&ss_phy_1 {
- status = "okay";
-};
-
&usb3_1 {
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
--
2.33.1
Mdio0_pins are now declared in ipq8064 dtsi. Usb phy are enabled by
default.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 17 -----------------
1 file changed, 17 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
index 596d129d4a95..d495b81b587b 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
@@ -255,10 +255,6 @@ &gsbi7_serial {
status = "okay";
};
-&hs_phy_1 {
- status = "okay";
-};
-
&nand {
status = "okay";
@@ -305,15 +301,6 @@ mux {
};
};
- mdio0_pins: mdio0_pins {
- mux {
- pins = "gpio0", "gpio1";
- function = "gpio";
- drive-strength = <8>;
- bias-disable;
- };
- };
-
mdio1_pins: mdio1_pins {
mux {
pins = "gpio10", "gpio11";
@@ -354,10 +341,6 @@ mux {
};
};
-&ss_phy_1 {
- status = "okay";
-};
-
&usb3_1 {
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
--
2.33.1
Many devices are based on the v2.0 of the ipq8064 SoC. Main difference
is a change in the pci compatible and different way to configre the usb
phy.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 70 ++++++++++++++++++++++++
1 file changed, 70 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
new file mode 100644
index 000000000000..c082c3cd1a19
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-ipq8064.dtsi"
+
+/ {
+ aliases {
+ serial0 = &gsbi4_serial;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rsvd@41200000 {
+ reg = <0x41200000 0x300000>;
+ no-map;
+ };
+ };
+};
+
+&gsbi4 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+
+ serial@16340000 {
+ status = "okay";
+ };
+ /*
+ * The i2c device on gsbi4 should not be enabled.
+ * On ipq806x designs gsbi4 i2c is meant for exclusive
+ * RPM usage. Turning this on in kernel manifests as
+ * i2c failure for the RPM.
+ */
+};
+
+&CPU_SPC {
+ status = "okay";
+};
+
+&pcie0 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie1 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie2 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&sata {
+ ports-implemented = <0x1>;
+};
+
+&ss_phy_0 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};
+
+&ss_phy_1 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};
--
2.33.1
Add multiple binding for cpu node, l2 node and add idle-states
definition for ipq8064 dtsi.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 36 +++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index a1a809134d9e..e4a2b95699c7 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -30,6 +30,16 @@ cpu0: cpu@0 {
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
+ clocks = <&kraitcc 0>, <&kraitcc 4>;
+ clock-names = "cpu", "l2";
+ clock-latency = <100000>;
+ cpu-supply = <&smb208_s2a>;
+ operating-points-v2 = <&opp_table0>;
+ voltage-tolerance = <5>;
+ cooling-min-state = <0>;
+ cooling-max-state = <10>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SPC>;
};
cpu1: cpu@1 {
@@ -40,11 +50,37 @@ cpu1: cpu@1 {
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
+ clocks = <&kraitcc 1>, <&kraitcc 4>;
+ clock-names = "cpu", "l2";
+ clock-latency = <100000>;
+ cpu-supply = <&smb208_s2b>;
+ operating-points-v2 = <&opp_table0>;
+ voltage-tolerance = <5>;
+ cooling-min-state = <0>;
+ cooling-max-state = <10>;
+ #cooling-cells = <2>;
+ cpu-idle-states = <&CPU_SPC>;
+ };
+
+ idle-states {
+ CPU_SPC: spc {
+ compatible = "qcom,idle-state-spc";
+ status = "disabled";
+ entry-latency-us = <400>;
+ exit-latency-us = <900>;
+ min-residency-us = <3000>;
+ };
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
+ qcom,saw = <&saw_l2>;
+
+ clocks = <&kraitcc 4>;
+ clock-names = "l2";
+ l2-supply = <&smb208_s1a>;
+ operating-points-v2 = <&opp_table_l2>;
};
};
--
2.33.1
Many devices are based on the v2.0 of the ipq8064 SoC. Main difference
is a change in the pci compatible and different way to configre the usb
phy.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 70 ++++++++++++++++++++++++
1 file changed, 70 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
new file mode 100644
index 000000000000..c082c3cd1a19
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-ipq8064.dtsi"
+
+/ {
+ aliases {
+ serial0 = &gsbi4_serial;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rsvd@41200000 {
+ reg = <0x41200000 0x300000>;
+ no-map;
+ };
+ };
+};
+
+&gsbi4 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+
+ serial@16340000 {
+ status = "okay";
+ };
+ /*
+ * The i2c device on gsbi4 should not be enabled.
+ * On ipq806x designs gsbi4 i2c is meant for exclusive
+ * RPM usage. Turning this on in kernel manifests as
+ * i2c failure for the RPM.
+ */
+};
+
+&CPU_SPC {
+ status = "okay";
+};
+
+&pcie0 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie1 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie2 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&sata {
+ ports-implemented = <0x1>;
+};
+
+&ss_phy_0 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};
+
+&ss_phy_1 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};
--
2.33.1
Many device are based on ipq8065 SoC. Ipq8065 is an evolution of the
ipq8064 SoC (also named ipq8064-v3.0 from qsdk) that has all the
improvement from ipq8064-v2.0 with the addition of a more powerful CPU
that can now be clocked to 1.7Ghz, a quicker L2 cache that can be
clocked to 1.4Ghz. It also shipped with more powerful regulators to
provide the required voltage to the CPUs and L2.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8065.dtsi | 168 ++++++++++++++++++++++++++++
1 file changed, 168 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq8065.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom-ipq8065.dtsi
new file mode 100644
index 000000000000..817d723b0c88
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-ipq8064.dtsi"
+
+/ {
+ model = "Qualcomm IPQ8065";
+ compatible = "qcom,ipq8065", "qcom,ipq8064";
+
+ aliases {
+ serial0 = &gsbi4_serial;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rsvd@41200000 {
+ reg = <0x41200000 0x300000>;
+ no-map;
+ };
+ };
+};
+
+&gsbi4 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+
+ serial@16340000 {
+ status = "okay";
+ };
+ /*
+ * The i2c device on gsbi4 should not be enabled.
+ * On ipq806x designs gsbi4 i2c is meant for exclusive
+ * RPM usage. Turning this on in kernel manifests as
+ * i2c failure for the RPM.
+ */
+};
+
+&pcie0 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie1 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie2 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&sata {
+ ports-implemented = <0x1>;
+};
+
+&smb208_s2a {
+ regulator-min-microvolt = <775000>;
+ regulator-max-microvolt = <1275000>;
+};
+
+&smb208_s2b {
+ regulator-min-microvolt = <775000>;
+ regulator-max-microvolt = <1275000>;
+};
+
+&ss_phy_0 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};
+
+&ss_phy_1 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};
+
+&opp_table_l2 {
+ /delete-node/opp-1200000000;
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <1150000>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+};
+
+&opp_table0 {
+ /*
+ * On ipq8065 1.2 ghz freq is not present
+ * Remove it to make cpufreq work and not
+ * complain for missing definition
+ */
+
+ /delete-node/opp-1200000000;
+
+ /*
+ * Voltage thresholds are <target min max>
+ */
+ opp-384000000 {
+ opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>;
+ opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>;
+ };
+
+ opp-600000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>;
+ opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>;
+ };
+
+ opp-800000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>;
+ };
+
+ opp-1000000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>;
+ };
+
+ opp-1400000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>;
+ opp-level = <1>;
+ };
+
+ opp-1725000000 {
+ opp-hz = /bits/ 64 <1725000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>;
+ opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>;
+ opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>;
+ opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+};
--
2.33.1
Many device are based on ipq8065 SoC. Ipq8065 is an evolution of the
ipq8064 SoC (also named ipq8064-v3.0 from qsdk) that has all the
improvement from ipq8064-v2.0 with the addition of a more powerful CPU
that can now be clocked to 1.7Ghz, a quicker L2 cache that can be
clocked to 1.4Ghz. It also shipped with more powerful regulators to
provide the required voltage to the CPUs and L2.
Signed-off-by: Ansuel Smith <[email protected]>
---
arch/arm/boot/dts/qcom-ipq8065.dtsi | 168 ++++++++++++++++++++++++++++
1 file changed, 168 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq8065.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom-ipq8065.dtsi
new file mode 100644
index 000000000000..817d723b0c88
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8065.dtsi
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-ipq8064.dtsi"
+
+/ {
+ model = "Qualcomm IPQ8065";
+ compatible = "qcom,ipq8065", "qcom,ipq8064";
+
+ aliases {
+ serial0 = &gsbi4_serial;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ rsvd@41200000 {
+ reg = <0x41200000 0x300000>;
+ no-map;
+ };
+ };
+};
+
+&gsbi4 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "okay";
+
+ serial@16340000 {
+ status = "okay";
+ };
+ /*
+ * The i2c device on gsbi4 should not be enabled.
+ * On ipq806x designs gsbi4 i2c is meant for exclusive
+ * RPM usage. Turning this on in kernel manifests as
+ * i2c failure for the RPM.
+ */
+};
+
+&pcie0 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie1 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&pcie2 {
+ compatible = "qcom,pcie-ipq8064-v2";
+};
+
+&sata {
+ ports-implemented = <0x1>;
+};
+
+&smb208_s2a {
+ regulator-min-microvolt = <775000>;
+ regulator-max-microvolt = <1275000>;
+};
+
+&smb208_s2b {
+ regulator-min-microvolt = <775000>;
+ regulator-max-microvolt = <1275000>;
+};
+
+&ss_phy_0 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};
+
+&ss_phy_1 {
+ qcom,rx-eq = <2>;
+ qcom,tx-deamp_3_5db = <32>;
+ qcom,mpll = <5>;
+};
+
+&opp_table_l2 {
+ /delete-node/opp-1200000000;
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <1150000>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+};
+
+&opp_table0 {
+ /*
+ * On ipq8065 1.2 ghz freq is not present
+ * Remove it to make cpufreq work and not
+ * complain for missing definition
+ */
+
+ /delete-node/opp-1200000000;
+
+ /*
+ * Voltage thresholds are <target min max>
+ */
+ opp-384000000 {
+ opp-microvolt-speed0-pvs0-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs1-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs4-v0 = <875000 831250 918750>;
+ opp-microvolt-speed0-pvs5-v0 = <825000 783750 866250>;
+ opp-microvolt-speed0-pvs6-v0 = <775000 736250 813750>;
+ };
+
+ opp-600000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs2-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs3-v0 = <925000 878750 971250>;
+ opp-microvolt-speed0-pvs4-v0 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs5-v0 = <850000 807500 892500>;
+ opp-microvolt-speed0-pvs6-v0 = <800000 760000 840000>;
+ };
+
+ opp-800000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs2-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs3-v0 = <975000 926250 1023750>;
+ opp-microvolt-speed0-pvs4-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs5-v0 = <900000 855000 945000>;
+ opp-microvolt-speed0-pvs6-v0 = <850000 807500 892500>;
+ };
+
+ opp-1000000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs2-v0 = <1050000 997500 1102500>;
+ opp-microvolt-speed0-pvs3-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs4-v0 = <1000000 950000 1050000>;
+ opp-microvolt-speed0-pvs5-v0 = <950000 902500 997500>;
+ opp-microvolt-speed0-pvs6-v0 = <900000 855000 945000>;
+ };
+
+ opp-1400000000 {
+ opp-microvolt-speed0-pvs0-v0 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs1-v0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
+ opp-microvolt-speed0-pvs3-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs4-v0 = <1075000 1021250 1128750>;
+ opp-microvolt-speed0-pvs5-v0 = <1025000 973750 1076250>;
+ opp-microvolt-speed0-pvs6-v0 = <975000 926250 1023750>;
+ opp-level = <1>;
+ };
+
+ opp-1725000000 {
+ opp-hz = /bits/ 64 <1725000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1262500 1199375 1325625>;
+ opp-microvolt-speed0-pvs1-v0 = <1225000 1163750 1286250>;
+ opp-microvolt-speed0-pvs2-v0 = <1200000 1140000 1260000>;
+ opp-microvolt-speed0-pvs3-v0 = <1175000 1116250 1233750>;
+ opp-microvolt-speed0-pvs4-v0 = <1150000 1092500 1207500>;
+ opp-microvolt-speed0-pvs5-v0 = <1100000 1045000 1155000>;
+ opp-microvolt-speed0-pvs6-v0 = <1050000 997500 1102500>;
+ opp-supported-hw = <0x1>;
+ clock-latency-ns = <100000>;
+ opp-level = <2>;
+ };
+};
--
2.33.1
On Mon 17 Jan 19:20 CST 2022, Ansuel Smith wrote:
> Add opp table for cpu and l2 cache. The l2 cache won't work as it would
> require a dedicated cpufreq driver to scale cache with core.
>
Are you saying that the L2 cache frequency scaling doesn't work so you
put it there for completeness sake, or that it doesn't work without this
patch?
Could you please rewrite this to make it clear in the git history?
Thanks,
Bjorn
> Opp-level is set based on the logic of
> 0: idle level
> 1: normal level
> 2: turbo level
>
> Signed-off-by: Ansuel Smith <[email protected]>
> ---
> arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++
> 1 file changed, 99 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> index 6f9075489e58..1e6297d6f302 100644
> --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> @@ -48,6 +48,105 @@ L2: l2-cache {
> };
> };
>
> + opp_table_l2: opp_table_l2 {
> + compatible = "operating-points-v2";
> +
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + opp-microvolt = <1100000>;
> + clock-latency-ns = <100000>;
> + opp-level = <0>;
> + };
> +
> + opp-1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-microvolt = <1100000>;
> + clock-latency-ns = <100000>;
> + opp-level = <1>;
> + };
> +
> + opp-1200000000 {
> + opp-hz = /bits/ 64 <1200000000>;
> + opp-microvolt = <1150000>;
> + clock-latency-ns = <100000>;
> + opp-level = <2>;
> + };
> + };
> +
> + opp_table0: opp_table0 {
> + compatible = "operating-points-v2-kryo-cpu";
> + nvmem-cells = <&speedbin_efuse>;
> +
> + /*
> + * Voltage thresholds are <target min max>
> + */
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
> + opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
> + opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
> + opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <100000>;
> + opp-level = <0>;
> + };
> +
> + opp-600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
> + opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
> + opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
> + opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <100000>;
> + opp-level = <1>;
> + };
> +
> + opp-800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
> + opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
> + opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
> + opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <100000>;
> + opp-level = <1>;
> + };
> +
> + opp-1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
> + opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
> + opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
> + opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <100000>;
> + opp-level = <1>;
> + };
> +
> + opp-1200000000 {
> + opp-hz = /bits/ 64 <1200000000>;
> + opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
> + opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
> + opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
> + opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <100000>;
> + opp-level = <2>;
> + };
> +
> + opp-1400000000 {
> + opp-hz = /bits/ 64 <1400000000>;
> + opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
> + opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
> + opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
> + opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <100000>;
> + opp-level = <2>;
> + };
> + };
> +
> thermal-zones {
> sensor0-thermal {
> polling-delay-passive = <0>;
> --
> 2.33.1
>
On Mon 17 Jan 19:20 CST 2022, Ansuel Smith wrote:
> This try to complete the ipq8064 dtsi and introduce 2 new dtsi
> ipq8064-v2 and ipq8065. While some node are still missing (cpufreq node,
> l2 scale node, fab scale node) this would add most of the missing node
> to make ipq8064 actually usable.
>
> Some of the changes are the fix for the pci IO that cause any secondary
> wifi card with ath10k to fail init.
> Adds regulators definition for RPM.
> Adds many missing gsbi nodes used by all the devices.
> Enable the usb phy by default as they are actually enabled internally by
> xlate only if the dwc3 driver is used.
> Add opp table and declare idle state for ipq8064.
> Fix some dtc warning.
>
> This also add the ipq8064-v2.0 dtsi and the ipq8065 dtsi used by more
> recent devices based on this SoC.
>
From the look of the series I suspect that you format-patch'ed a series
with 16 patches, then fixed something and re-ran it now with 17 patches.
Can you please resubmit the series to make it clear what you would like
me to apply. (Preferably with that one commit message clarified)
Regards,
Bjorn
> Ansuel Smith (17):
> ARM: dts: qcom: add multiple missing pin definition for ipq8064
> ARM: dts: qcom: add gsbi6 missing definition for ipq8064
> ARM: dts: qcom: add missing rpm regulators and cells for ipq8064
> ARM: dts: qcom: add missing snps,dwmac compatible for gmac ipq8064
> ARM: dts: qcom: enable usb phy by default for ipq8064
> ARM: dts: qcom: reduce pci IO size to 64K for ipq8064
> ARM: dts: qcom: fix dtc warning for missing #address-cells for ipq8064
> ARM: dts: qcom: add smem node for ipq8064
> ARM: dts: qcom: add saw for l2 cache and kraitcc for ipq8064
> ARM: dts: qcom: add sic non secure node for ipq8064
> ARM: dts: qcom: fix and add some missing gsbi node for ipq8064
> ARM: dts: qcom: add opp table for cpu and l2 for ipq8064
> ARM: dts: qcom: add speedbin efuse nvmem binding
> ARM: dts: qcom: add multiple missing binding for cpu and l2 for
> ipq8064
> ARM: dts: qcom: remove redundant binding from ipq8064 rb3011 dts
> ARM: dts: qcom: add ipq8064-v2.0 dtsi
> ARM: dts: qcom: add ipq8065 dtsi
>
> arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 17 --
> arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi | 70 +++++
> arch/arm/boot/dts/qcom-ipq8064.dtsi | 344 +++++++++++++++++++++-
> arch/arm/boot/dts/qcom-ipq8065.dtsi | 168 +++++++++++
> 4 files changed, 568 insertions(+), 31 deletions(-)
> create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v2.0.dtsi
> create mode 100644 arch/arm/boot/dts/qcom-ipq8065.dtsi
>
> --
> 2.33.1
>
On Mon 17 Jan 19:20 CST 2022, Ansuel Smith wrote:
> Add cells definition for rpm node and add missing regulators for the 4
> regulator present on ipq8064. There regulators are controlled by rpm and
> to correctly works gsbi4_i2c require to be NEVER disabled or rpm will
> reject any regulator change request.
>
Is the SMB208 mandatory on all ipq8064 designs, or should this be pushed
out to the device dts?
Regards,
Bjorn
> Signed-off-by: Ansuel Smith <[email protected]>
> ---
> arch/arm/boot/dts/qcom-ipq8064.dtsi | 35 +++++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> index 094125605bea..824cf13dd037 100644
> --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> @@ -829,10 +829,45 @@ rpm: rpm@108000 {
> clocks = <&gcc RPM_MSG_RAM_H_CLK>;
> clock-names = "ram";
>
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> rpmcc: clock-controller {
> compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
> #clock-cells = <1>;
> };
> +
> + regulators {
> + compatible = "qcom,rpm-smb208-regulators";
> +
> + smb208_s1a: s1a {
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1150000>;
> +
> + qcom,switch-mode-frequency = <1200000>;
> + };
> +
> + smb208_s1b: s1b {
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1150000>;
> +
> + qcom,switch-mode-frequency = <1200000>;
> + };
> +
> + smb208_s2a: s2a {
> + regulator-min-microvolt = < 800000>;
> + regulator-max-microvolt = <1250000>;
> +
> + qcom,switch-mode-frequency = <1200000>;
> + };
> +
> + smb208_s2b: s2b {
> + regulator-min-microvolt = < 800000>;
> + regulator-max-microvolt = <1250000>;
> +
> + qcom,switch-mode-frequency = <1200000>;
> + };
> + };
> };
>
> tcsr: syscon@1a400000 {
> --
> 2.33.1
>
On Mon, Jan 31, 2022 at 04:49:07PM -0600, Bjorn Andersson wrote:
> On Mon 17 Jan 19:20 CST 2022, Ansuel Smith wrote:
>
> > Add opp table for cpu and l2 cache. The l2 cache won't work as it would
> > require a dedicated cpufreq driver to scale cache with core.
> >
>
> Are you saying that the L2 cache frequency scaling doesn't work so you
> put it there for completeness sake, or that it doesn't work without this
> patch?
>
I put it here for completeness sake. A driver should use the opp table
anyway, so I case I manage to make the cpufreq accepted upstream this is
already present and can be used directly.
> Could you please rewrite this to make it clear in the git history?
>
Hope it's not a problem, in theory should be correct to put it anyway as
it does describe how the device works.
> Thanks,
> Bjorn
>
> > Opp-level is set based on the logic of
> > 0: idle level
> > 1: normal level
> > 2: turbo level
> >
> > Signed-off-by: Ansuel Smith <[email protected]>
> > ---
> > arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++
> > 1 file changed, 99 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > index 6f9075489e58..1e6297d6f302 100644
> > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > @@ -48,6 +48,105 @@ L2: l2-cache {
> > };
> > };
> >
> > + opp_table_l2: opp_table_l2 {
> > + compatible = "operating-points-v2";
> > +
> > + opp-384000000 {
> > + opp-hz = /bits/ 64 <384000000>;
> > + opp-microvolt = <1100000>;
> > + clock-latency-ns = <100000>;
> > + opp-level = <0>;
> > + };
> > +
> > + opp-1000000000 {
> > + opp-hz = /bits/ 64 <1000000000>;
> > + opp-microvolt = <1100000>;
> > + clock-latency-ns = <100000>;
> > + opp-level = <1>;
> > + };
> > +
> > + opp-1200000000 {
> > + opp-hz = /bits/ 64 <1200000000>;
> > + opp-microvolt = <1150000>;
> > + clock-latency-ns = <100000>;
> > + opp-level = <2>;
> > + };
> > + };
> > +
> > + opp_table0: opp_table0 {
> > + compatible = "operating-points-v2-kryo-cpu";
> > + nvmem-cells = <&speedbin_efuse>;
> > +
> > + /*
> > + * Voltage thresholds are <target min max>
> > + */
> > + opp-384000000 {
> > + opp-hz = /bits/ 64 <384000000>;
> > + opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
> > + opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
> > + opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
> > + opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
> > + opp-supported-hw = <0x1>;
> > + clock-latency-ns = <100000>;
> > + opp-level = <0>;
> > + };
> > +
> > + opp-600000000 {
> > + opp-hz = /bits/ 64 <600000000>;
> > + opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
> > + opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
> > + opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
> > + opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
> > + opp-supported-hw = <0x1>;
> > + clock-latency-ns = <100000>;
> > + opp-level = <1>;
> > + };
> > +
> > + opp-800000000 {
> > + opp-hz = /bits/ 64 <800000000>;
> > + opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
> > + opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
> > + opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
> > + opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
> > + opp-supported-hw = <0x1>;
> > + clock-latency-ns = <100000>;
> > + opp-level = <1>;
> > + };
> > +
> > + opp-1000000000 {
> > + opp-hz = /bits/ 64 <1000000000>;
> > + opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
> > + opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
> > + opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
> > + opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
> > + opp-supported-hw = <0x1>;
> > + clock-latency-ns = <100000>;
> > + opp-level = <1>;
> > + };
> > +
> > + opp-1200000000 {
> > + opp-hz = /bits/ 64 <1200000000>;
> > + opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
> > + opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
> > + opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
> > + opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
> > + opp-supported-hw = <0x1>;
> > + clock-latency-ns = <100000>;
> > + opp-level = <2>;
> > + };
> > +
> > + opp-1400000000 {
> > + opp-hz = /bits/ 64 <1400000000>;
> > + opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
> > + opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
> > + opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
> > + opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
> > + opp-supported-hw = <0x1>;
> > + clock-latency-ns = <100000>;
> > + opp-level = <2>;
> > + };
> > + };
> > +
> > thermal-zones {
> > sensor0-thermal {
> > polling-delay-passive = <0>;
> > --
> > 2.33.1
> >
--
Ansuel
On Mon, Jan 31, 2022 at 04:46:18PM -0600, Bjorn Andersson wrote:
> On Mon 17 Jan 19:20 CST 2022, Ansuel Smith wrote:
>
> > Add cells definition for rpm node and add missing regulators for the 4
> > regulator present on ipq8064. There regulators are controlled by rpm and
> > to correctly works gsbi4_i2c require to be NEVER disabled or rpm will
> > reject any regulator change request.
> >
>
> Is the SMB208 mandatory on all ipq8064 designs, or should this be pushed
> out to the device dts?
It's not; the RB3011 uses a different regulator (a TPS563900).
> > Signed-off-by: Ansuel Smith <[email protected]>
> > ---
> > arch/arm/boot/dts/qcom-ipq8064.dtsi | 35 +++++++++++++++++++++++++++++
> > 1 file changed, 35 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > index 094125605bea..824cf13dd037 100644
> > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > @@ -829,10 +829,45 @@ rpm: rpm@108000 {
> > clocks = <&gcc RPM_MSG_RAM_H_CLK>;
> > clock-names = "ram";
> >
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > rpmcc: clock-controller {
> > compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
> > #clock-cells = <1>;
> > };
> > +
> > + regulators {
> > + compatible = "qcom,rpm-smb208-regulators";
> > +
> > + smb208_s1a: s1a {
> > + regulator-min-microvolt = <1050000>;
> > + regulator-max-microvolt = <1150000>;
> > +
> > + qcom,switch-mode-frequency = <1200000>;
> > + };
> > +
> > + smb208_s1b: s1b {
> > + regulator-min-microvolt = <1050000>;
> > + regulator-max-microvolt = <1150000>;
> > +
> > + qcom,switch-mode-frequency = <1200000>;
> > + };
> > +
> > + smb208_s2a: s2a {
> > + regulator-min-microvolt = < 800000>;
> > + regulator-max-microvolt = <1250000>;
> > +
> > + qcom,switch-mode-frequency = <1200000>;
> > + };
> > +
> > + smb208_s2b: s2b {
> > + regulator-min-microvolt = < 800000>;
> > + regulator-max-microvolt = <1250000>;
> > +
> > + qcom,switch-mode-frequency = <1200000>;
> > + };
> > + };
> > };
> >
> > tcsr: syscon@1a400000 {
> > --
> > 2.33.1
> >
J.
--
... "There's no money, there's no weed. It's all been replaced by a fucking
big pile of corpses." -- Lock, Stock and Two Smoking Barrels
On Tue, Feb 01, 2022 at 10:58:52PM +0100, Ansuel Smith wrote:
> On Tue, Feb 01, 2022 at 02:39:20PM +0000, Jonathan McDowell wrote:
> > On Mon, Jan 31, 2022 at 04:46:18PM -0600, Bjorn Andersson wrote:
> > > On Mon 17 Jan 19:20 CST 2022, Ansuel Smith wrote:
> > >
> > > > Add cells definition for rpm node and add missing regulators for the 4
> > > > regulator present on ipq8064. There regulators are controlled by rpm and
> > > > to correctly works gsbi4_i2c require to be NEVER disabled or rpm will
> > > > reject any regulator change request.
> > > >
> > >
> > > Is the SMB208 mandatory on all ipq8064 designs, or should this be pushed
> > > out to the device dts?
> >
> > It's not; the RB3011 uses a different regulator (a TPS563900).
> >
>
> Fact is that that's a special case. We have 20 devices based on ipq806x
> and they all have smb208 regulators.
Indeed, it's another Mikrotik special unfortunately (I haven't managed
to get the SMEM driver to work on the platform either).
> Is the TPS563900 also controlled by rpm?
AFAICT it's CPU controlled via I2C. It looks like one output is shared
for the CPU cores etc and the other is for the NSS cores, rather than
the full control the smb208 offers.
> Anyway should we use a dedicated dtsi to declare the correct regulators?
I've got no problem with smb208 being the default, but please add any
appropriate disabling of it to the RB3011 DTS.
> > > > Signed-off-by: Ansuel Smith <[email protected]>
> > > > ---
> > > > arch/arm/boot/dts/qcom-ipq8064.dtsi | 35 +++++++++++++++++++++++++++++
> > > > 1 file changed, 35 insertions(+)
> > > >
> > > > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > > > index 094125605bea..824cf13dd037 100644
> > > > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > > > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > > > @@ -829,10 +829,45 @@ rpm: rpm@108000 {
> > > > clocks = <&gcc RPM_MSG_RAM_H_CLK>;
> > > > clock-names = "ram";
> > > >
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > +
> > > > rpmcc: clock-controller {
> > > > compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
> > > > #clock-cells = <1>;
> > > > };
> > > > +
> > > > + regulators {
> > > > + compatible = "qcom,rpm-smb208-regulators";
> > > > +
> > > > + smb208_s1a: s1a {
> > > > + regulator-min-microvolt = <1050000>;
> > > > + regulator-max-microvolt = <1150000>;
> > > > +
> > > > + qcom,switch-mode-frequency = <1200000>;
> > > > + };
> > > > +
> > > > + smb208_s1b: s1b {
> > > > + regulator-min-microvolt = <1050000>;
> > > > + regulator-max-microvolt = <1150000>;
> > > > +
> > > > + qcom,switch-mode-frequency = <1200000>;
> > > > + };
> > > > +
> > > > + smb208_s2a: s2a {
> > > > + regulator-min-microvolt = < 800000>;
> > > > + regulator-max-microvolt = <1250000>;
> > > > +
> > > > + qcom,switch-mode-frequency = <1200000>;
> > > > + };
> > > > +
> > > > + smb208_s2b: s2b {
> > > > + regulator-min-microvolt = < 800000>;
> > > > + regulator-max-microvolt = <1250000>;
> > > > +
> > > > + qcom,switch-mode-frequency = <1200000>;
> > > > + };
> > > > + };
> > > > };
> > > >
> > > > tcsr: syscon@1a400000 {
> > > > --
> > > > 2.33.1
J.
--
/-\ | 101 things you can't have too much
|@/ Debian GNU/Linux Developer | of : 13 - Holidays.
\- |
On Tue, Feb 01, 2022 at 02:39:20PM +0000, Jonathan McDowell wrote:
> On Mon, Jan 31, 2022 at 04:46:18PM -0600, Bjorn Andersson wrote:
> > On Mon 17 Jan 19:20 CST 2022, Ansuel Smith wrote:
> >
> > > Add cells definition for rpm node and add missing regulators for the 4
> > > regulator present on ipq8064. There regulators are controlled by rpm and
> > > to correctly works gsbi4_i2c require to be NEVER disabled or rpm will
> > > reject any regulator change request.
> > >
> >
> > Is the SMB208 mandatory on all ipq8064 designs, or should this be pushed
> > out to the device dts?
>
> It's not; the RB3011 uses a different regulator (a TPS563900).
>
Fact is that that's a special case. We have 20 devices based on ipq806x
and they all have smb208 regulators.
Is the TPS563900 also controlled by rpm?
Anyway should we use a dedicated dtsi to declare the correct regulators?
> > > Signed-off-by: Ansuel Smith <[email protected]>
> > > ---
> > > arch/arm/boot/dts/qcom-ipq8064.dtsi | 35 +++++++++++++++++++++++++++++
> > > 1 file changed, 35 insertions(+)
> > >
> > > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > > index 094125605bea..824cf13dd037 100644
> > > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> > > @@ -829,10 +829,45 @@ rpm: rpm@108000 {
> > > clocks = <&gcc RPM_MSG_RAM_H_CLK>;
> > > clock-names = "ram";
> > >
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > rpmcc: clock-controller {
> > > compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
> > > #clock-cells = <1>;
> > > };
> > > +
> > > + regulators {
> > > + compatible = "qcom,rpm-smb208-regulators";
> > > +
> > > + smb208_s1a: s1a {
> > > + regulator-min-microvolt = <1050000>;
> > > + regulator-max-microvolt = <1150000>;
> > > +
> > > + qcom,switch-mode-frequency = <1200000>;
> > > + };
> > > +
> > > + smb208_s1b: s1b {
> > > + regulator-min-microvolt = <1050000>;
> > > + regulator-max-microvolt = <1150000>;
> > > +
> > > + qcom,switch-mode-frequency = <1200000>;
> > > + };
> > > +
> > > + smb208_s2a: s2a {
> > > + regulator-min-microvolt = < 800000>;
> > > + regulator-max-microvolt = <1250000>;
> > > +
> > > + qcom,switch-mode-frequency = <1200000>;
> > > + };
> > > +
> > > + smb208_s2b: s2b {
> > > + regulator-min-microvolt = < 800000>;
> > > + regulator-max-microvolt = <1250000>;
> > > +
> > > + qcom,switch-mode-frequency = <1200000>;
> > > + };
> > > + };
> > > };
> > >
> > > tcsr: syscon@1a400000 {
> > > --
> > > 2.33.1
> > >
>
> J.
>
> --
> ... "There's no money, there's no weed. It's all been replaced by a fucking
> big pile of corpses." -- Lock, Stock and Two Smoking Barrels
--
Ansuel
On Tue, Jan 18, 2022 at 02:20:32AM +0100, Ansuel Smith wrote:
> Add gsbi6 missing definition for ipq8064.
>
> Signed-off-by: Ansuel Smith <[email protected]>
> ---
> arch/arm/boot/dts/qcom-ipq8064.dtsi | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> index cc6ca9013ab1..094125605bea 100644
> --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
> @@ -665,6 +665,33 @@ spi@1a280000 {
> };
> };
>
> + gsbi6: gsbi@16500000 {
> + status = "disabled";
> + compatible = "qcom,gsbi-v1.0.0";
> + cell-index = <6>;
> + reg = <0x16500000 0x100>;
> + clocks = <&gcc GSBI6_H_CLK>;
> + clock-names = "iface";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + syscon-tcsr = <&tcsr>;
> +
> + gsbi6_i2c: i2c@16580000 {
> + compatible = "qcom,i2c-qup-v1.1.1";
> + reg = <0x16580000 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
> + clock-names = "core", "iface";
> + status = "disabled";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
Can you include the SPI definition too? The RB3011 has its SPI LCD
living here.
gsbi6_spi: spi@16580000 {
compatible = "qcom,spi-qup-v1.1.1";
reg = <0x16580000 0x1000>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
clock-names = "core", "iface";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
> + };
> +
> gsbi7: gsbi@16600000 {
> status = "disabled";
> compatible = "qcom,gsbi-v1.0.0";
> --
> 2.33.1
>
J.
--
] https://www.earth.li/~noodles/ [] "send me the rhubarb" -- Martin [
] PGP/GPG Key @ the.earth.li [] Brooks on the risks of dog poo in [
] via keyserver, web or email. [] compost [
] RSA: 4096/0x94FA372B2DA8B985 [] [