Hi Paul,
Thank you for the patch.
On Sat, Feb 05, 2022 at 07:53:31PM +0100, Paul Kocialkowski wrote:
> This introduces YAML bindings documentation for the Allwinner A31 MIPI
> CSI-2 controller.
>
> Signed-off-by: Paul Kocialkowski <[email protected]>
> Reviewed-by: Maxime Ripard <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> ---
> .../media/allwinner,sun6i-a31-mipi-csi2.yaml | 142 ++++++++++++++++++
> 1 file changed, 142 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
> new file mode 100644
> index 000000000000..09207904b6db
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
> @@ -0,0 +1,142 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Allwinner A31 MIPI CSI-2 Device Tree Bindings
> +
> +maintainers:
> + - Paul Kocialkowski <[email protected]>
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: allwinner,sun6i-a31-mipi-csi2
> + - items:
> + - const: allwinner,sun8i-v3s-mipi-csi2
> + - const: allwinner,sun6i-a31-mipi-csi2
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Bus Clock
> + - description: Module Clock
> +
> + clock-names:
> + items:
> + - const: bus
> + - const: mod
> +
> + phys:
> + maxItems: 1
> + description: MIPI D-PHY
> +
> + phy-names:
> + items:
> + - const: dphy
> +
> + resets:
> + maxItems: 1
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + description: Input port, connect to a MIPI CSI-2 sensor
> +
> + properties:
> + reg:
> + const: 0
> +
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - data-lanes
> +
> + additionalProperties: false
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + description: Output port, connect to a CSI controller
> +
> + properties:
> + reg:
> + const: 1
> +
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + additionalProperties: false
The two ports should be required.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - phys
> + - phy-names
And ports should be required here.
Reviewed-by: Laurent Pinchart <[email protected]>
> + - resets
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/sun8i-v3s-ccu.h>
> + #include <dt-bindings/reset/sun8i-v3s-ccu.h>
> +
> + mipi_csi2: csi@1cb1000 {
> + compatible = "allwinner,sun8i-v3s-mipi-csi2",
> + "allwinner,sun6i-a31-mipi-csi2";
> + reg = <0x01cb1000 0x1000>;
> + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CSI>,
> + <&ccu CLK_CSI1_SCLK>;
> + clock-names = "bus", "mod";
> + resets = <&ccu RST_BUS_CSI>;
> +
> + phys = <&dphy>;
> + phy-names = "dphy";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mipi_csi2_in: port@0 {
> + reg = <0>;
> +
> + mipi_csi2_in_ov5648: endpoint {
> + data-lanes = <1 2 3 4>;
> +
> + remote-endpoint = <&ov5648_out_mipi_csi2>;
> + };
> + };
> +
> + mipi_csi2_out: port@1 {
> + reg = <1>;
> +
> + mipi_csi2_out_csi0: endpoint {
> + remote-endpoint = <&csi0_in_mipi_csi2>;
> + };
> + };
> + };
> + };
> +
> +...
--
Regards,
Laurent Pinchart
Hi Laurent,
Thanks for the review!
On Mon 07 Feb 22, 18:09, Laurent Pinchart wrote:
> Hi Paul,
>
> Thank you for the patch.
>
> On Sat, Feb 05, 2022 at 07:53:31PM +0100, Paul Kocialkowski wrote:
> > This introduces YAML bindings documentation for the Allwinner A31 MIPI
> > CSI-2 controller.
> >
> > Signed-off-by: Paul Kocialkowski <[email protected]>
> > Reviewed-by: Maxime Ripard <[email protected]>
> > Reviewed-by: Rob Herring <[email protected]>
> > ---
> > .../media/allwinner,sun6i-a31-mipi-csi2.yaml | 142 ++++++++++++++++++
> > 1 file changed, 142 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
> > new file mode 100644
> > index 000000000000..09207904b6db
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml
> > @@ -0,0 +1,142 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-mipi-csi2.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Allwinner A31 MIPI CSI-2 Device Tree Bindings
> > +
> > +maintainers:
> > + - Paul Kocialkowski <[email protected]>
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - const: allwinner,sun6i-a31-mipi-csi2
> > + - items:
> > + - const: allwinner,sun8i-v3s-mipi-csi2
> > + - const: allwinner,sun6i-a31-mipi-csi2
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: Bus Clock
> > + - description: Module Clock
> > +
> > + clock-names:
> > + items:
> > + - const: bus
> > + - const: mod
> > +
> > + phys:
> > + maxItems: 1
> > + description: MIPI D-PHY
> > +
> > + phy-names:
> > + items:
> > + - const: dphy
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + ports:
> > + $ref: /schemas/graph.yaml#/properties/ports
> > +
> > + properties:
> > + port@0:
> > + $ref: /schemas/graph.yaml#/$defs/port-base
> > + description: Input port, connect to a MIPI CSI-2 sensor
> > +
> > + properties:
> > + reg:
> > + const: 0
> > +
> > + endpoint:
> > + $ref: video-interfaces.yaml#
> > + unevaluatedProperties: false
> > +
> > + properties:
> > + data-lanes:
> > + minItems: 1
> > + maxItems: 4
> > +
> > + required:
> > + - data-lanes
> > +
> > + additionalProperties: false
> > +
> > + port@1:
> > + $ref: /schemas/graph.yaml#/$defs/port-base
> > + description: Output port, connect to a CSI controller
> > +
> > + properties:
> > + reg:
> > + const: 1
> > +
> > + endpoint:
> > + $ref: video-interfaces.yaml#
> > + unevaluatedProperties: false
> > +
> > + additionalProperties: false
>
> The two ports should be required.
Agreed.
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > + - clock-names
> > + - phys
> > + - phy-names
>
> And ports should be required here.
Sure!
Thanks,
Paul
> Reviewed-by: Laurent Pinchart <[email protected]>
>
> > + - resets
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/clock/sun8i-v3s-ccu.h>
> > + #include <dt-bindings/reset/sun8i-v3s-ccu.h>
> > +
> > + mipi_csi2: csi@1cb1000 {
> > + compatible = "allwinner,sun8i-v3s-mipi-csi2",
> > + "allwinner,sun6i-a31-mipi-csi2";
> > + reg = <0x01cb1000 0x1000>;
> > + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_CSI>,
> > + <&ccu CLK_CSI1_SCLK>;
> > + clock-names = "bus", "mod";
> > + resets = <&ccu RST_BUS_CSI>;
> > +
> > + phys = <&dphy>;
> > + phy-names = "dphy";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + mipi_csi2_in: port@0 {
> > + reg = <0>;
> > +
> > + mipi_csi2_in_ov5648: endpoint {
> > + data-lanes = <1 2 3 4>;
> > +
> > + remote-endpoint = <&ov5648_out_mipi_csi2>;
> > + };
> > + };
> > +
> > + mipi_csi2_out: port@1 {
> > + reg = <1>;
> > +
> > + mipi_csi2_out_csi0: endpoint {
> > + remote-endpoint = <&csi0_in_mipi_csi2>;
> > + };
> > + };
> > + };
> > + };
> > +
> > +...
>
> --
> Regards,
>
> Laurent Pinchart
--
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com