This is an attempt in making the ipq8064 SoC actually usable. Currently
many feature are missing for this SoC and devs user off-the-tree patches
to make it work (example patch for missing clock, patch for cpufreq
driver, patch to add missing node in the dts)
I notice there was some work in modernizing the gcc driver for other
qcom target but this wasn't done for ipq806x. This does exactly this, we
drop any parent_names stuff and we switch to the parent_data way. We
also drop the pxo and cxo source clk from gcc driver and we refer to the
dts for it.
This also add all the missing feature for the nss cores and the
cryptoengine in them. It does also introduce the required flags to make
the RPM actually work and NOT reject any command. There was an attempt
in declaring these clock as core clock in the dts but this ends up in no
serial as the kernel makes these clock not accessible. We just want to
make the kernel NOT disable them if unused nothing more.
At the end we update the ipq8064 dtsi to add the pxo and cxo tag and
declare them in gcc and also fix a problem with tsens probe.
v6:
- Add more info about the changed define
- Fixed wrong definition for pxo/cxo parent map
v5:
- Drop patch removing fixed clk
- Use name in parent_data to keep compatibility with old dtb
- Fix error in the documentation commits
- Keep old copyright for gcc documentation
- Fix an error with the rcg floor ops
- Set nss clk based on the device compatible
v4:
- Drop drivers in all the patches.
- Introduce floor ops for sdc
- gcc.yaml to gcc-other.yaml
- gcc-common.yaml to gcc.yaml
v3:
- Rework Documentation with Rob suggestions
v2:
- Fix error from Rob bot.
- Add additional commits to make qcom,gcc.yaml a template
- Squash parent_hws patch with the modernize patch
- Create gcc_pxo instead of using long define.
Ansuel Smith (15):
dt-bindings: clock: split qcom,gcc.yaml to common and specific schema
dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation
dt-bindings: clock: document qcom,gcc-ipq8064 binding
clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0
clk: qcom: gcc-ipq806x: convert parent_names to parent_data
clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents
clk: qcom: gcc-ipq806x: add additional freq nss cores
clk: qcom: gcc-ipq806x: add unusued flag for critical clock
clk: qcom: clk-rcg: add clk_rcg_floor_ops ops
clk: qcom: gcc-ipq806x: add additional freq for sdc table
dt-bindings: clock: add ipq8064 ce5 clk define
clk: qcom: gcc-ipq806x: add CryptoEngine clocks
dt-bindings: reset: add ipq8064 ce5 resets
clk: qcom: gcc-ipq806x: add CryptoEngine resets
ARM: dts: qcom: add syscon and cxo/pxo clock to gcc node for ipq8064
.../bindings/clock/qcom,gcc-apq8064.yaml | 29 +-
.../bindings/clock/qcom,gcc-ipq8064.yaml | 76 ++
.../bindings/clock/qcom,gcc-other.yaml | 70 ++
.../devicetree/bindings/clock/qcom,gcc.yaml | 59 +-
arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +-
drivers/clk/qcom/clk-rcg.c | 24 +
drivers/clk/qcom/clk-rcg.h | 1 +
drivers/clk/qcom/gcc-ipq806x.c | 649 +++++++++++++-----
include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 +-
include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +
10 files changed, 685 insertions(+), 241 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
--
2.34.1
Ipq8065 SoC (an evolution of ipq8064 SoC) contains nss cores that can be
clocked to 800MHz. Add these missing freq to the gcc driver.
Set the freq_tbl for the ubi32_cores to the correct values based on the
machine compatible.
Signed-off-by: Ansuel Smith <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
drivers/clk/qcom/gcc-ipq806x.c | 24 +++++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index ef285d3853aa..f49fc8b753a8 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -232,7 +232,9 @@ static struct clk_regmap pll14_vote = {
static struct pll_freq_tbl pll18_freq_tbl[] = {
NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
+ NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
+ NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
};
static struct clk_pll pll18 = {
@@ -2698,7 +2700,7 @@ static struct clk_branch nss_tcm_clk = {
},
};
-static const struct freq_tbl clk_tbl_nss[] = {
+static const struct freq_tbl clk_tbl_nss_ipq8064[] = {
{ 110000000, P_PLL18, 1, 1, 5 },
{ 275000000, P_PLL18, 2, 0, 0 },
{ 550000000, P_PLL18, 1, 0, 0 },
@@ -2706,6 +2708,14 @@ static const struct freq_tbl clk_tbl_nss[] = {
{ }
};
+static const struct freq_tbl clk_tbl_nss_ipq8065[] = {
+ { 110000000, P_PLL18, 1, 1, 5 },
+ { 275000000, P_PLL18, 2, 0, 0 },
+ { 600000000, P_PLL18, 1, 0, 0 },
+ { 800000000, P_PLL18, 1, 0, 0 },
+ { }
+};
+
static struct clk_dyn_rcg ubi32_core1_src_clk = {
.ns_reg[0] = 0x3d2c,
.ns_reg[1] = 0x3d30,
@@ -2745,7 +2755,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = {
.pre_div_width = 2,
},
.mux_sel_bit = 0,
- .freq_tbl = clk_tbl_nss,
+ /* nss freq table is selected based on the SoC compatible */
.clkr = {
.enable_reg = 0x3d20,
.enable_mask = BIT(1),
@@ -2798,7 +2808,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
.pre_div_width = 2,
},
.mux_sel_bit = 0,
- .freq_tbl = clk_tbl_nss,
+ /* nss freq table is selected based on the SoC compatible */
.clkr = {
.enable_reg = 0x3d40,
.enable_mask = BIT(1),
@@ -3131,6 +3141,14 @@ static int gcc_ipq806x_probe(struct platform_device *pdev)
if (ret)
return ret;
+ if (of_machine_is_compatible("qcom,ipq8065")) {
+ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
+ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8065;
+ } else {
+ ubi32_core1_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
+ ubi32_core2_src_clk.freq_tbl = clk_tbl_nss_ipq8064;
+ }
+
ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
if (ret)
return ret;
--
2.34.1
Document qcom,gcc-ipq8064 binding needed to declare pxo and cxo source
clocks. The gcc node is also used by the tsens driver, already documented,
to get the calib nvmem cells and the base reg from gcc. Use
qcom,gcc.yaml as a template and remove the compatible from
generic qcom,gcc-other.yaml
Signed-off-by: Ansuel Smith <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
.../bindings/clock/qcom,gcc-ipq8064.yaml | 76 +++++++++++++++++++
.../bindings/clock/qcom,gcc-other.yaml | 3 -
2 files changed, 76 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
new file mode 100644
index 000000000000..9eb91dd22557
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq8064.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for IPQ8064
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+maintainers:
+ - Ansuel Smith <[email protected]>
+
+description: |
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains on IPQ8064.
+
+ See also:
+ - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
+ - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
+
+properties:
+ compatible:
+ items:
+ - const: qcom,gcc-ipq8064
+ - const: syscon
+
+ clocks:
+ items:
+ - description: PXO source
+ - description: CXO source
+
+ clock-names:
+ items:
+ - const: pxo
+ - const: cxo
+
+ thermal-sensor:
+ type: object
+
+ allOf:
+ - $ref: /schemas/thermal/qcom-tsens.yaml#
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ gcc: clock-controller@900000 {
+ compatible = "qcom,gcc-ipq8064", "syscon";
+ reg = <0x00900000 0x4000>;
+ clocks = <&pxo_board>, <&cxo_board>;
+ clock-names = "pxo", "cxo";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+
+ tsens: thermal-sensor {
+ compatible = "qcom,ipq8064-tsens";
+
+ nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
+ nvmem-cell-names = "calib", "calib_backup";
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow";
+
+ #qcom,sensors = <11>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
index 47e1c5332d76..4dc0274dbd6b 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
@@ -18,8 +18,6 @@ description:
- dt-bindings/clock/qcom,gcc-ipq4019.h
- dt-bindings/clock/qcom,gcc-ipq6018.h
- dt-bindings/reset/qcom,gcc-ipq6018.h
- - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
- - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
- dt-bindings/clock/qcom,gcc-msm8939.h
- dt-bindings/clock/qcom,gcc-msm8953.h
- dt-bindings/reset/qcom,gcc-msm8939.h
@@ -40,7 +38,6 @@ properties:
enum:
- qcom,gcc-ipq4019
- qcom,gcc-ipq6018
- - qcom,gcc-ipq8064
- qcom,gcc-mdm9607
- qcom,gcc-msm8226
- qcom,gcc-msm8660
--
2.34.1
Add clk_rcg_floor_ops for clock that can't provide a stable freq and
require to use a floor freq to provide the requested frequency.
Signed-off-by: Ansuel Smith <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
drivers/clk/qcom/clk-rcg.c | 24 ++++++++++++++++++++++++
drivers/clk/qcom/clk-rcg.h | 1 +
2 files changed, 25 insertions(+)
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index a9d181d6be21..88845baa7f84 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -526,6 +526,19 @@ static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
return __clk_rcg_set_rate(rcg, f);
}
+static int clk_rcg_set_floor_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_rcg *rcg = to_clk_rcg(hw);
+ const struct freq_tbl *f;
+
+ f = qcom_find_freq_floor(rcg->freq_tbl, rate);
+ if (!f)
+ return -EINVAL;
+
+ return __clk_rcg_set_rate(rcg, f);
+}
+
static int clk_rcg_bypass_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
@@ -816,6 +829,17 @@ const struct clk_ops clk_rcg_ops = {
};
EXPORT_SYMBOL_GPL(clk_rcg_ops);
+const struct clk_ops clk_rcg_floor_ops = {
+ .enable = clk_enable_regmap,
+ .disable = clk_disable_regmap,
+ .get_parent = clk_rcg_get_parent,
+ .set_parent = clk_rcg_set_parent,
+ .recalc_rate = clk_rcg_recalc_rate,
+ .determine_rate = clk_rcg_determine_rate,
+ .set_rate = clk_rcg_set_floor_rate,
+};
+EXPORT_SYMBOL_GPL(clk_rcg_floor_ops);
+
const struct clk_ops clk_rcg_bypass_ops = {
.enable = clk_enable_regmap,
.disable = clk_disable_regmap,
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 99efcc7f8d88..00cea508d49e 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -86,6 +86,7 @@ struct clk_rcg {
};
extern const struct clk_ops clk_rcg_ops;
+extern const struct clk_ops clk_rcg_floor_ops;
extern const struct clk_ops clk_rcg_bypass_ops;
extern const struct clk_ops clk_rcg_bypass2_ops;
extern const struct clk_ops clk_rcg_pixel_ops;
--
2.34.1
Some clocks are used by other devices present on the SoC. For example
the gsbi4_h_clk is used by RPM and is if disabled cause the RPM to
reject any regulator change command. These clock should never be
disabled.
Signed-off-by: Ansuel Smith <[email protected]>
---
drivers/clk/qcom/gcc-ipq806x.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index f49fc8b753a8..983d07586930 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -798,7 +798,7 @@ static struct clk_rcg gsbi4_qup_src = {
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
},
},
};
@@ -816,7 +816,7 @@ static struct clk_branch gsbi4_qup_clk = {
},
.num_parents = 1,
.ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
@@ -900,7 +900,7 @@ static struct clk_rcg gsbi6_qup_src = {
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
- .flags = CLK_SET_PARENT_GATE,
+ .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
},
},
};
@@ -969,7 +969,7 @@ static struct clk_branch gsbi7_qup_clk = {
},
.num_parents = 1,
.ops = &clk_branch_ops,
- .flags = CLK_SET_RATE_PARENT,
+ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
},
},
};
@@ -1015,6 +1015,7 @@ static struct clk_branch gsbi4_h_clk = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_h_clk",
.ops = &clk_branch_ops,
+ .flags = CLK_IGNORE_UNUSED,
},
},
};
--
2.34.1
Split qcom,gcc.yaml to common and specific schema to use it as a
template for schema that needs to use the gcc bindings and require
to add additional bindings.
Signed-off-by: Ansuel Smith <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
.../bindings/clock/qcom,gcc-other.yaml | 76 +++++++++++++++++++
.../devicetree/bindings/clock/qcom,gcc.yaml | 59 +-------------
2 files changed, 80 insertions(+), 55 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
new file mode 100644
index 000000000000..4e5903bcd70d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-other.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding
+
+maintainers:
+ - Stephen Boyd <[email protected]>
+ - Taniya Das <[email protected]>
+
+description:
+ Qualcomm global clock control module which supports the clocks, resets and
+ power domains.
+
+ See also:
+ - dt-bindings/clock/qcom,gcc-apq8084.h
+ - dt-bindings/reset/qcom,gcc-apq8084.h
+ - dt-bindings/clock/qcom,gcc-ipq4019.h
+ - dt-bindings/clock/qcom,gcc-ipq6018.h
+ - dt-bindings/reset/qcom,gcc-ipq6018.h
+ - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
+ - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
+ - dt-bindings/clock/qcom,gcc-msm8939.h
+ - dt-bindings/clock/qcom,gcc-msm8953.h
+ - dt-bindings/reset/qcom,gcc-msm8939.h
+ - dt-bindings/clock/qcom,gcc-msm8660.h
+ - dt-bindings/reset/qcom,gcc-msm8660.h
+ - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
+ - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
+ - dt-bindings/clock/qcom,gcc-mdm9607.h
+ - dt-bindings/clock/qcom,gcc-mdm9615.h
+ - dt-bindings/reset/qcom,gcc-mdm9615.h
+ - dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
+
+allOf:
+ - $ref: "qcom,gcc.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - qcom,gcc-apq8084
+ - qcom,gcc-ipq4019
+ - qcom,gcc-ipq6018
+ - qcom,gcc-ipq8064
+ - qcom,gcc-mdm9607
+ - qcom,gcc-msm8226
+ - qcom,gcc-msm8660
+ - qcom,gcc-msm8916
+ - qcom,gcc-msm8939
+ - qcom,gcc-msm8953
+ - qcom,gcc-msm8960
+ - qcom,gcc-msm8974
+ - qcom,gcc-msm8974pro
+ - qcom,gcc-msm8974pro-ac
+ - qcom,gcc-mdm9615
+ - qcom,gcc-sdm630
+ - qcom,gcc-sdm660
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ # Example for GCC for MSM8960:
+ - |
+ clock-controller@900000 {
+ compatible = "qcom,gcc-msm8960";
+ reg = <0x900000 0x4000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
index f66d703bd913..2ed27a2ef445 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
@@ -4,57 +4,17 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Global Clock & Reset Controller Binding
+title: Qualcomm Global Clock & Reset Controller Binding Common Bindings
maintainers:
- Stephen Boyd <[email protected]>
- Taniya Das <[email protected]>
description: |
- Qualcomm global clock control module which supports the clocks, resets and
- power domains.
-
- See also:
- - dt-bindings/clock/qcom,gcc-apq8084.h
- - dt-bindings/reset/qcom,gcc-apq8084.h
- - dt-bindings/clock/qcom,gcc-ipq4019.h
- - dt-bindings/clock/qcom,gcc-ipq6018.h
- - dt-bindings/reset/qcom,gcc-ipq6018.h
- - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
- - dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
- - dt-bindings/clock/qcom,gcc-msm8939.h
- - dt-bindings/clock/qcom,gcc-msm8953.h
- - dt-bindings/reset/qcom,gcc-msm8939.h
- - dt-bindings/clock/qcom,gcc-msm8660.h
- - dt-bindings/reset/qcom,gcc-msm8660.h
- - dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- - dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
- - dt-bindings/clock/qcom,gcc-mdm9607.h
- - dt-bindings/clock/qcom,gcc-mdm9615.h
- - dt-bindings/reset/qcom,gcc-mdm9615.h
- - dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
+ Common bindings for Qualcomm global clock control module which supports
+ the clocks, resets and power domains.
properties:
- compatible:
- enum:
- - qcom,gcc-apq8084
- - qcom,gcc-ipq4019
- - qcom,gcc-ipq6018
- - qcom,gcc-ipq8064
- - qcom,gcc-mdm9607
- - qcom,gcc-msm8226
- - qcom,gcc-msm8660
- - qcom,gcc-msm8916
- - qcom,gcc-msm8939
- - qcom,gcc-msm8953
- - qcom,gcc-msm8960
- - qcom,gcc-msm8974
- - qcom,gcc-msm8974pro
- - qcom,gcc-msm8974pro-ac
- - qcom,gcc-mdm9615
- - qcom,gcc-sdm630
- - qcom,gcc-sdm660
-
'#clock-cells':
const: 1
@@ -72,22 +32,11 @@ properties:
Protected clock specifier list as per common clock binding.
required:
- - compatible
- reg
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
-additionalProperties: false
+additionalProperties: true
-examples:
- # Example for GCC for MSM8960:
- - |
- clock-controller@900000 {
- compatible = "qcom,gcc-msm8960";
- reg = <0x900000 0x4000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
- };
...
--
2.34.1
Convert parent_names to parent_data to modernize the driver.
Where possible use parent_hws directly.
Signed-off-by: Ansuel Smith <[email protected]>
---
drivers/clk/qcom/gcc-ipq806x.c | 286 ++++++++++++++++++++-------------
1 file changed, 173 insertions(+), 113 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 34cddf461dba..aacd0ada0dd3 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -25,6 +25,10 @@
#include "clk-hfpll.h"
#include "reset.h"
+static const struct clk_parent_data gcc_pxo[] = {
+ { .fw_name = "pxo", .name = "pxo" },
+};
+
static struct clk_pll pll0 = {
.l_reg = 0x30c4,
.m_reg = 0x30c8,
@@ -35,7 +39,7 @@ static struct clk_pll pll0 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll0",
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -46,7 +50,9 @@ static struct clk_regmap pll0_vote = {
.enable_mask = BIT(0),
.hw.init = &(struct clk_init_data){
.name = "pll0_vote",
- .parent_names = (const char *[]){ "pll0" },
+ .parent_hws = (const struct clk_hw*[]){
+ &pll0.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -62,7 +68,7 @@ static struct clk_pll pll3 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll3",
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -89,7 +95,7 @@ static struct clk_pll pll8 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll8",
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -100,7 +106,9 @@ static struct clk_regmap pll8_vote = {
.enable_mask = BIT(8),
.hw.init = &(struct clk_init_data){
.name = "pll8_vote",
- .parent_names = (const char *[]){ "pll8" },
+ .parent_hws = (const struct clk_hw*[]){
+ &pll8.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -123,7 +131,7 @@ static struct hfpll_data hfpll0_data = {
static struct clk_hfpll hfpll0 = {
.d = &hfpll0_data,
.clkr.hw.init = &(struct clk_init_data){
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.name = "hfpll0",
.ops = &clk_ops_hfpll,
@@ -149,7 +157,7 @@ static struct hfpll_data hfpll1_data = {
static struct clk_hfpll hfpll1 = {
.d = &hfpll1_data,
.clkr.hw.init = &(struct clk_init_data){
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.name = "hfpll1",
.ops = &clk_ops_hfpll,
@@ -175,7 +183,7 @@ static struct hfpll_data hfpll_l2_data = {
static struct clk_hfpll hfpll_l2 = {
.d = &hfpll_l2_data,
.clkr.hw.init = &(struct clk_init_data){
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.name = "hfpll_l2",
.ops = &clk_ops_hfpll,
@@ -194,7 +202,7 @@ static struct clk_pll pll14 = {
.status_bit = 16,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll14",
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -205,7 +213,9 @@ static struct clk_regmap pll14_vote = {
.enable_mask = BIT(14),
.hw.init = &(struct clk_init_data){
.name = "pll14_vote",
- .parent_names = (const char *[]){ "pll14" },
+ .parent_hws = (const struct clk_hw*[]){
+ &pll14.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_pll_vote_ops,
},
@@ -238,7 +248,7 @@ static struct clk_pll pll18 = {
.freq_tbl = pll18_freq_tbl,
.clkr.hw.init = &(struct clk_init_data){
.name = "pll18",
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_pll_ops,
},
@@ -259,9 +269,9 @@ static const struct parent_map gcc_pxo_pll8_map[] = {
{ P_PLL8, 3 }
};
-static const char * const gcc_pxo_pll8[] = {
- "pxo",
- "pll8_vote",
+static const struct clk_parent_data gcc_pxo_pll8[] = {
+ { .fw_name = "pxo", .name = "pxo" },
+ { .hw = &pll8_vote.hw },
};
static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
@@ -270,10 +280,10 @@ static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
{ P_CXO, 5 }
};
-static const char * const gcc_pxo_pll8_cxo[] = {
- "pxo",
- "pll8_vote",
- "cxo",
+static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
+ { .fw_name = "pxo", .name = "pxo" },
+ { .hw = &pll8_vote.hw },
+ { .fw_name = "cxo", .name = "cxo" },
};
static const struct parent_map gcc_pxo_pll3_map[] = {
@@ -286,9 +296,9 @@ static const struct parent_map gcc_pxo_pll3_sata_map[] = {
{ P_PLL3, 6 }
};
-static const char * const gcc_pxo_pll3[] = {
- "pxo",
- "pll3",
+static const struct clk_parent_data gcc_pxo_pll3[] = {
+ { .fw_name = "pxo", .name = "pxo" },
+ { .hw = &pll3.clkr.hw },
};
static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
@@ -297,10 +307,10 @@ static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
{ P_PLL0, 2 }
};
-static const char * const gcc_pxo_pll8_pll0[] = {
- "pxo",
- "pll8_vote",
- "pll0_vote",
+static const struct clk_parent_data gcc_pxo_pll8_pll0[] = {
+ { .fw_name = "pxo", .name = "pxo" },
+ { .hw = &pll8_vote.hw },
+ { .hw = &pll0_vote.hw },
};
static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
@@ -311,12 +321,12 @@ static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
{ P_PLL18, 1 }
};
-static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
- "pxo",
- "pll8_vote",
- "pll0_vote",
- "pll14",
- "pll18",
+static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
+ { .fw_name = "pxo", .name = "pxo" },
+ { .hw = &pll8_vote.hw },
+ { .hw = &pll0_vote.hw },
+ { .hw = &pll14.clkr.hw },
+ { .hw = &pll18.clkr.hw },
};
static struct freq_tbl clk_tbl_gsbi_uart[] = {
@@ -362,7 +372,7 @@ static struct clk_rcg gsbi1_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -378,8 +388,8 @@ static struct clk_branch gsbi1_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_clk",
- .parent_names = (const char *[]){
- "gsbi1_uart_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi1_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -413,7 +423,7 @@ static struct clk_rcg gsbi2_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -429,8 +439,8 @@ static struct clk_branch gsbi2_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_clk",
- .parent_names = (const char *[]){
- "gsbi2_uart_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi2_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -464,7 +474,7 @@ static struct clk_rcg gsbi4_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -480,8 +490,8 @@ static struct clk_branch gsbi4_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_clk",
- .parent_names = (const char *[]){
- "gsbi4_uart_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi4_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -515,7 +525,7 @@ static struct clk_rcg gsbi5_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -531,8 +541,8 @@ static struct clk_branch gsbi5_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_clk",
- .parent_names = (const char *[]){
- "gsbi5_uart_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi5_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -566,7 +576,7 @@ static struct clk_rcg gsbi6_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -582,8 +592,8 @@ static struct clk_branch gsbi6_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_clk",
- .parent_names = (const char *[]){
- "gsbi6_uart_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi6_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -617,7 +627,7 @@ static struct clk_rcg gsbi7_uart_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -633,8 +643,8 @@ static struct clk_branch gsbi7_uart_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_clk",
- .parent_names = (const char *[]){
- "gsbi7_uart_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi7_uart_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -681,7 +691,7 @@ static struct clk_rcg gsbi1_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -697,7 +707,9 @@ static struct clk_branch gsbi1_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_clk",
- .parent_names = (const char *[]){ "gsbi1_qup_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi1_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -730,7 +742,7 @@ static struct clk_rcg gsbi2_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -746,7 +758,9 @@ static struct clk_branch gsbi2_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_clk",
- .parent_names = (const char *[]){ "gsbi2_qup_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi2_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -779,7 +793,7 @@ static struct clk_rcg gsbi4_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -795,7 +809,9 @@ static struct clk_branch gsbi4_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_clk",
- .parent_names = (const char *[]){ "gsbi4_qup_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi4_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -828,7 +844,7 @@ static struct clk_rcg gsbi5_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -844,7 +860,9 @@ static struct clk_branch gsbi5_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_clk",
- .parent_names = (const char *[]){ "gsbi5_qup_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi5_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -877,7 +895,7 @@ static struct clk_rcg gsbi6_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -893,7 +911,9 @@ static struct clk_branch gsbi6_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_clk",
- .parent_names = (const char *[]){ "gsbi6_qup_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi6_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -926,7 +946,7 @@ static struct clk_rcg gsbi7_qup_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -942,7 +962,9 @@ static struct clk_branch gsbi7_qup_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_clk",
- .parent_names = (const char *[]){ "gsbi7_qup_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gsbi7_qup_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1076,7 +1098,7 @@ static struct clk_rcg gp0_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp0_src",
- .parent_names = gcc_pxo_pll8_cxo,
+ .parent_data = gcc_pxo_pll8_cxo,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
@@ -1092,7 +1114,9 @@ static struct clk_branch gp0_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp0_clk",
- .parent_names = (const char *[]){ "gp0_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gp0_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1125,7 +1149,7 @@ static struct clk_rcg gp1_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp1_src",
- .parent_names = gcc_pxo_pll8_cxo,
+ .parent_data = gcc_pxo_pll8_cxo,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -1141,7 +1165,9 @@ static struct clk_branch gp1_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp1_clk",
- .parent_names = (const char *[]){ "gp1_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gp1_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1174,7 +1200,7 @@ static struct clk_rcg gp2_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "gp2_src",
- .parent_names = gcc_pxo_pll8_cxo,
+ .parent_data = gcc_pxo_pll8_cxo,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -1190,7 +1216,9 @@ static struct clk_branch gp2_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "gp2_clk",
- .parent_names = (const char *[]){ "gp2_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &gp2_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1228,7 +1256,7 @@ static struct clk_rcg prng_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "prng_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
},
@@ -1244,7 +1272,9 @@ static struct clk_branch prng_clk = {
.enable_mask = BIT(10),
.hw.init = &(struct clk_init_data){
.name = "prng_clk",
- .parent_names = (const char *[]){ "prng_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &prng_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
},
@@ -1290,7 +1320,7 @@ static struct clk_rcg sdc1_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc1_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
},
@@ -1305,7 +1335,9 @@ static struct clk_branch sdc1_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc1_clk",
- .parent_names = (const char *[]){ "sdc1_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &sdc1_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1338,7 +1370,7 @@ static struct clk_rcg sdc3_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "sdc3_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
},
@@ -1353,7 +1385,9 @@ static struct clk_branch sdc3_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "sdc3_clk",
- .parent_names = (const char *[]){ "sdc3_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &sdc3_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1421,7 +1455,7 @@ static struct clk_rcg tsif_ref_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_src",
- .parent_names = gcc_pxo_pll8,
+ .parent_data = gcc_pxo_pll8,
.num_parents = 2,
.ops = &clk_rcg_ops,
},
@@ -1436,7 +1470,9 @@ static struct clk_branch tsif_ref_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_clk",
- .parent_names = (const char *[]){ "tsif_ref_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &tsif_ref_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1583,7 +1619,7 @@ static struct clk_rcg pcie_ref_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pcie_ref_src",
- .parent_names = gcc_pxo_pll3,
+ .parent_data = gcc_pxo_pll3,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -1599,7 +1635,9 @@ static struct clk_branch pcie_ref_src_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pcie_ref_src_clk",
- .parent_names = (const char *[]){ "pcie_ref_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &pcie_ref_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1675,7 +1713,7 @@ static struct clk_rcg pcie1_ref_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pcie1_ref_src",
- .parent_names = gcc_pxo_pll3,
+ .parent_data = gcc_pxo_pll3,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -1691,7 +1729,9 @@ static struct clk_branch pcie1_ref_src_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pcie1_ref_src_clk",
- .parent_names = (const char *[]){ "pcie1_ref_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &pcie1_ref_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1767,7 +1807,7 @@ static struct clk_rcg pcie2_ref_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "pcie2_ref_src",
- .parent_names = gcc_pxo_pll3,
+ .parent_data = gcc_pxo_pll3,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -1783,7 +1823,9 @@ static struct clk_branch pcie2_ref_src_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "pcie2_ref_src_clk",
- .parent_names = (const char *[]){ "pcie2_ref_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &pcie2_ref_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1864,7 +1906,7 @@ static struct clk_rcg sata_ref_src = {
.enable_mask = BIT(7),
.hw.init = &(struct clk_init_data){
.name = "sata_ref_src",
- .parent_names = gcc_pxo_pll3,
+ .parent_data = gcc_pxo_pll3,
.num_parents = 2,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -1880,7 +1922,9 @@ static struct clk_branch sata_rxoob_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_rxoob_clk",
- .parent_names = (const char *[]){ "sata_ref_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &sata_ref_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1896,7 +1940,9 @@ static struct clk_branch sata_pmalive_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_pmalive_clk",
- .parent_names = (const char *[]){ "sata_ref_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &sata_ref_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -1912,7 +1958,7 @@ static struct clk_branch sata_phy_ref_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "sata_phy_ref_clk",
- .parent_names = (const char *[]){ "pxo" },
+ .parent_data = gcc_pxo,
.num_parents = 1,
.ops = &clk_branch_ops,
},
@@ -2001,7 +2047,7 @@ static struct clk_rcg usb30_master_clk_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb30_master_ref_src",
- .parent_names = gcc_pxo_pll8_pll0,
+ .parent_data = gcc_pxo_pll8_pll0,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -2017,7 +2063,9 @@ static struct clk_branch usb30_0_branch_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb30_0_branch_clk",
- .parent_names = (const char *[]){ "usb30_master_ref_src", },
+ .parent_hws = (const struct clk_hw*[]){
+ &usb30_master_clk_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2033,7 +2081,9 @@ static struct clk_branch usb30_1_branch_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb30_1_branch_clk",
- .parent_names = (const char *[]){ "usb30_master_ref_src", },
+ .parent_hws = (const struct clk_hw*[]){
+ &usb30_master_clk_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2071,7 +2121,7 @@ static struct clk_rcg usb30_utmi_clk = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb30_utmi_clk",
- .parent_names = gcc_pxo_pll8_pll0,
+ .parent_data = gcc_pxo_pll8_pll0,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -2087,7 +2137,9 @@ static struct clk_branch usb30_0_utmi_clk_ctl = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb30_0_utmi_clk_ctl",
- .parent_names = (const char *[]){ "usb30_utmi_clk", },
+ .parent_hws = (const struct clk_hw*[]){
+ &usb30_utmi_clk.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2103,7 +2155,9 @@ static struct clk_branch usb30_1_utmi_clk_ctl = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb30_1_utmi_clk_ctl",
- .parent_names = (const char *[]){ "usb30_utmi_clk", },
+ .parent_hws = (const struct clk_hw*[]){
+ &usb30_utmi_clk.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2141,7 +2195,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_src",
- .parent_names = gcc_pxo_pll8_pll0,
+ .parent_data = gcc_pxo_pll8_pll0,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -2157,7 +2211,9 @@ static struct clk_branch usb_hs1_xcvr_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_clk",
- .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_hs1_xcvr_clk_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2205,7 +2261,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
.enable_mask = BIT(11),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_src",
- .parent_names = gcc_pxo_pll8_pll0,
+ .parent_data = gcc_pxo_pll8_pll0,
.num_parents = 3,
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
@@ -2221,7 +2277,9 @@ static struct clk_branch usb_fs1_xcvr_clk = {
.enable_mask = BIT(9),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_clk",
- .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_fs1_xcvr_clk_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2237,7 +2295,9 @@ static struct clk_branch usb_fs1_sys_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_sys_clk",
- .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
+ .parent_hws = (const struct clk_hw*[]){
+ &usb_fs1_xcvr_clk_src.clkr.hw,
+ },
.num_parents = 1,
.ops = &clk_branch_ops,
.flags = CLK_SET_RATE_PARENT,
@@ -2337,7 +2397,7 @@ static struct clk_dyn_rcg gmac_core1_src = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gmac_core1_src",
- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
},
@@ -2354,8 +2414,8 @@ static struct clk_branch gmac_core1_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gmac_core1_clk",
- .parent_names = (const char *[]){
- "gmac_core1_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gmac_core1_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -2409,7 +2469,7 @@ static struct clk_dyn_rcg gmac_core2_src = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gmac_core2_src",
- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
},
@@ -2426,8 +2486,8 @@ static struct clk_branch gmac_core2_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gmac_core2_clk",
- .parent_names = (const char *[]){
- "gmac_core2_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gmac_core2_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -2481,7 +2541,7 @@ static struct clk_dyn_rcg gmac_core3_src = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gmac_core3_src",
- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
},
@@ -2498,8 +2558,8 @@ static struct clk_branch gmac_core3_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gmac_core3_clk",
- .parent_names = (const char *[]){
- "gmac_core3_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gmac_core3_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -2553,7 +2613,7 @@ static struct clk_dyn_rcg gmac_core4_src = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "gmac_core4_src",
- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
},
@@ -2570,8 +2630,8 @@ static struct clk_branch gmac_core4_clk = {
.enable_mask = BIT(4),
.hw.init = &(struct clk_init_data){
.name = "gmac_core4_clk",
- .parent_names = (const char *[]){
- "gmac_core4_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &gmac_core4_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -2613,7 +2673,7 @@ static struct clk_dyn_rcg nss_tcm_src = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "nss_tcm_src",
- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
},
@@ -2628,8 +2688,8 @@ static struct clk_branch nss_tcm_clk = {
.enable_mask = BIT(6) | BIT(4),
.hw.init = &(struct clk_init_data){
.name = "nss_tcm_clk",
- .parent_names = (const char *[]){
- "nss_tcm_src",
+ .parent_hws = (const struct clk_hw*[]){
+ &nss_tcm_src.clkr.hw,
},
.num_parents = 1,
.ops = &clk_branch_ops,
@@ -2691,7 +2751,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "ubi32_core1_src_clk",
- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
@@ -2744,7 +2804,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
.enable_mask = BIT(1),
.hw.init = &(struct clk_init_data){
.name = "ubi32_core2_src_clk",
- .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+ .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
.num_parents = 5,
.ops = &clk_dyn_rcg_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
--
2.34.1
Add additional freq supported for the sdc table. The ops are changed to
the floor_ops to handle a freq request of 52kHz where we need to provide
a freq of 51.2kHz instead for stability reason.
Signed-off-by: Ansuel Smith <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
drivers/clk/qcom/gcc-ipq806x.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index 983d07586930..f3d56519eee5 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -1292,6 +1292,7 @@ static const struct freq_tbl clk_tbl_sdc[] = {
{ 20210000, P_PLL8, 1, 1, 19 },
{ 24000000, P_PLL8, 4, 1, 4 },
{ 48000000, P_PLL8, 4, 1, 2 },
+ { 51200000, P_PLL8, 1, 2, 15 },
{ 64000000, P_PLL8, 3, 1, 2 },
{ 96000000, P_PLL8, 4, 0, 0 },
{ 192000000, P_PLL8, 2, 0, 0 },
@@ -1325,7 +1326,7 @@ static struct clk_rcg sdc1_src = {
.name = "sdc1_src",
.parent_data = gcc_pxo_pll8,
.num_parents = ARRAY_SIZE(gcc_pxo_pll8),
- .ops = &clk_rcg_ops,
+ .ops = &clk_rcg_floor_ops,
},
}
};
--
2.34.1
Add ipq8064 ce5 resets needed for CryptoEngine gcc driver.
Signed-off-by: Ansuel Smith <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Acked-by: Philipp Zabel <[email protected]>
Acked-by: Rob Herring <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/dt-bindings/reset/qcom,gcc-ipq806x.h b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
index 26b6f9200620..020c9cf18751 100644
--- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
+++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
@@ -163,5 +163,10 @@
#define NSS_CAL_PRBS_RST_N_RESET 154
#define NSS_LCKDT_RST_N_RESET 155
#define NSS_SRDS_N_RESET 156
+#define CRYPTO_ENG1_RESET 157
+#define CRYPTO_ENG2_RESET 158
+#define CRYPTO_ENG3_RESET 159
+#define CRYPTO_ENG4_RESET 160
+#define CRYPTO_AHB_RESET 161
#endif
--
2.34.1
On Sat, Feb 26, 2022 at 02:52:20PM +0100, Ansuel Smith wrote:
> This is an attempt in making the ipq8064 SoC actually usable. Currently
> many feature are missing for this SoC and devs user off-the-tree patches
> to make it work (example patch for missing clock, patch for cpufreq
> driver, patch to add missing node in the dts)
>
> I notice there was some work in modernizing the gcc driver for other
> qcom target but this wasn't done for ipq806x. This does exactly this, we
> drop any parent_names stuff and we switch to the parent_data way. We
> also drop the pxo and cxo source clk from gcc driver and we refer to the
> dts for it.
>
> This also add all the missing feature for the nss cores and the
> cryptoengine in them. It does also introduce the required flags to make
> the RPM actually work and NOT reject any command. There was an attempt
> in declaring these clock as core clock in the dts but this ends up in no
> serial as the kernel makes these clock not accessible. We just want to
> make the kernel NOT disable them if unused nothing more.
>
> At the end we update the ipq8064 dtsi to add the pxo and cxo tag and
> declare them in gcc and also fix a problem with tsens probe.
FWIW, series tested on my RB3011. No regressions, tsens driver now
correctly loads.
Tested-by: Jonathan McDowell <[email protected]>
> v6:
> - Add more info about the changed define
> - Fixed wrong definition for pxo/cxo parent map
> v5:
> - Drop patch removing fixed clk
> - Use name in parent_data to keep compatibility with old dtb
> - Fix error in the documentation commits
> - Keep old copyright for gcc documentation
> - Fix an error with the rcg floor ops
> - Set nss clk based on the device compatible
> v4:
> - Drop drivers in all the patches.
> - Introduce floor ops for sdc
> - gcc.yaml to gcc-other.yaml
> - gcc-common.yaml to gcc.yaml
> v3:
> - Rework Documentation with Rob suggestions
> v2:
> - Fix error from Rob bot.
> - Add additional commits to make qcom,gcc.yaml a template
> - Squash parent_hws patch with the modernize patch
> - Create gcc_pxo instead of using long define.
>
> Ansuel Smith (15):
> dt-bindings: clock: split qcom,gcc.yaml to common and specific schema
> dt-bindings: clock: simplify qcom,gcc-apq8064 Documentation
> dt-bindings: clock: document qcom,gcc-ipq8064 binding
> clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0
> clk: qcom: gcc-ipq806x: convert parent_names to parent_data
> clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents
> clk: qcom: gcc-ipq806x: add additional freq nss cores
> clk: qcom: gcc-ipq806x: add unusued flag for critical clock
> clk: qcom: clk-rcg: add clk_rcg_floor_ops ops
> clk: qcom: gcc-ipq806x: add additional freq for sdc table
> dt-bindings: clock: add ipq8064 ce5 clk define
> clk: qcom: gcc-ipq806x: add CryptoEngine clocks
> dt-bindings: reset: add ipq8064 ce5 resets
> clk: qcom: gcc-ipq806x: add CryptoEngine resets
> ARM: dts: qcom: add syscon and cxo/pxo clock to gcc node for ipq8064
>
> .../bindings/clock/qcom,gcc-apq8064.yaml | 29 +-
> .../bindings/clock/qcom,gcc-ipq8064.yaml | 76 ++
> .../bindings/clock/qcom,gcc-other.yaml | 70 ++
> .../devicetree/bindings/clock/qcom,gcc.yaml | 59 +-
> arch/arm/boot/dts/qcom-ipq8064.dtsi | 8 +-
> drivers/clk/qcom/clk-rcg.c | 24 +
> drivers/clk/qcom/clk-rcg.h | 1 +
> drivers/clk/qcom/gcc-ipq806x.c | 649 +++++++++++++-----
> include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 +-
> include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +
> 10 files changed, 685 insertions(+), 241 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
>
> --
> 2.34.1
J.
--
Web [ Even the Evening Herald slags me off. ]
site: https:// [ ] Made by
http://www.earth.li/~noodles/ [ ] HuggieTag 0.0.24