This patch continues support for the imxrt series now with the imxrt1170
This patch contains:
- Update to imxrt_defconfig
- Devicetree
- Clock driver
- Pinctrl driver
- New pll
This patch also updates some documentation for both imxrt1170 an 1050.
The i.MXRT1170 has a vast array of features including two cores. 2 Ethernet, 2 USB phy, and a 2d gpu.
It also is featured in a new google coral board
https://coral.ai/products/dev-board-micro
Not affiliated unfortunately.
---
V1 -> V2:
- Add 3 new commits in documentation
- Fix spelling
---
Jesse Taube (15):
dt-bindings: arm: imx: Add i.MXRT compatible Documentation
dt-bindings: timer: gpt: Add i.MXRT compatible Documentation
dt-bindings: gpio: fsl-imx-gpio: Add i.MXRT compatibles
dt-bindings: mmc: fsl-imx-esdhc: add i.MXRT1170 compatible
dt-bindings: serial: fsl-lpuart: add i.MXRT1170 compatible
dt-bindings: pinctrl: add i.MXRT1170 pinctrl Documentation
dt-bindings: clock: imx: Add documentation for i.MXRT1170 clock
ARM: mach-imx: Add support for i.MXRT1170
ARM: clk: imx: Update pllv3 to support i.MXRT1170
dt-bindings: imx: Add clock binding for i.MXRT1170
clk: imx: Add initial support for i.MXRT1170 clock driver
pinctrl: freescale: Add i.MXRT1170 pinctrl driver support
ARM: dts: imxrt1170-pinfunc: Add pinctrl binding header
ARM: dts: imx: Add i.MXRT1170-EVK support
ARM: imxrt_defconfig: Add i.MXRT1170
.../devicetree/bindings/arm/fsl.yaml | 12 +
.../bindings/clock/fsl,imxrt1170-clock.yaml | 59 +
.../bindings/gpio/fsl-imx-gpio.yaml | 2 +
.../bindings/mmc/fsl-imx-esdhc.yaml | 6 +
.../bindings/pinctrl/fsl,imxrt1170.yaml | 77 +
.../bindings/serial/fsl-lpuart.yaml | 4 +
.../devicetree/bindings/timer/fsl,imxgpt.yaml | 2 +
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/imxrt1170-evk.dts | 110 ++
arch/arm/boot/dts/imxrt1170-pinfunc.h | 1561 +++++++++++++++++
arch/arm/boot/dts/imxrt1170.dtsi | 276 +++
arch/arm/configs/imxrt_defconfig | 17 +
arch/arm/mach-imx/mach-imxrt.c | 1 +
drivers/clk/imx/Kconfig | 7 +
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imxrt1170.c | 536 ++++++
drivers/clk/imx/clk-pllv3.c | 57 +-
drivers/clk/imx/clk.h | 4 +
drivers/pinctrl/freescale/Kconfig | 7 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imxrt1170.c | 349 ++++
include/dt-bindings/clock/imxrt1170-clock.h | 282 +++
22 files changed, 3371 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/fsl,imxrt1170-clock.yaml
create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml
create mode 100644 arch/arm/boot/dts/imxrt1170-evk.dts
create mode 100644 arch/arm/boot/dts/imxrt1170-pinfunc.h
create mode 100644 arch/arm/boot/dts/imxrt1170.dtsi
create mode 100644 drivers/clk/imx/clk-imxrt1170.c
create mode 100644 drivers/pinctrl/freescale/pinctrl-imxrt1170.c
create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h
--
2.35.1
Both the i.MXRT1170 and 1050 have the same gpio controller as
"fsl,imx35-gpio". Add i.MXRT to the compatible list.
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- New commit to fix dtbs_check
---
Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml
index f57d22d1ebd6..ae18603697d7 100644
--- a/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml
@@ -37,6 +37,8 @@ properties:
- fsl,imx8mp-gpio
- fsl,imx8mq-gpio
- fsl,imx8qxp-gpio
+ - fsl,imxrt1050-gpio
+ - fsl,imxrt1170-gpio
- const: fsl,imx35-gpio
reg:
--
2.35.1
Add clock driver support for i.MXRT1170.
Cc: Giulio Benetti <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- Add slab.h and clock-provider.h
- Add spaces in `root_clocks`
- Expand and sort macro
- Move `clk_hw` structs to `clocks_probe`
- Remove of_irq.h
- Remove unused code/comments
---
drivers/clk/imx/Kconfig | 7 +
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-imxrt1170.c | 536 ++++++++++++++++++++++++++++++++
3 files changed, 544 insertions(+)
create mode 100644 drivers/clk/imx/clk-imxrt1170.c
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 45641b8bdc50..009adbe8059f 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -112,3 +112,10 @@ config CLK_IMXRT1050
select MXC_CLK
help
Build the driver for i.MXRT1050 CCM Clock Driver
+
+config CLK_IMXRT1170
+ tristate "IMXRT1170 CCM Clock Driver"
+ depends on SOC_IMXRT
+ select MXC_CLK
+ help
+ Build the driver for i.MXRT1170 CCM Clock Driver
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 1e13c5cb37d9..0968d9ffcf6b 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -47,4 +47,5 @@ obj-$(CONFIG_CLK_IMX6UL) += clk-imx6ul.o
obj-$(CONFIG_CLK_IMX7D) += clk-imx7d.o
obj-$(CONFIG_CLK_IMX7ULP) += clk-imx7ulp.o
obj-$(CONFIG_CLK_IMXRT1050) += clk-imxrt1050.o
+obj-$(CONFIG_CLK_IMXRT1170) += clk-imxrt1170.o
obj-$(CONFIG_CLK_VF610) += clk-vf610.o
diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c
new file mode 100644
index 000000000000..bcae3b687be6
--- /dev/null
+++ b/drivers/clk/imx/clk-imxrt1170.c
@@ -0,0 +1,536 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s):
+ * Jesse Taube <[email protected]>
+ */
+#include <linux/clk.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/clock/imxrt1170-clock.h>
+
+#include "clk.h"
+
+#define CLOCK_MUX_DEFAULT "rcosc48M_div2", "osc", "rcosc400M", "rcosc16M"
+
+#define LPCG_GATE(gate) (0x6000 + (gate * 0x20))
+
+enum root_clock_names {
+ m7,
+ m4,
+ bus,
+ bus_lpsr,
+ semc,
+ cssys,
+ cstrace,
+ m4_systick,
+ m7_systick,
+ adc1,
+ adc2,
+ acmp,
+ flexio1,
+ flexio2,
+ gpt1,
+ gpt2,
+ gpt3,
+ gpt4,
+ gpt5,
+ gpt6,
+ flexspi1,
+ flexspi2,
+ can1,
+ can2,
+ can3,
+ lpuart1,
+ lpuart2,
+ lpuart3,
+ lpuart4,
+ lpuart5,
+ lpuart6,
+ lpuart7,
+ lpuart8,
+ lpuart9,
+ lpuart10,
+ lpuart11,
+ lpuart12,
+ lpi2c1,
+ lpi2c2,
+ lpi2c3,
+ lpi2c4,
+ lpi2c5,
+ lpi2c6,
+ lpspi1,
+ lpspi2,
+ lpspi3,
+ lpspi4,
+ lpspi5,
+ lpspi6,
+ emv1,
+ emv2,
+ enet1,
+ enet2,
+ enet_qos,
+ enet_25m,
+ enet_timer1,
+ enet_timer2,
+ enet_timer3,
+ usdhc1,
+ usdhc2,
+ asrc,
+ mqs,
+ mic,
+ spdif,
+ sai1,
+ sai2,
+ sai3,
+ sai4,
+ gc355,
+ lcdif,
+ lcdifv2,
+ mipi_ref,
+ mipi_esc,
+ csi2,
+ csi2_esc,
+ csi2_ui,
+ csi,
+ cko1,
+ cko2,
+ end,
+};
+
+static const char * const root_clocks[79][8] = {
+ { CLOCK_MUX_DEFAULT, "pll_arm", "pll1_sys", "pll3_sys", "pll_video" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_sys", "pll1_div5" },
+ { CLOCK_MUX_DEFAULT, "pll3_sys", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_sys", "pll1_div5" },
+ { CLOCK_MUX_DEFAULT, "pll1_div5", "pll2_sys", "pll2_pfd1", "pll3_pfd0" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_pfd1", "pll2_sys" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_pfd0", "pll1_div5" },
+ { CLOCK_MUX_DEFAULT, "pll2_sys", "pll3_div2", "pll1_div5", "pll2_pfd0" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_sys", "pll1_div5", "pll_audio", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll_audio", "pll_video" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll_audio", "pll_video" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd0", "pll2_sys", "pll2_pfd2", "pll3_sys" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd0", "pll2_sys", "pll2_pfd2", "pll3_sys" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_pfd3", "pll1_div5" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_pfd3", "pll1_div5" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_pfd3", "pll1_div5" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_pfd3", "pll1_div5" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_pfd3", "pll1_div5" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll3_pfd2", "pll1_div5" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll3_pfd2", "pll1_div5" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" },
+ { CLOCK_MUX_DEFAULT, "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" },
+ { CLOCK_MUX_DEFAULT, "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" },
+ { CLOCK_MUX_DEFAULT, "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" },
+ { CLOCK_MUX_DEFAULT, "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" },
+ { CLOCK_MUX_DEFAULT, "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" },
+ { CLOCK_MUX_DEFAULT, "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" },
+ { CLOCK_MUX_DEFAULT, "pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm" },
+ { CLOCK_MUX_DEFAULT, "pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm" },
+ { CLOCK_MUX_DEFAULT, "pll1_div5", "pll3_div2", "pll_audio", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll1_div5", "pll3_div2", "pll_audio", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll_audio", "pll1_div5" },
+ { CLOCK_MUX_DEFAULT, "pll_audio", "pll3_sys", "pll3_pfd2", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll_audio", "pll3_pfd2", "pll1_div5", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll_audio", "pll3_pfd2", "pll1_div5", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll_audio", "pll3_pfd2", "pll1_div5", "pll2_pfd3" },
+ { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll_audio", "pll1_div5" },
+ { CLOCK_MUX_DEFAULT, "pll2_sys", "pll2_pfd1", "pll3_sys", "pll_video" },
+ { CLOCK_MUX_DEFAULT, "pll2_sys", "pll2_pfd2", "pll3_pfd0", "pll_video" },
+ { CLOCK_MUX_DEFAULT, "pll2_sys", "pll2_pfd2", "pll3_pfd0", "pll_video" },
+ { CLOCK_MUX_DEFAULT, "pll2_sys", "pll2_pfd0", "pll3_pfd0", "pll_video" },
+ { CLOCK_MUX_DEFAULT, "pll2_sys", "pll2_pfd0", "pll3_pfd0", "pll_video" },
+ { CLOCK_MUX_DEFAULT, "pll2_pfd2", "pll3_sys", "pll2_pfd0", "pll_video" },
+ { CLOCK_MUX_DEFAULT, "pll2_pfd2", "pll3_sys", "pll2_pfd0", "pll_video" },
+ { CLOCK_MUX_DEFAULT, "pll2_pfd2", "pll3_sys", "pll2_pfd0", "pll_video" },
+ { CLOCK_MUX_DEFAULT, "pll2_pfd2", "pll3_sys", "pll3_pfd1", "pll_video" },
+ { CLOCK_MUX_DEFAULT, "pll2_pfd2", "pll2_sys", "pll3_pfd1", "pll1_div5" },
+ { CLOCK_MUX_DEFAULT, "pll2_pfd3", "rcosc48M", "pll3_pfd1", "pll_audio"}
+};
+
+static const char * const pll_arm_mux[] = {"pll_arm_pre", "osc"};
+static const char * const pll3_mux[] = {"pll3_pre", "osc"};
+static const char * const pll2_mux[] = {"pll2_pre", "osc"};
+
+static const struct clk_div_table post_div_table[] = {
+ { .val = 3, .div = 1, },
+ { .val = 2, .div = 8, },
+ { .val = 1, .div = 4, },
+ { .val = 0, .div = 2, },
+ { }
+};
+
+static int imxrt1170_clocks_probe(struct platform_device *pdev)
+{
+ void __iomem *ccm_base;
+ void __iomem *pll_base;
+ struct clk_hw **hws;
+ struct clk_hw_onecell_data *clk_hw_data;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *anp;
+ int ret;
+
+ clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
+ IMXRT1170_CLK_END), GFP_KERNEL);
+ if (WARN_ON(!clk_hw_data))
+ return -ENOMEM;
+
+ clk_hw_data->num = IMXRT1170_CLK_END;
+ hws = clk_hw_data->hws;
+
+ hws[IMXRT1170_CLK_OSC] = imx_obtain_fixed_clk_hw(np, "osc");
+ hws[IMXRT1170_CLK_RCOSC_16M] = imx_obtain_fixed_clk_hw(np, "rcosc16M");
+ hws[IMXRT1170_CLK_OSC_32K] = imx_obtain_fixed_clk_hw(np, "osc32k");
+
+ hws[IMXRT1170_CLK_RCOSC_48M] = imx_clk_hw_fixed_factor("rcosc48M", "rcosc16M", 3, 1);
+ hws[IMXRT1170_CLK_RCOSC_400M] = imx_clk_hw_fixed_factor("rcosc400M", "rcosc16M", 25, 1);
+ hws[IMXRT1170_CLK_RCOSC_48M_DIV2] = imx_clk_hw_fixed_factor("rcosc48M_div2", "rcosc48M", 1, 2);
+
+ anp = of_find_compatible_node(NULL, NULL, "fsl,imxrt-anatop");
+ pll_base = of_iomap(anp, 0);
+ of_node_put(anp);
+ if (WARN_ON(!pll_base))
+ return -ENOMEM;
+
+ /* Anatop clocks */
+ hws[IMXRT1170_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0UL);
+
+ hws[IMXRT1170_CLK_PLL_ARM_PRE] = imx_clk_hw_pllv3(IMX_PLLV3_SYSV2, "pll_arm_pre", "osc", pll_base + 0x200, 0xff);
+ imx_clk_hw_pll3_powerbit(hws[IMXRT1170_CLK_PLL_ARM_PRE], 13);
+ hws[IMXRT1170_CLK_PLL_ARM_BYPASS] = imx_clk_hw_mux("pll_arm_bypass",
+ pll_base + 0x200, 17, 1, pll_arm_mux, 2);
+ hws[IMXRT1170_CLK_PLL_ARM_DIV] = clk_hw_register_divider_table(NULL, "pll_arm_div",
+ "pll_arm_bypass", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
+ pll_base + 0x200, 15, 2, 0, post_div_table, &imx_ccm_lock);
+ hws[IMXRT1170_CLK_PLL_ARM] = imx_clk_hw_gate("pll_arm", "pll_arm_div", pll_base + 0x200, 14);
+
+ hws[IMXRT1170_CLK_PLL3_PRE] = imx_clk_hw_pllv3(IMX_PLLV3_GENERICV2, "pll3_pre", "osc", pll_base + 0x210, 0x1);
+ imx_clk_hw_pll3_powerbit(hws[IMXRT1170_CLK_PLL3_PRE], 21);
+ hws[IMXRT1170_CLK_PLL3_BYPASS] = imx_clk_hw_mux("pll3_bypass",
+ pll_base + 0x210, 16, 1, pll3_mux, 2);
+ hws[IMXRT1170_CLK_PLL3] = imx_clk_hw_gate("pll3_sys", "pll3_bypass", pll_base + 0x210, 13);
+
+ hws[IMXRT1170_CLK_PLL2_PRE] = imx_clk_hw_pllv3(IMX_PLLV3_GENERICV2, "pll2_pre", "osc", pll_base + 0x240, 0x1);
+ imx_clk_hw_pll3_powerbit(hws[IMXRT1170_CLK_PLL2_PRE], 23);
+ hws[IMXRT1170_CLK_PLL2_BYPASS] = imx_clk_hw_mux("pll2_bypass",
+ pll_base + 0x240, 16, 1, pll2_mux, 2);
+ hws[IMXRT1170_CLK_PLL2] = imx_clk_hw_gate("pll2_sys", "pll2_bypass", pll_base + 0x240, 13);
+
+ hws[IMXRT1170_CLK_PLL3_PFD0] = imx_clk_hw_pfd("pll3_pfd0", "pll3_sys", pll_base + 0x230, 0);
+ hws[IMXRT1170_CLK_PLL3_PFD1] = imx_clk_hw_pfd("pll3_pfd1", "pll3_sys", pll_base + 0x230, 1);
+ hws[IMXRT1170_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2", "pll3_sys", pll_base + 0x230, 2);
+ hws[IMXRT1170_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3", "pll3_sys", pll_base + 0x230, 3);
+ hws[IMXRT1170_CLK_PLL3_DIV2_GATE] = imx_clk_hw_fixed_factor("pll3_div2_gate", "pll3_sys", 1, 2);
+ hws[IMXRT1170_CLK_PLL3_DIV2] = imx_clk_hw_gate("pll3_div2", "pll3_sys", pll_base + 0x210, 3);
+
+ hws[IMXRT1170_CLK_PLL2_PFD0] = imx_clk_hw_pfd("pll2_pfd0", "pll2_sys", pll_base + 0x270, 0);
+ hws[IMXRT1170_CLK_PLL2_PFD1] = imx_clk_hw_pfd("pll2_pfd1", "pll2_sys", pll_base + 0x270, 1);
+ hws[IMXRT1170_CLK_PLL2_PFD2] = imx_clk_hw_pfd("pll2_pfd2", "pll2_sys", pll_base + 0x270, 2);
+ hws[IMXRT1170_CLK_PLL2_PFD3] = imx_clk_hw_pfd("pll2_pfd3", "pll2_sys", pll_base + 0x270, 3);
+
+ /* CCM clocks */
+ ccm_base = devm_platform_ioremap_resource(pdev, 0);
+ if (WARN_ON(IS_ERR(ccm_base)))
+ return PTR_ERR(ccm_base);
+
+ hws[IMXRT1170_CLK_M7_SEL] = imx_clk_hw_mux("m7_sel", ccm_base + (m7 * 0x80), 8, 3, root_clocks[m7], 8);
+ hws[IMXRT1170_CLK_M4_SEL] = imx_clk_hw_mux("m4_sel", ccm_base + (m4 * 0x80), 8, 3, root_clocks[m4], 8);
+ hws[IMXRT1170_CLK_BUS_SEL] = imx_clk_hw_mux("bus_sel", ccm_base + (bus * 0x80), 8, 3, root_clocks[bus], 8);
+ hws[IMXRT1170_CLK_BUS_LPSR_SEL] = imx_clk_hw_mux("bus_lpsr_sel", ccm_base + (bus_lpsr * 0x80), 8, 3, root_clocks[bus_lpsr], 8);
+ hws[IMXRT1170_CLK_SEMC_SEL] = imx_clk_hw_mux("semc_sel", ccm_base + (semc * 0x80), 8, 3, root_clocks[semc], 8);
+ hws[IMXRT1170_CLK_CSSYS_SEL] = imx_clk_hw_mux("cssys_sel", ccm_base + (cssys * 0x80), 8, 3, root_clocks[cssys], 8);
+ hws[IMXRT1170_CLK_CSTRACE_SEL] = imx_clk_hw_mux("cstrace_sel", ccm_base + (cstrace * 0x80), 8, 3, root_clocks[cstrace], 8);
+ hws[IMXRT1170_CLK_M4_SYSTICK_SEL] = imx_clk_hw_mux("m4_systick_sel", ccm_base + (m4_systick * 0x80), 8, 3, root_clocks[m4_systick], 8);
+ hws[IMXRT1170_CLK_M7_SYSTICK_SEL] = imx_clk_hw_mux("m7_systick_sel", ccm_base + (m7_systick * 0x80), 8, 3, root_clocks[m7_systick], 8);
+ hws[IMXRT1170_CLK_ADC1_SEL] = imx_clk_hw_mux("adc1_sel", ccm_base + (adc1 * 0x80), 8, 3, root_clocks[adc1], 8);
+ hws[IMXRT1170_CLK_ADC2_SEL] = imx_clk_hw_mux("adc2_sel", ccm_base + (adc2 * 0x80), 8, 3, root_clocks[adc2], 8);
+ hws[IMXRT1170_CLK_ACMP_SEL] = imx_clk_hw_mux("acmp_sel", ccm_base + (acmp * 0x80), 8, 3, root_clocks[acmp], 8);
+ hws[IMXRT1170_CLK_FLEXIO1_SEL] = imx_clk_hw_mux("flexio1_sel", ccm_base + (flexio1 * 0x80), 8, 3, root_clocks[flexio1], 8);
+ hws[IMXRT1170_CLK_FLEXIO2_SEL] = imx_clk_hw_mux("flexio2_sel", ccm_base + (flexio2 * 0x80), 8, 3, root_clocks[flexio2], 8);
+ hws[IMXRT1170_CLK_GPT1_SEL] = imx_clk_hw_mux("gpt1_sel", ccm_base + (gpt1 * 0x80), 8, 3, root_clocks[gpt1], 8);
+ hws[IMXRT1170_CLK_GPT2_SEL] = imx_clk_hw_mux("gpt2_sel", ccm_base + (gpt2 * 0x80), 8, 3, root_clocks[gpt2], 8);
+ hws[IMXRT1170_CLK_GPT3_SEL] = imx_clk_hw_mux("gpt3_sel", ccm_base + (gpt3 * 0x80), 8, 3, root_clocks[gpt3], 8);
+ hws[IMXRT1170_CLK_GPT4_SEL] = imx_clk_hw_mux("gpt4_sel", ccm_base + (gpt4 * 0x80), 8, 3, root_clocks[gpt4], 8);
+ hws[IMXRT1170_CLK_GPT5_SEL] = imx_clk_hw_mux("gpt5_sel", ccm_base + (gpt5 * 0x80), 8, 3, root_clocks[gpt5], 8);
+ hws[IMXRT1170_CLK_GPT6_SEL] = imx_clk_hw_mux("gpt6_sel", ccm_base + (gpt6 * 0x80), 8, 3, root_clocks[gpt6], 8);
+ hws[IMXRT1170_CLK_FLEXSPI1_SEL] = imx_clk_hw_mux("flexspi1_sel", ccm_base + (flexspi1 * 0x80), 8, 3, root_clocks[flexspi1], 8);
+ hws[IMXRT1170_CLK_FLEXSPI2_SEL] = imx_clk_hw_mux("flexspi2_sel", ccm_base + (flexspi2 * 0x80), 8, 3, root_clocks[flexspi2], 8);
+ hws[IMXRT1170_CLK_CAN1_SEL] = imx_clk_hw_mux("can1_sel", ccm_base + (can1 * 0x80), 8, 3, root_clocks[can1], 8);
+ hws[IMXRT1170_CLK_CAN2_SEL] = imx_clk_hw_mux("can2_sel", ccm_base + (can2 * 0x80), 8, 3, root_clocks[can2], 8);
+ hws[IMXRT1170_CLK_CAN3_SEL] = imx_clk_hw_mux("can3_sel", ccm_base + (can3 * 0x80), 8, 3, root_clocks[can3], 8);
+ hws[IMXRT1170_CLK_LPUART1_SEL] = imx_clk_hw_mux("lpuart1_sel", ccm_base + (lpuart1 * 0x80), 8, 3, root_clocks[lpuart1], 8);
+ hws[IMXRT1170_CLK_LPUART2_SEL] = imx_clk_hw_mux("lpuart2_sel", ccm_base + (lpuart2 * 0x80), 8, 3, root_clocks[lpuart2], 8);
+ hws[IMXRT1170_CLK_LPUART3_SEL] = imx_clk_hw_mux("lpuart3_sel", ccm_base + (lpuart3 * 0x80), 8, 3, root_clocks[lpuart3], 8);
+ hws[IMXRT1170_CLK_LPUART4_SEL] = imx_clk_hw_mux("lpuart4_sel", ccm_base + (lpuart4 * 0x80), 8, 3, root_clocks[lpuart4], 8);
+ hws[IMXRT1170_CLK_LPUART5_SEL] = imx_clk_hw_mux("lpuart5_sel", ccm_base + (lpuart5 * 0x80), 8, 3, root_clocks[lpuart5], 8);
+ hws[IMXRT1170_CLK_LPUART6_SEL] = imx_clk_hw_mux("lpuart6_sel", ccm_base + (lpuart6 * 0x80), 8, 3, root_clocks[lpuart6], 8);
+ hws[IMXRT1170_CLK_LPUART7_SEL] = imx_clk_hw_mux("lpuart7_sel", ccm_base + (lpuart7 * 0x80), 8, 3, root_clocks[lpuart7], 8);
+ hws[IMXRT1170_CLK_LPUART8_SEL] = imx_clk_hw_mux("lpuart8_sel", ccm_base + (lpuart8 * 0x80), 8, 3, root_clocks[lpuart8], 8);
+ hws[IMXRT1170_CLK_LPUART9_SEL] = imx_clk_hw_mux("lpuart9_sel", ccm_base + (lpuart9 * 0x80), 8, 3, root_clocks[lpuart9], 8);
+ hws[IMXRT1170_CLK_LPUART10_SEL] = imx_clk_hw_mux("lpuart10_sel", ccm_base + (lpuart10 * 0x80), 8, 3, root_clocks[lpuart10], 8);
+ hws[IMXRT1170_CLK_LPUART11_SEL] = imx_clk_hw_mux("lpuart11_sel", ccm_base + (lpuart11 * 0x80), 8, 3, root_clocks[lpuart11], 8);
+ hws[IMXRT1170_CLK_LPUART12_SEL] = imx_clk_hw_mux("lpuart12_sel", ccm_base + (lpuart12 * 0x80), 8, 3, root_clocks[lpuart12], 8);
+ hws[IMXRT1170_CLK_LPI2C1_SEL] = imx_clk_hw_mux("lpi2c1_sel", ccm_base + (lpi2c1 * 0x80), 8, 3, root_clocks[lpi2c1], 8);
+ hws[IMXRT1170_CLK_LPI2C2_SEL] = imx_clk_hw_mux("lpi2c2_sel", ccm_base + (lpi2c2 * 0x80), 8, 3, root_clocks[lpi2c2], 8);
+ hws[IMXRT1170_CLK_LPI2C3_SEL] = imx_clk_hw_mux("lpi2c3_sel", ccm_base + (lpi2c3 * 0x80), 8, 3, root_clocks[lpi2c3], 8);
+ hws[IMXRT1170_CLK_LPI2C4_SEL] = imx_clk_hw_mux("lpi2c4_sel", ccm_base + (lpi2c4 * 0x80), 8, 3, root_clocks[lpi2c4], 8);
+ hws[IMXRT1170_CLK_LPI2C5_SEL] = imx_clk_hw_mux("lpi2c5_sel", ccm_base + (lpi2c5 * 0x80), 8, 3, root_clocks[lpi2c5], 8);
+ hws[IMXRT1170_CLK_LPI2C6_SEL] = imx_clk_hw_mux("lpi2c6_sel", ccm_base + (lpi2c6 * 0x80), 8, 3, root_clocks[lpi2c6], 8);
+ hws[IMXRT1170_CLK_LPSPI1_SEL] = imx_clk_hw_mux("lpspi1_sel", ccm_base + (lpspi1 * 0x80), 8, 3, root_clocks[lpspi1], 8);
+ hws[IMXRT1170_CLK_LPSPI2_SEL] = imx_clk_hw_mux("lpspi2_sel", ccm_base + (lpspi2 * 0x80), 8, 3, root_clocks[lpspi2], 8);
+ hws[IMXRT1170_CLK_LPSPI3_SEL] = imx_clk_hw_mux("lpspi3_sel", ccm_base + (lpspi3 * 0x80), 8, 3, root_clocks[lpspi3], 8);
+ hws[IMXRT1170_CLK_LPSPI4_SEL] = imx_clk_hw_mux("lpspi4_sel", ccm_base + (lpspi4 * 0x80), 8, 3, root_clocks[lpspi4], 8);
+ hws[IMXRT1170_CLK_LPSPI5_SEL] = imx_clk_hw_mux("lpspi5_sel", ccm_base + (lpspi5 * 0x80), 8, 3, root_clocks[lpspi5], 8);
+ hws[IMXRT1170_CLK_LPSPI6_SEL] = imx_clk_hw_mux("lpspi6_sel", ccm_base + (lpspi6 * 0x80), 8, 3, root_clocks[lpspi6], 8);
+ hws[IMXRT1170_CLK_EMV1_SEL] = imx_clk_hw_mux("emv1_sel", ccm_base + (emv1 * 0x80), 8, 3, root_clocks[emv1], 8);
+ hws[IMXRT1170_CLK_EMV2_SEL] = imx_clk_hw_mux("emv2_sel", ccm_base + (emv2 * 0x80), 8, 3, root_clocks[emv2], 8);
+ hws[IMXRT1170_CLK_ENET1_SEL] = imx_clk_hw_mux("enet1_sel", ccm_base + (enet1 * 0x80), 8, 3, root_clocks[enet1], 8);
+ hws[IMXRT1170_CLK_ENET2_SEL] = imx_clk_hw_mux("enet2_sel", ccm_base + (enet2 * 0x80), 8, 3, root_clocks[enet2], 8);
+ hws[IMXRT1170_CLK_ENET_QOS_SEL] = imx_clk_hw_mux("enet_qos_sel", ccm_base + (enet_qos * 0x80), 8, 3, root_clocks[enet_qos], 8);
+ hws[IMXRT1170_CLK_ENET_25M_SEL] = imx_clk_hw_mux("enet_25m_sel", ccm_base + (enet_25m * 0x80), 8, 3, root_clocks[enet_25m], 8);
+ hws[IMXRT1170_CLK_ENET_TIMER1_SEL] = imx_clk_hw_mux("enet_timer1_sel", ccm_base + (enet_timer1 * 0x80), 8, 3, root_clocks[enet_timer1], 8);
+ hws[IMXRT1170_CLK_ENET_TIMER2_SEL] = imx_clk_hw_mux("enet_timer2_sel", ccm_base + (enet_timer2 * 0x80), 8, 3, root_clocks[enet_timer2], 8);
+ hws[IMXRT1170_CLK_ENET_TIMER3_SEL] = imx_clk_hw_mux("enet_timer3_sel", ccm_base + (enet_timer3 * 0x80), 8, 3, root_clocks[enet_timer3], 8);
+ hws[IMXRT1170_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", ccm_base + (usdhc1 * 0x80), 8, 3, root_clocks[usdhc1], 8);
+ hws[IMXRT1170_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", ccm_base + (usdhc2 * 0x80), 8, 3, root_clocks[usdhc2], 8);
+ hws[IMXRT1170_CLK_ASRC_SEL] = imx_clk_hw_mux("asrc_sel", ccm_base + (asrc * 0x80), 8, 3, root_clocks[asrc], 8);
+ hws[IMXRT1170_CLK_MQS_SEL] = imx_clk_hw_mux("mqs_sel", ccm_base + (mqs * 0x80), 8, 3, root_clocks[mqs], 8);
+ hws[IMXRT1170_CLK_MIC_SEL] = imx_clk_hw_mux("mic_sel", ccm_base + (mic * 0x80), 8, 3, root_clocks[mic], 8);
+ hws[IMXRT1170_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel", ccm_base + (spdif * 0x80), 8, 3, root_clocks[spdif], 8);
+ hws[IMXRT1170_CLK_SAI1_SEL] = imx_clk_hw_mux("sai1_sel", ccm_base + (sai1 * 0x80), 8, 3, root_clocks[sai1], 8);
+ hws[IMXRT1170_CLK_SAI2_SEL] = imx_clk_hw_mux("sai2_sel", ccm_base + (sai2 * 0x80), 8, 3, root_clocks[sai2], 8);
+ hws[IMXRT1170_CLK_SAI3_SEL] = imx_clk_hw_mux("sai3_sel", ccm_base + (sai3 * 0x80), 8, 3, root_clocks[sai3], 8);
+ hws[IMXRT1170_CLK_SAI4_SEL] = imx_clk_hw_mux("sai4_sel", ccm_base + (sai4 * 0x80), 8, 3, root_clocks[sai4], 8);
+ hws[IMXRT1170_CLK_GC355_SEL] = imx_clk_hw_mux("gc355_sel", ccm_base + (gc355 * 0x80), 8, 3, root_clocks[gc355], 8);
+ hws[IMXRT1170_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel", ccm_base + (lcdif * 0x80), 8, 3, root_clocks[lcdif], 8);
+ hws[IMXRT1170_CLK_LCDIFV2_SEL] = imx_clk_hw_mux("lcdifv2_sel", ccm_base + (lcdifv2 * 0x80), 8, 3, root_clocks[lcdifv2], 8);
+ hws[IMXRT1170_CLK_MIPI_REF_SEL] = imx_clk_hw_mux("mipi_ref_sel", ccm_base + (mipi_ref * 0x80), 8, 3, root_clocks[mipi_ref], 8);
+ hws[IMXRT1170_CLK_MIPI_ESC_SEL] = imx_clk_hw_mux("mipi_esc_sel", ccm_base + (mipi_esc * 0x80), 8, 3, root_clocks[mipi_esc], 8);
+ hws[IMXRT1170_CLK_CSI2_SEL] = imx_clk_hw_mux("csi2_sel", ccm_base + (csi2 * 0x80), 8, 3, root_clocks[csi2], 8);
+ hws[IMXRT1170_CLK_CSI2_ESC_SEL] = imx_clk_hw_mux("csi2_esc_sel", ccm_base + (csi2_esc * 0x80), 8, 3, root_clocks[csi2_esc], 8);
+ hws[IMXRT1170_CLK_CSI2_UI_SEL] = imx_clk_hw_mux("csi2_ui_sel", ccm_base + (csi2_ui * 0x80), 8, 3, root_clocks[csi2_ui], 8);
+ hws[IMXRT1170_CLK_CSI_SEL] = imx_clk_hw_mux("csi_sel", ccm_base + (csi * 0x80), 8, 3, root_clocks[csi], 8);
+ hws[IMXRT1170_CLK_CKO1_SEL] = imx_clk_hw_mux("cko1_sel", ccm_base + (cko1 * 0x80), 8, 3, root_clocks[cko1], 8);
+ hws[IMXRT1170_CLK_CKO2_SEL] = imx_clk_hw_mux("cko2_sel", ccm_base + (cko2 * 0x80), 8, 3, root_clocks[cko2], 8);
+
+ hws[IMXRT1170_CLK_M7_GATE] = imx_clk_hw_gate_dis_flags("m7_gate", "m7_sel", ccm_base + (m7 * 0x80), 24, CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_M4_GATE] = imx_clk_hw_gate_dis_flags("m4_gate", "m4_sel", ccm_base + (m4 * 0x80), 24, CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_BUS_GATE] = imx_clk_hw_gate_dis_flags("bus_gate", "bus_sel", ccm_base + (bus * 0x80), 24, CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_BUS_LPSR_GATE] = imx_clk_hw_gate_dis_flags("bus_lpsr_gate", "bus_lpsr_sel", ccm_base + (bus_lpsr * 0x80), 24, CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_SEMC_GATE] = imx_clk_hw_gate_dis_flags("semc_gate", "semc_sel", ccm_base + (semc * 0x80), 24, CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_CSSYS_GATE] = imx_clk_hw_gate_dis_flags("cssys_gate", "cssys_sel", ccm_base + (cssys * 0x80), 24, CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_CSTRACE_GATE] = imx_clk_hw_gate_dis_flags("cstrace_gate", "cstrace_sel", ccm_base + (cstrace * 0x80), 24, CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_M4_SYSTICK_GATE] = imx_clk_hw_gate_dis_flags("m4_systick_gate", "m4_systick_sel", ccm_base + (m4_systick * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_M7_SYSTICK_GATE] = imx_clk_hw_gate_dis_flags("m7_systick_gate", "m7_systick_sel", ccm_base + (m7_systick * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ADC1_GATE] = imx_clk_hw_gate_dis_flags("adc1_gate", "adc1_sel", ccm_base + (adc1 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ADC2_GATE] = imx_clk_hw_gate_dis_flags("adc2_gate", "adc2_sel", ccm_base + (adc2 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ACMP_GATE] = imx_clk_hw_gate_dis_flags("acmp_gate", "acmp_sel", ccm_base + (acmp * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_FLEXIO1_GATE] = imx_clk_hw_gate_dis_flags("flexio1_gate", "flexio1_sel", ccm_base + (flexio1 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_FLEXIO2_GATE] = imx_clk_hw_gate_dis_flags("flexio2_gate", "flexio2_sel", ccm_base + (flexio2 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_GPT1_GATE] = imx_clk_hw_gate_dis_flags("gpt1_gate", "gpt1_sel", ccm_base + (gpt1 * 0x80), 24, CLK_IS_CRITICAL);
+ hws[IMXRT1170_CLK_GPT2_GATE] = imx_clk_hw_gate_dis_flags("gpt2_gate", "gpt2_sel", ccm_base + (gpt2 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_GPT3_GATE] = imx_clk_hw_gate_dis_flags("gpt3_gate", "gpt3_sel", ccm_base + (gpt3 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_GPT4_GATE] = imx_clk_hw_gate_dis_flags("gpt4_gate", "gpt4_sel", ccm_base + (gpt4 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_GPT5_GATE] = imx_clk_hw_gate_dis_flags("gpt5_gate", "gpt5_sel", ccm_base + (gpt5 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_GPT6_GATE] = imx_clk_hw_gate_dis_flags("gpt6_gate", "gpt6_sel", ccm_base + (gpt6 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_FLEXSPI1_GATE] = imx_clk_hw_gate_dis_flags("flexspi1_gate", "flexspi1_sel", ccm_base + (flexspi1 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_FLEXSPI2_GATE] = imx_clk_hw_gate_dis_flags("flexspi2_gate", "flexspi2_sel", ccm_base + (flexspi2 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CAN1_GATE] = imx_clk_hw_gate_dis_flags("can1_gate", "can1_sel", ccm_base + (can1 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CAN2_GATE] = imx_clk_hw_gate_dis_flags("can2_gate", "can2_sel", ccm_base + (can2 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CAN3_GATE] = imx_clk_hw_gate_dis_flags("can3_gate", "can3_sel", ccm_base + (can3 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART1_GATE] = imx_clk_hw_gate_dis_flags("lpuart1_gate", "lpuart1_sel", ccm_base + (lpuart1 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART2_GATE] = imx_clk_hw_gate_dis_flags("lpuart2_gate", "lpuart2_sel", ccm_base + (lpuart2 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART3_GATE] = imx_clk_hw_gate_dis_flags("lpuart3_gate", "lpuart3_sel", ccm_base + (lpuart3 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART4_GATE] = imx_clk_hw_gate_dis_flags("lpuart4_gate", "lpuart4_sel", ccm_base + (lpuart4 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART5_GATE] = imx_clk_hw_gate_dis_flags("lpuart5_gate", "lpuart5_sel", ccm_base + (lpuart5 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART6_GATE] = imx_clk_hw_gate_dis_flags("lpuart6_gate", "lpuart6_sel", ccm_base + (lpuart6 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART7_GATE] = imx_clk_hw_gate_dis_flags("lpuart7_gate", "lpuart7_sel", ccm_base + (lpuart7 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART8_GATE] = imx_clk_hw_gate_dis_flags("lpuart8_gate", "lpuart8_sel", ccm_base + (lpuart8 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART9_GATE] = imx_clk_hw_gate_dis_flags("lpuart9_gate", "lpuart9_sel", ccm_base + (lpuart9 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART10_GATE] = imx_clk_hw_gate_dis_flags("lpuart10_gate", "lpuart10_sel", ccm_base + (lpuart10 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART11_GATE] = imx_clk_hw_gate_dis_flags("lpuart11_gate", "lpuart11_sel", ccm_base + (lpuart11 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPUART12_GATE] = imx_clk_hw_gate_dis_flags("lpuart12_gate", "lpuart12_sel", ccm_base + (lpuart12 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPI2C1_GATE] = imx_clk_hw_gate_dis_flags("lpi2c1_gate", "lpi2c1_sel", ccm_base + (lpi2c1 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPI2C2_GATE] = imx_clk_hw_gate_dis_flags("lpi2c2_gate", "lpi2c2_sel", ccm_base + (lpi2c2 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPI2C3_GATE] = imx_clk_hw_gate_dis_flags("lpi2c3_gate", "lpi2c3_sel", ccm_base + (lpi2c3 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPI2C4_GATE] = imx_clk_hw_gate_dis_flags("lpi2c4_gate", "lpi2c4_sel", ccm_base + (lpi2c4 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPI2C5_GATE] = imx_clk_hw_gate_dis_flags("lpi2c5_gate", "lpi2c5_sel", ccm_base + (lpi2c5 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPI2C6_GATE] = imx_clk_hw_gate_dis_flags("lpi2c6_gate", "lpi2c6_sel", ccm_base + (lpi2c6 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPSPI1_GATE] = imx_clk_hw_gate_dis_flags("lpspi1_gate", "lpspi1_sel", ccm_base + (lpspi1 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPSPI2_GATE] = imx_clk_hw_gate_dis_flags("lpspi2_gate", "lpspi2_sel", ccm_base + (lpspi2 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPSPI3_GATE] = imx_clk_hw_gate_dis_flags("lpspi3_gate", "lpspi3_sel", ccm_base + (lpspi3 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPSPI4_GATE] = imx_clk_hw_gate_dis_flags("lpspi4_gate", "lpspi4_sel", ccm_base + (lpspi4 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPSPI5_GATE] = imx_clk_hw_gate_dis_flags("lpspi5_gate", "lpspi5_sel", ccm_base + (lpspi5 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LPSPI6_GATE] = imx_clk_hw_gate_dis_flags("lpspi6_gate", "lpspi6_sel", ccm_base + (lpspi6 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_EMV1_GATE] = imx_clk_hw_gate_dis_flags("emv1_gate", "emv1_sel", ccm_base + (emv1 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_EMV2_GATE] = imx_clk_hw_gate_dis_flags("emv2_gate", "emv2_sel", ccm_base + (emv2 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ENET1_GATE] = imx_clk_hw_gate_dis_flags("enet1_gate", "enet1_sel", ccm_base + (enet1 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ENET2_GATE] = imx_clk_hw_gate_dis_flags("enet2_gate", "enet2_sel", ccm_base + (enet2 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ENET_QOS_GATE] = imx_clk_hw_gate_dis_flags("enet_qos_gate", "enet_qos_sel", ccm_base + (enet_qos * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ENET_25M_GATE] = imx_clk_hw_gate_dis_flags("enet_25m_gate", "enet_25m_sel", ccm_base + (enet_25m * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ENET_TIMER1_GATE] = imx_clk_hw_gate_dis_flags("enet_timer1_gate", "enet_timer1_sel", ccm_base + (enet_timer1 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ENET_TIMER2_GATE] = imx_clk_hw_gate_dis_flags("enet_timer2_gate", "enet_timer2_sel", ccm_base + (enet_timer2 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ENET_TIMER3_GATE] = imx_clk_hw_gate_dis_flags("enet_timer3_gate", "enet_timer3_sel", ccm_base + (enet_timer3 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_USDHC1_GATE] = imx_clk_hw_gate_dis_flags("usdhc1_gate", "usdhc1_sel", ccm_base + (usdhc1 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_USDHC2_GATE] = imx_clk_hw_gate_dis_flags("usdhc2_gate", "usdhc2_sel", ccm_base + (usdhc2 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_ASRC_GATE] = imx_clk_hw_gate_dis_flags("asrc_gate", "asrc_sel", ccm_base + (asrc * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_MQS_GATE] = imx_clk_hw_gate_dis_flags("mqs_gate", "mqs_sel", ccm_base + (mqs * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_MIC_GATE] = imx_clk_hw_gate_dis_flags("mic_gate", "mic_sel", ccm_base + (mic * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_SPDIF_GATE] = imx_clk_hw_gate_dis_flags("spdif_gate", "spdif_sel", ccm_base + (spdif * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_SAI1_GATE] = imx_clk_hw_gate_dis_flags("sai1_gate", "sai1_sel", ccm_base + (sai1 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_SAI2_GATE] = imx_clk_hw_gate_dis_flags("sai2_gate", "sai2_sel", ccm_base + (sai2 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_SAI3_GATE] = imx_clk_hw_gate_dis_flags("sai3_gate", "sai3_sel", ccm_base + (sai3 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_SAI4_GATE] = imx_clk_hw_gate_dis_flags("sai4_gate", "sai4_sel", ccm_base + (sai4 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_GC355_GATE] = imx_clk_hw_gate_dis_flags("gc355_gate", "gc355_sel", ccm_base + (gc355 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LCDIF_GATE] = imx_clk_hw_gate_dis_flags("lcdif_gate", "lcdif_sel", ccm_base + (lcdif * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_LCDIFV2_GATE] = imx_clk_hw_gate_dis_flags("lcdifv2_gate", "lcdifv2_sel", ccm_base + (lcdifv2 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_MIPI_REF_GATE] = imx_clk_hw_gate_dis_flags("mipi_ref_gate", "mipi_ref_sel", ccm_base + (mipi_ref * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_MIPI_ESC_GATE] = imx_clk_hw_gate_dis_flags("mipi_esc_gate", "mipi_esc_sel", ccm_base + (mipi_esc * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CSI2_GATE] = imx_clk_hw_gate_dis_flags("csi2_gate", "csi2_sel", ccm_base + (csi2 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CSI2_ESC_GATE] = imx_clk_hw_gate_dis_flags("csi2_esc_gate", "csi2_esc_sel", ccm_base + (csi2_esc * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CSI2_UI_GATE] = imx_clk_hw_gate_dis_flags("csi2_ui_gate", "csi2_ui_sel", ccm_base + (csi2_ui * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CSI_GATE] = imx_clk_hw_gate_dis_flags("csi_gate", "csi_sel", ccm_base + (csi * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CKO1_GATE] = imx_clk_hw_gate_dis_flags("cko1_gate", "cko1_sel", ccm_base + (cko1 * 0x80), 24, 0);
+ hws[IMXRT1170_CLK_CKO2_GATE] = imx_clk_hw_gate_dis_flags("cko2_gate", "cko2_sel", ccm_base + (cko2 * 0x80), 24, 0);
+
+ hws[IMXRT1170_CLK_M7] = imx_clk_hw_divider("m7", "m7_gate", ccm_base + (m7 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_M4] = imx_clk_hw_divider("m4", "m4_gate", ccm_base + (m4 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_BUS] = imx_clk_hw_divider("bus", "bus_gate", ccm_base + (bus * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_BUS_LPSR] = imx_clk_hw_divider("bus_lpsr", "bus_lpsr_gate", ccm_base + (bus_lpsr * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_SEMC] = imx_clk_hw_divider("semc", "semc_gate", ccm_base + (semc * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CSSYS] = imx_clk_hw_divider("cssys", "cssys_gate", ccm_base + (cssys * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CSTRACE] = imx_clk_hw_divider("cstrace", "cstrace_gate", ccm_base + (cstrace * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_M4_SYSTICK] = imx_clk_hw_divider("m4_systick", "m4_systick_gate", ccm_base + (m4_systick * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_M7_SYSTICK] = imx_clk_hw_divider("m7_systick", "m7_systick_gate", ccm_base + (m7_systick * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ADC1] = imx_clk_hw_divider("adc1", "adc1_gate", ccm_base + (adc1 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ADC2] = imx_clk_hw_divider("adc2", "adc2_gate", ccm_base + (adc2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ACMP] = imx_clk_hw_divider("acmp", "acmp_gate", ccm_base + (acmp * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_FLEXIO1] = imx_clk_hw_divider("flexio1", "flexio1_gate", ccm_base + (flexio1 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_FLEXIO2] = imx_clk_hw_divider("flexio2", "flexio2_gate", ccm_base + (flexio2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_GPT1] = imx_clk_hw_divider("gpt1", "gpt1_gate", ccm_base + (gpt1 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_GPT2] = imx_clk_hw_divider("gpt2", "gpt2_gate", ccm_base + (gpt2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_GPT3] = imx_clk_hw_divider("gpt3", "gpt3_gate", ccm_base + (gpt3 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_GPT4] = imx_clk_hw_divider("gpt4", "gpt4_gate", ccm_base + (gpt4 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_GPT5] = imx_clk_hw_divider("gpt5", "gpt5_gate", ccm_base + (gpt5 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_GPT6] = imx_clk_hw_divider("gpt6", "gpt6_gate", ccm_base + (gpt6 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_FLEXSPI1] = imx_clk_hw_divider("flexspi1", "flexspi1_gate", ccm_base + (flexspi1 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_FLEXSPI2] = imx_clk_hw_divider("flexspi2", "flexspi2_gate", ccm_base + (flexspi2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CAN1] = imx_clk_hw_divider("can1", "can1_gate", ccm_base + (can1 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CAN2] = imx_clk_hw_divider("can2", "can2_gate", ccm_base + (can2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CAN3] = imx_clk_hw_divider("can3", "can3_gate", ccm_base + (can3 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART1] = imx_clk_hw_divider("lpuart1", "lpuart1_gate", ccm_base + (lpuart1 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART2] = imx_clk_hw_divider("lpuart2", "lpuart2_gate", ccm_base + (lpuart2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART3] = imx_clk_hw_divider("lpuart3", "lpuart3_gate", ccm_base + (lpuart3 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART4] = imx_clk_hw_divider("lpuart4", "lpuart4_gate", ccm_base + (lpuart4 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART5] = imx_clk_hw_divider("lpuart5", "lpuart5_gate", ccm_base + (lpuart5 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART6] = imx_clk_hw_divider("lpuart6", "lpuart6_gate", ccm_base + (lpuart6 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART7] = imx_clk_hw_divider("lpuart7", "lpuart7_gate", ccm_base + (lpuart7 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART8] = imx_clk_hw_divider("lpuart8", "lpuart8_gate", ccm_base + (lpuart8 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART9] = imx_clk_hw_divider("lpuart9", "lpuart9_gate", ccm_base + (lpuart9 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART10] = imx_clk_hw_divider("lpuart10", "lpuart10_gate", ccm_base + (lpuart10 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART11] = imx_clk_hw_divider("lpuart11", "lpuart11_gate", ccm_base + (lpuart11 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPUART12] = imx_clk_hw_divider("lpuart12", "lpuart12_gate", ccm_base + (lpuart12 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPI2C1] = imx_clk_hw_divider("lpi2c1", "lpi2c1_gate", ccm_base + (lpi2c1 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPI2C2] = imx_clk_hw_divider("lpi2c2", "lpi2c2_gate", ccm_base + (lpi2c2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPI2C3] = imx_clk_hw_divider("lpi2c3", "lpi2c3_gate", ccm_base + (lpi2c3 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPI2C4] = imx_clk_hw_divider("lpi2c4", "lpi2c4_gate", ccm_base + (lpi2c4 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPI2C5] = imx_clk_hw_divider("lpi2c5", "lpi2c5_gate", ccm_base + (lpi2c5 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPI2C6] = imx_clk_hw_divider("lpi2c6", "lpi2c6_gate", ccm_base + (lpi2c6 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPSPI1] = imx_clk_hw_divider("lpspi1", "lpspi1_gate", ccm_base + (lpspi1 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPSPI2] = imx_clk_hw_divider("lpspi2", "lpspi2_gate", ccm_base + (lpspi2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPSPI3] = imx_clk_hw_divider("lpspi3", "lpspi3_gate", ccm_base + (lpspi3 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPSPI4] = imx_clk_hw_divider("lpspi4", "lpspi4_gate", ccm_base + (lpspi4 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPSPI5] = imx_clk_hw_divider("lpspi5", "lpspi5_gate", ccm_base + (lpspi5 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LPSPI6] = imx_clk_hw_divider("lpspi6", "lpspi6_gate", ccm_base + (lpspi6 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_EMV1] = imx_clk_hw_divider("emv1", "emv1_gate", ccm_base + (emv1 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_EMV2] = imx_clk_hw_divider("emv2", "emv2_gate", ccm_base + (emv2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ENET1] = imx_clk_hw_divider("enet1", "enet1_gate", ccm_base + (enet1 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ENET2] = imx_clk_hw_divider("enet2", "enet2_gate", ccm_base + (enet2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ENET_QOS] = imx_clk_hw_divider("enet_qos", "enet_qos_gate", ccm_base + (enet_qos * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ENET_25M] = imx_clk_hw_divider("enet_25m", "enet_25m_gate", ccm_base + (enet_25m * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ENET_TIMER1] = imx_clk_hw_divider("enet_timer1", "enet_timer1_gate", ccm_base + (enet_timer1 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ENET_TIMER2] = imx_clk_hw_divider("enet_timer2", "enet_timer2_gate", ccm_base + (enet_timer2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ENET_TIMER3] = imx_clk_hw_divider("enet_timer3", "enet_timer3_gate", ccm_base + (enet_timer3 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_USDHC1] = imx_clk_hw_divider("usdhc1", "usdhc1_gate", ccm_base + (usdhc1 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_USDHC2] = imx_clk_hw_divider("usdhc2", "usdhc2_gate", ccm_base + (usdhc2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_ASRC] = imx_clk_hw_divider("asrc", "asrc_gate", ccm_base + (asrc * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_MQS] = imx_clk_hw_divider("mqs", "mqs_gate", ccm_base + (mqs * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_MIC] = imx_clk_hw_divider("mic", "mic_gate", ccm_base + (mic * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_SPDIF] = imx_clk_hw_divider("spdif", "spdif_gate", ccm_base + (spdif * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_SAI1] = imx_clk_hw_divider("sai1", "sai1_gate", ccm_base + (sai1 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_SAI2] = imx_clk_hw_divider("sai2", "sai2_gate", ccm_base + (sai2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_SAI3] = imx_clk_hw_divider("sai3", "sai3_gate", ccm_base + (sai3 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_SAI4] = imx_clk_hw_divider("sai4", "sai4_gate", ccm_base + (sai4 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_GC355] = imx_clk_hw_divider("gc355", "gc355_gate", ccm_base + (gc355 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LCDIF] = imx_clk_hw_divider("lcdif", "lcdif_gate", ccm_base + (lcdif * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_LCDIFV2] = imx_clk_hw_divider("lcdifv2", "lcdifv2_gate", ccm_base + (lcdifv2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_MIPI_REF] = imx_clk_hw_divider("mipi_ref", "mipi_ref_gate", ccm_base + (mipi_ref * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_MIPI_ESC] = imx_clk_hw_divider("mipi_esc", "mipi_esc_gate", ccm_base + (mipi_esc * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CSI2] = imx_clk_hw_divider("csi2", "csi2_gate", ccm_base + (csi2 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CSI2_ESC] = imx_clk_hw_divider("csi2_esc", "csi2_esc_gate", ccm_base + (csi2_esc * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CSI2_UI] = imx_clk_hw_divider("csi2_ui", "csi2_ui_gate", ccm_base + (csi2_ui * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CSI] = imx_clk_hw_divider("csi", "csi_gate", ccm_base + (csi * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CKO1] = imx_clk_hw_divider("cko1", "cko1_gate", ccm_base + (cko1 * 0x80), 0, 8);
+ hws[IMXRT1170_CLK_CKO2] = imx_clk_hw_divider("cko2", "cko2_gate", ccm_base + (cko2 * 0x80), 0, 8);
+
+ hws[IMXRT1170_CLK_USB] = imx_clk_hw_gate("usb", "bus", ccm_base + LPCG_GATE(115), 0);
+
+ imx_check_clk_hws(hws, IMXRT1170_CLK_END);
+
+ ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
+ if (ret < 0) {
+ dev_err(dev, "Failed to register clks for i.MXRT1170.\n");
+ imx_unregister_hw_clocks(hws, IMXRT1170_CLK_END);
+ }
+ return ret;
+}
+
+static const struct of_device_id imxrt1170_clk_of_match[] = {
+ { .compatible = "fsl,imxrt1170-ccm" },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, imxrt1170_clk_of_match);
+
+static struct platform_driver imxrt1170_clk_driver = {
+ .probe = imxrt1170_clocks_probe,
+ .driver = {
+ .name = "imxrt1170-ccm",
+ .of_match_table = imxrt1170_clk_of_match,
+ },
+};
+module_platform_driver(imxrt1170_clk_driver);
--
2.35.1
Add DT binding documentation for i.MXRT1170 clock driver.
Cc: Giulio Benetti <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- Change title to Clock Controller
- Rename to add fsl
---
.../bindings/clock/fsl,imxrt1170-clock.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/fsl,imxrt1170-clock.yaml
diff --git a/Documentation/devicetree/bindings/clock/fsl,imxrt1170-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,imxrt1170-clock.yaml
new file mode 100644
index 000000000000..a092ac0f7a50
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fsl,imxrt1170-clock.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imxrt1170-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MXRT1170 Clock Controller
+
+maintainers:
+ - Giulio Benetti <[email protected]>
+ - Jesse Taube <[email protected]>
+
+description: |
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See include/dt-bindings/clock/imxrt*-clock.h
+ for the full list of i.MXRT clock IDs.
+
+properties:
+ compatible:
+ const: fsl,imxrt1170-ccm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: 32M ext osc
+ - description: 16M int rcosc
+ - description: 32k osc
+
+ clock-names:
+ items:
+ - const: osc
+ - const: rcosc16M
+ - const: osc32k
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imxrt1170-clock.h>
+
+ clks: clock-controller@40cc0000 {
+ compatible = "fsl,imxrt1170-ccm";
+ reg = <0x40cc0000 0x4000>;
+ clocks = <&osc>, <&rcosc16M>, <&osc32k>;
+ clock-names = "osc", "rcosc16M", "osc32k";
+ #clock-cells = <1>;
+ };
--
2.35.1
Add the clock binding doc for i.MXRT1170.
Cc: Giulio Benetti <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- Change to GPL-2.0-only
---
include/dt-bindings/clock/imxrt1170-clock.h | 282 ++++++++++++++++++++
1 file changed, 282 insertions(+)
create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h
diff --git a/include/dt-bindings/clock/imxrt1170-clock.h b/include/dt-bindings/clock/imxrt1170-clock.h
new file mode 100644
index 000000000000..a88137f6cbc1
--- /dev/null
+++ b/include/dt-bindings/clock/imxrt1170-clock.h
@@ -0,0 +1,282 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright(C) 2022
+ * Author(s): Jesse Taube <[email protected]>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMXRT1170_H
+#define __DT_BINDINGS_CLOCK_IMXRT1170_H
+
+#define IMXRT1170_CLK_DUMMY 0
+#define IMXRT1170_CLK_OSC 1
+#define IMXRT1170_CLK_OSC_32K 2
+#define IMXRT1170_CLK_RCOSC_16M 3
+#define IMXRT1170_CLK_RCOSC_48M 4
+#define IMXRT1170_CLK_RCOSC_48M_DIV2 5
+#define IMXRT1170_CLK_RCOSC_400M 6
+#define IMXRT1170_CLK_PLL_ARM_PRE 7
+#define IMXRT1170_CLK_PLL_ARM_BYPASS 8
+#define IMXRT1170_CLK_PLL_ARM_DIV 9
+#define IMXRT1170_CLK_PLL_ARM 10
+#define IMXRT1170_CLK_PLL_AUDIO 11
+#define IMXRT1170_CLK_PLL_VIDEO 12
+#define IMXRT1170_CLK_PLL1 13
+#define IMXRT1170_CLK_PLL1_DIV2 14
+#define IMXRT1170_CLK_PLL1_DIV5 15
+#define IMXRT1170_CLK_PLL2_PRE 16
+#define IMXRT1170_CLK_PLL2_BYPASS 17
+#define IMXRT1170_CLK_PLL2 18
+#define IMXRT1170_CLK_PLL2_PFD0 19
+#define IMXRT1170_CLK_PLL2_PFD1 20
+#define IMXRT1170_CLK_PLL2_PFD2 21
+#define IMXRT1170_CLK_PLL2_PFD3 22
+#define IMXRT1170_CLK_PLL3_PRE 23
+#define IMXRT1170_CLK_PLL3_BYPASS 24
+#define IMXRT1170_CLK_PLL3 25
+#define IMXRT1170_CLK_PLL3_DIV2_GATE 26
+#define IMXRT1170_CLK_PLL3_DIV2 27
+#define IMXRT1170_CLK_PLL3_PFD0 28
+#define IMXRT1170_CLK_PLL3_PFD1 29
+#define IMXRT1170_CLK_PLL3_PFD2 30
+#define IMXRT1170_CLK_PLL3_PFD3 31
+#define IMXRT1170_CLK_M7_SEL 32
+#define IMXRT1170_CLK_M7_GATE 33
+#define IMXRT1170_CLK_M7 34
+#define IMXRT1170_CLK_M4_SEL 35
+#define IMXRT1170_CLK_M4_GATE 36
+#define IMXRT1170_CLK_M4 37
+#define IMXRT1170_CLK_BUS_SEL 38
+#define IMXRT1170_CLK_BUS_GATE 39
+#define IMXRT1170_CLK_BUS 40
+#define IMXRT1170_CLK_BUS_LPSR_SEL 41
+#define IMXRT1170_CLK_BUS_LPSR_GATE 42
+#define IMXRT1170_CLK_BUS_LPSR 43
+#define IMXRT1170_CLK_SEMC_SEL 44
+#define IMXRT1170_CLK_SEMC_GATE 45
+#define IMXRT1170_CLK_SEMC 46
+#define IMXRT1170_CLK_CSSYS_SEL 47
+#define IMXRT1170_CLK_CSSYS_GATE 48
+#define IMXRT1170_CLK_CSSYS 49
+#define IMXRT1170_CLK_CSTRACE_SEL 50
+#define IMXRT1170_CLK_CSTRACE_GATE 51
+#define IMXRT1170_CLK_CSTRACE 52
+#define IMXRT1170_CLK_M4_SYSTICK_SEL 53
+#define IMXRT1170_CLK_M4_SYSTICK_GATE 54
+#define IMXRT1170_CLK_M4_SYSTICK 55
+#define IMXRT1170_CLK_M7_SYSTICK_SEL 56
+#define IMXRT1170_CLK_M7_SYSTICK_GATE 57
+#define IMXRT1170_CLK_M7_SYSTICK 58
+#define IMXRT1170_CLK_ADC1_SEL 59
+#define IMXRT1170_CLK_ADC1_GATE 60
+#define IMXRT1170_CLK_ADC1 61
+#define IMXRT1170_CLK_ADC2_SEL 62
+#define IMXRT1170_CLK_ADC2_GATE 63
+#define IMXRT1170_CLK_ADC2 64
+#define IMXRT1170_CLK_ACMP_SEL 65
+#define IMXRT1170_CLK_ACMP_GATE 66
+#define IMXRT1170_CLK_ACMP 67
+#define IMXRT1170_CLK_FLEXIO1_SEL 68
+#define IMXRT1170_CLK_FLEXIO1_GATE 69
+#define IMXRT1170_CLK_FLEXIO1 70
+#define IMXRT1170_CLK_FLEXIO2_SEL 71
+#define IMXRT1170_CLK_FLEXIO2_GATE 72
+#define IMXRT1170_CLK_FLEXIO2 73
+#define IMXRT1170_CLK_GPT1_SEL 74
+#define IMXRT1170_CLK_GPT1_GATE 75
+#define IMXRT1170_CLK_GPT1 76
+#define IMXRT1170_CLK_GPT2_SEL 77
+#define IMXRT1170_CLK_GPT2_GATE 78
+#define IMXRT1170_CLK_GPT2 79
+#define IMXRT1170_CLK_GPT3_SEL 80
+#define IMXRT1170_CLK_GPT3_GATE 81
+#define IMXRT1170_CLK_GPT3 82
+#define IMXRT1170_CLK_GPT4_SEL 83
+#define IMXRT1170_CLK_GPT4_GATE 84
+#define IMXRT1170_CLK_GPT4 85
+#define IMXRT1170_CLK_GPT5_SEL 86
+#define IMXRT1170_CLK_GPT5_GATE 87
+#define IMXRT1170_CLK_GPT5 88
+#define IMXRT1170_CLK_GPT6_SEL 89
+#define IMXRT1170_CLK_GPT6_GATE 90
+#define IMXRT1170_CLK_GPT6 91
+#define IMXRT1170_CLK_FLEXSPI1_SEL 92
+#define IMXRT1170_CLK_FLEXSPI1_GATE 93
+#define IMXRT1170_CLK_FLEXSPI1 94
+#define IMXRT1170_CLK_FLEXSPI2_SEL 95
+#define IMXRT1170_CLK_FLEXSPI2_GATE 96
+#define IMXRT1170_CLK_FLEXSPI2 97
+#define IMXRT1170_CLK_CAN1_SEL 98
+#define IMXRT1170_CLK_CAN1_GATE 99
+#define IMXRT1170_CLK_CAN1 100
+#define IMXRT1170_CLK_CAN2_SEL 101
+#define IMXRT1170_CLK_CAN2_GATE 102
+#define IMXRT1170_CLK_CAN2 103
+#define IMXRT1170_CLK_CAN3_SEL 104
+#define IMXRT1170_CLK_CAN3_GATE 105
+#define IMXRT1170_CLK_CAN3 106
+#define IMXRT1170_CLK_LPUART1_SEL 107
+#define IMXRT1170_CLK_LPUART1_GATE 108
+#define IMXRT1170_CLK_LPUART1 109
+#define IMXRT1170_CLK_LPUART2_SEL 110
+#define IMXRT1170_CLK_LPUART2_GATE 111
+#define IMXRT1170_CLK_LPUART2 112
+#define IMXRT1170_CLK_LPUART3_SEL 113
+#define IMXRT1170_CLK_LPUART3_GATE 114
+#define IMXRT1170_CLK_LPUART3 115
+#define IMXRT1170_CLK_LPUART4_SEL 116
+#define IMXRT1170_CLK_LPUART4_GATE 117
+#define IMXRT1170_CLK_LPUART4 118
+#define IMXRT1170_CLK_LPUART5_SEL 119
+#define IMXRT1170_CLK_LPUART5_GATE 120
+#define IMXRT1170_CLK_LPUART5 121
+#define IMXRT1170_CLK_LPUART6_SEL 122
+#define IMXRT1170_CLK_LPUART6_GATE 123
+#define IMXRT1170_CLK_LPUART6 124
+#define IMXRT1170_CLK_LPUART7_SEL 125
+#define IMXRT1170_CLK_LPUART7_GATE 126
+#define IMXRT1170_CLK_LPUART7 127
+#define IMXRT1170_CLK_LPUART8_SEL 128
+#define IMXRT1170_CLK_LPUART8_GATE 129
+#define IMXRT1170_CLK_LPUART8 130
+#define IMXRT1170_CLK_LPUART9_SEL 131
+#define IMXRT1170_CLK_LPUART9_GATE 132
+#define IMXRT1170_CLK_LPUART9 133
+#define IMXRT1170_CLK_LPUART10_SEL 134
+#define IMXRT1170_CLK_LPUART10_GATE 135
+#define IMXRT1170_CLK_LPUART10 136
+#define IMXRT1170_CLK_LPUART11_SEL 137
+#define IMXRT1170_CLK_LPUART11_GATE 138
+#define IMXRT1170_CLK_LPUART11 139
+#define IMXRT1170_CLK_LPUART12_SEL 140
+#define IMXRT1170_CLK_LPUART12_GATE 141
+#define IMXRT1170_CLK_LPUART12 142
+#define IMXRT1170_CLK_LPI2C1_SEL 143
+#define IMXRT1170_CLK_LPI2C1_GATE 144
+#define IMXRT1170_CLK_LPI2C1 145
+#define IMXRT1170_CLK_LPI2C2_SEL 146
+#define IMXRT1170_CLK_LPI2C2_GATE 147
+#define IMXRT1170_CLK_LPI2C2 148
+#define IMXRT1170_CLK_LPI2C3_SEL 149
+#define IMXRT1170_CLK_LPI2C3_GATE 150
+#define IMXRT1170_CLK_LPI2C3 151
+#define IMXRT1170_CLK_LPI2C4_SEL 152
+#define IMXRT1170_CLK_LPI2C4_GATE 153
+#define IMXRT1170_CLK_LPI2C4 154
+#define IMXRT1170_CLK_LPI2C5_SEL 155
+#define IMXRT1170_CLK_LPI2C5_GATE 156
+#define IMXRT1170_CLK_LPI2C5 157
+#define IMXRT1170_CLK_LPI2C6_SEL 158
+#define IMXRT1170_CLK_LPI2C6_GATE 159
+#define IMXRT1170_CLK_LPI2C6 160
+#define IMXRT1170_CLK_LPSPI1_SEL 161
+#define IMXRT1170_CLK_LPSPI1_GATE 162
+#define IMXRT1170_CLK_LPSPI1 163
+#define IMXRT1170_CLK_LPSPI2_SEL 164
+#define IMXRT1170_CLK_LPSPI2_GATE 165
+#define IMXRT1170_CLK_LPSPI2 166
+#define IMXRT1170_CLK_LPSPI3_SEL 167
+#define IMXRT1170_CLK_LPSPI3_GATE 168
+#define IMXRT1170_CLK_LPSPI3 169
+#define IMXRT1170_CLK_LPSPI4_SEL 170
+#define IMXRT1170_CLK_LPSPI4_GATE 171
+#define IMXRT1170_CLK_LPSPI4 172
+#define IMXRT1170_CLK_LPSPI5_SEL 173
+#define IMXRT1170_CLK_LPSPI5_GATE 174
+#define IMXRT1170_CLK_LPSPI5 175
+#define IMXRT1170_CLK_LPSPI6_SEL 176
+#define IMXRT1170_CLK_LPSPI6_GATE 177
+#define IMXRT1170_CLK_LPSPI6 178
+#define IMXRT1170_CLK_EMV1_SEL 179
+#define IMXRT1170_CLK_EMV1_GATE 180
+#define IMXRT1170_CLK_EMV1 181
+#define IMXRT1170_CLK_EMV2_SEL 182
+#define IMXRT1170_CLK_EMV2_GATE 183
+#define IMXRT1170_CLK_EMV2 184
+#define IMXRT1170_CLK_ENET1_SEL 185
+#define IMXRT1170_CLK_ENET1_GATE 186
+#define IMXRT1170_CLK_ENET1 187
+#define IMXRT1170_CLK_ENET2_SEL 188
+#define IMXRT1170_CLK_ENET2_GATE 189
+#define IMXRT1170_CLK_ENET2 190
+#define IMXRT1170_CLK_ENET_QOS_SEL 191
+#define IMXRT1170_CLK_ENET_QOS_GATE 192
+#define IMXRT1170_CLK_ENET_QOS 193
+#define IMXRT1170_CLK_ENET_25M_SEL 194
+#define IMXRT1170_CLK_ENET_25M_GATE 195
+#define IMXRT1170_CLK_ENET_25M 196
+#define IMXRT1170_CLK_ENET_TIMER1_SEL 197
+#define IMXRT1170_CLK_ENET_TIMER1_GATE 198
+#define IMXRT1170_CLK_ENET_TIMER1 199
+#define IMXRT1170_CLK_ENET_TIMER2_SEL 200
+#define IMXRT1170_CLK_ENET_TIMER2_GATE 201
+#define IMXRT1170_CLK_ENET_TIMER2 202
+#define IMXRT1170_CLK_ENET_TIMER3_SEL 203
+#define IMXRT1170_CLK_ENET_TIMER3_GATE 204
+#define IMXRT1170_CLK_ENET_TIMER3 205
+#define IMXRT1170_CLK_USDHC1_SEL 206
+#define IMXRT1170_CLK_USDHC1_GATE 207
+#define IMXRT1170_CLK_USDHC1 208
+#define IMXRT1170_CLK_USDHC2_SEL 209
+#define IMXRT1170_CLK_USDHC2_GATE 210
+#define IMXRT1170_CLK_USDHC2 211
+#define IMXRT1170_CLK_ASRC_SEL 212
+#define IMXRT1170_CLK_ASRC_GATE 213
+#define IMXRT1170_CLK_ASRC 214
+#define IMXRT1170_CLK_MQS_SEL 215
+#define IMXRT1170_CLK_MQS_GATE 216
+#define IMXRT1170_CLK_MQS 217
+#define IMXRT1170_CLK_MIC_SEL 218
+#define IMXRT1170_CLK_MIC_GATE 219
+#define IMXRT1170_CLK_MIC 220
+#define IMXRT1170_CLK_SPDIF_SEL 221
+#define IMXRT1170_CLK_SPDIF_GATE 222
+#define IMXRT1170_CLK_SPDIF 223
+#define IMXRT1170_CLK_SAI1_SEL 224
+#define IMXRT1170_CLK_SAI1_GATE 225
+#define IMXRT1170_CLK_SAI1 226
+#define IMXRT1170_CLK_SAI2_SEL 227
+#define IMXRT1170_CLK_SAI2_GATE 228
+#define IMXRT1170_CLK_SAI2 229
+#define IMXRT1170_CLK_SAI3_SEL 230
+#define IMXRT1170_CLK_SAI3_GATE 231
+#define IMXRT1170_CLK_SAI3 232
+#define IMXRT1170_CLK_SAI4_SEL 233
+#define IMXRT1170_CLK_SAI4_GATE 234
+#define IMXRT1170_CLK_SAI4 235
+#define IMXRT1170_CLK_GC355_SEL 236
+#define IMXRT1170_CLK_GC355_GATE 237
+#define IMXRT1170_CLK_GC355 238
+#define IMXRT1170_CLK_LCDIF_SEL 239
+#define IMXRT1170_CLK_LCDIF_GATE 240
+#define IMXRT1170_CLK_LCDIF 241
+#define IMXRT1170_CLK_LCDIFV2_SEL 242
+#define IMXRT1170_CLK_LCDIFV2_GATE 243
+#define IMXRT1170_CLK_LCDIFV2 244
+#define IMXRT1170_CLK_MIPI_REF_SEL 245
+#define IMXRT1170_CLK_MIPI_REF_GATE 246
+#define IMXRT1170_CLK_MIPI_REF 247
+#define IMXRT1170_CLK_MIPI_ESC_SEL 248
+#define IMXRT1170_CLK_MIPI_ESC_GATE 249
+#define IMXRT1170_CLK_MIPI_ESC 250
+#define IMXRT1170_CLK_CSI2_SEL 251
+#define IMXRT1170_CLK_CSI2_GATE 252
+#define IMXRT1170_CLK_CSI2 253
+#define IMXRT1170_CLK_CSI2_ESC_SEL 254
+#define IMXRT1170_CLK_CSI2_ESC_GATE 255
+#define IMXRT1170_CLK_CSI2_ESC 256
+#define IMXRT1170_CLK_CSI2_UI_SEL 257
+#define IMXRT1170_CLK_CSI2_UI_GATE 258
+#define IMXRT1170_CLK_CSI2_UI 259
+#define IMXRT1170_CLK_CSI_SEL 260
+#define IMXRT1170_CLK_CSI_GATE 261
+#define IMXRT1170_CLK_CSI 262
+#define IMXRT1170_CLK_CKO1_SEL 263
+#define IMXRT1170_CLK_CKO1_GATE 264
+#define IMXRT1170_CLK_CKO1 265
+#define IMXRT1170_CLK_CKO2_SEL 266
+#define IMXRT1170_CLK_CKO2_GATE 267
+#define IMXRT1170_CLK_CKO2 268
+#define IMXRT1170_CLK_USB 269
+#define IMXRT1170_CLK_END 270
+
+#endif /* __DT_BINDINGS_CLOCK_IMXRT1170_H */
--
2.35.1
Recently the imxrt1050 was added but the cpu compatible node wasn't
added. Add both i.MXRT1170 and 1050 compatibles to fsl.yaml.
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- Swap order of soc's
---
Documentation/devicetree/bindings/arm/fsl.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 0b595b26061f..e71b981b0245 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -834,6 +834,18 @@ properties:
- const: toradex,colibri-imx8x
- const: fsl,imx8qxp
+ - description: i.MXRT1050 based Boards
+ items:
+ - enum:
+ - fsl,imxrt1050-evk # i.MXRT1050 EVK Board
+ - const: fsl,imxrt1050
+
+ - description: i.MXRT1170 based Boards
+ items:
+ - enum:
+ - fsl,imxrt1170-evk # i.MXRT1170 EVK Board
+ - const: fsl,imxrt1170
+
- description:
Freescale Vybrid Platform Device Tree Bindings
--
2.35.1
The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MXRT, which features NXP's implementation of the Arm
Cortex-M7 and M4 core.
The EVK provides 64 MB SDRAM, 128 MB Quad SPI flash, Micro SD card socket,
two USB 2.0 OTG, and two Ethernet ports.
This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
SD/MMC
Cc: Giulio Benetti <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- Add ipg clock for gpt
- Change mmc, uart and gpt compatibles
- Group fsl,pins for dtbs_check
- Remove underscore from pinctrl_usbotg1_id
- Remove unused fsl,mux_mask
- Rename ccm to clock-controller
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/imxrt1170-evk.dts | 110 +++++++++++
arch/arm/boot/dts/imxrt1170.dtsi | 276 ++++++++++++++++++++++++++++
3 files changed, 388 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/imxrt1170-evk.dts
create mode 100644 arch/arm/boot/dts/imxrt1170.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 07acd6189cae..87ae30818f39 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -724,7 +724,8 @@ dtb-$(CONFIG_SOC_IMX7ULP) += \
imx7ulp-com.dtb \
imx7ulp-evk.dtb
dtb-$(CONFIG_SOC_IMXRT) += \
- imxrt1050-evk.dtb
+ imxrt1050-evk.dtb \
+ imxrt1170-evk.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-moxa-uc-8410a.dtb \
ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/imxrt1170-evk.dts b/arch/arm/boot/dts/imxrt1170-evk.dts
new file mode 100644
index 000000000000..cac74d86168f
--- /dev/null
+++ b/arch/arm/boot/dts/imxrt1170-evk.dts
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube <[email protected]>
+ */
+
+/dts-v1/;
+#include "imxrt1170.dtsi"
+#include "imxrt1170-pinfunc.h"
+
+/ {
+ model = "NXP imxrt1170-evk board";
+ compatible = "fsl,imxrt1170-evk", "fsl,imxrt1170";
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ aliases {
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ gpio3 = &gpio4;
+ gpio4 = &gpio5;
+ gpio5 = &gpio6;
+ gpio6 = &gpio7;
+ gpio7 = &gpio8;
+ gpio8 = &gpio9;
+ gpio9 = &gpio10;
+ gpio10 = &gpio11;
+ gpio11 = &gpio12;
+ gpio12 = &gpio13;
+ mmc0 = &usdhc1;
+ serial0 = &lpuart1;
+ usbphy0 = &usbphy1;
+ };
+
+ memory@20240000 {
+ device_type = "memory";
+ reg = <0x20240000 0xf0000>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x4000000>;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm0>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio9 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&lpuart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+
+&usbotg1 {
+ vbus-supply = <®_usb_otg1_vbus>;
+ dr_mode = "host";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_id>;
+ disable-over-current;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_lpuart1: lpuart1grp {
+ fsl,pins = <IOMUXC_GPIO_AD_24_LPUART1_TXD 0xf1>,
+ <IOMUXC_GPIO_AD_25_LPUART1_RXD 0xf1>;
+ };
+
+ pinctrl_pwm0: pwm0grp {
+ fsl,pins = <IOMUXC_GPIO_AD_11_USB_OTG1_OC 0xf1>;
+ };
+
+ pinctrl_usbotg1_id: usbotg1idgrp {
+ fsl,pins = <IOMUXC_GPIO_AD_09_USBPHY1_OTG_ID 0xf1>;
+ };
+
+ pinctrl_usdhc0: usdhc0grp {
+ fsl,pins = <IOMUXC_GPIO_AD_32_USDHC1_CD_B 0x1B000>,
+ <IOMUXC_GPIO_AD_34_USDHC1_VSELECT 0xB069>,
+ <IOMUXC_GPIO_SD_B1_00_USDHC1_CMD 0x17061>,
+ <IOMUXC_GPIO_SD_B1_01_USDHC1_CLK 0x17061>,
+ <IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 0x17061>,
+ <IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 0x17061>,
+ <IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 0x17061>,
+ <IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 0x17061>;
+ };
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc0>;
+ pinctrl-1 = <&pinctrl_usdhc0>;
+ pinctrl-2 = <&pinctrl_usdhc0>;
+ pinctrl-3 = <&pinctrl_usdhc0>;
+ status = "okay";
+ broken-cd;
+};
diff --git a/arch/arm/boot/dts/imxrt1170.dtsi b/arch/arm/boot/dts/imxrt1170.dtsi
new file mode 100644
index 000000000000..64c130933ee8
--- /dev/null
+++ b/arch/arm/boot/dts/imxrt1170.dtsi
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube <[email protected]>
+ */
+
+#include "armv7-m.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/imxrt1170-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ size = <0x40000>;
+ no-map;
+ linux,dma-default;
+ };
+ };
+
+ clocks {
+ osc: osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ rcosc16M: rcosc16M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ };
+
+ osc32k: osc32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ osc3M: osc3M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <3000000>;
+ };
+ };
+
+ soc {
+ anatop: anatop@40c84000 {
+ compatible = "fsl,imxrt-anatop";
+ reg = <0x40c84000 0x4000>;
+ };
+
+ clks: clock-controller@40cc0000 {
+ compatible = "fsl,imxrt1170-ccm";
+ reg = <0x40cc0000 0x4000>;
+ clocks = <&osc>, <&rcosc16M>, <&osc32k>;
+ clock-names = "osc", "rcosc16M", "osc32k";
+ #clock-cells = <1>;
+ };
+
+ edma1: dma-controller@40070000 {
+ #dma-cells = <2>;
+ compatible = "fsl,imx7ulp-edma";
+ reg = <0x40070000 0x4000>,
+ <0x40074000 0x4000>;
+ dma-channels = <32>;
+ interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
+ <9>, <10>, <11>, <12>, <13>, <14>, <15>, <16>;
+ clock-names = "dma", "dmamux0";
+ clocks = <&clks IMXRT1170_CLK_BUS>,
+ <&clks IMXRT1170_CLK_M4>;
+ };
+
+ gpio1: gpio@4012c000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x4012c000 0x4000>;
+ interrupts = <100>, <101>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@40130000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40130000 0x4000>;
+ interrupts = <102>, <103>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@40134000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40134000 0x4000>;
+ interrupts = <104>, <105>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@40138000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40138000 0x4000>;
+ interrupts = <106>, <107>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio5: gpio@4013c000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x4013c000 0x4000>;
+ interrupts = <108>, <109>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio6: gpio@40140000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40140000 0x4000>;
+ interrupts = <61>, <62>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio7: gpio@40c5c000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c5c000 0x4000>;
+ interrupts = <99>, <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio8: gpio@40c60000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c60000 0x4000>;
+ interrupts = <99>, <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio9: gpio@40c64000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c64000 0x4000>;
+ interrupts = <99>, <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio10: gpio@40c68000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c68000 0x4000>;
+ interrupts = <99>, <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio11: gpio@40c6c000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c6c000 0x4000>;
+ interrupts = <99>, <99>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio12: gpio@40c70000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40c70000 0x4000>;
+ interrupts = <61>, <62>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio13: gpio@40ca0000 {
+ compatible = "fsl,imxrt1170-gpio", "fsl,imx35-gpio";
+ reg = <0x40ca0000 0x4000>;
+ interrupts = <93>, <93>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpt: timer@400ec000 {
+ compatible = "fsl,imxrt1170-gpt", "fsl,imx6dl-gpt";
+ reg = <0x400ec000 0x4000>;
+ interrupts = <119>;
+ clocks = <&osc3M>, <&osc3M>;
+ clock-names = "ipg", "per";
+ };
+
+ iomuxc: iomuxc@400e8000 {
+ compatible = "fsl,imxrt1170-iomuxc";
+ reg = <0x400e8000 0x4000>;
+ };
+
+ lpuart1: serial@4007c000 {
+ compatible = "fsl,imxrt1170-lpuart", "fsl,imxrt1050-lpuart";
+ reg = <0x4007c000 0x4000>;
+ interrupts = <20>;
+ clocks = <&clks IMXRT1170_CLK_LPUART1>;
+ clock-names = "ipg";
+ status = "disabled";
+ };
+
+ usdhc1: mmc@40418000 {
+ compatible = "fsl,imxrt1170-usdhc", "fsl,imxrt1050-usdhc";
+ reg = <0x40418000 0x10000>;
+ interrupts = <133>;
+ clocks = <&clks IMXRT1170_CLK_BUS>,
+ <&clks IMXRT1170_CLK_BUS>,
+ <&clks IMXRT1170_CLK_USDHC1>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ fsl,wp-controller;
+ no-1-8-v;
+ max-frequency = <4000000>;
+ fsl,tuning-start-tap = <20>;
+ fsl,tuning-step= <2>;
+ status = "disabled";
+ };
+
+ usbmisc1: usbmisc@40430200 {
+ compatible = "fsl,imx7ulp-usbmisc";
+ #index-cells = <1>;
+ reg = <0x40430200 0x200>;
+ };
+
+ usbotg1: usb@40430000 {
+ compatible = "fsl,imx7ulp-usb";
+ reg = <0x40430000 0x200>;
+ interrupts = <136>;
+ clocks = <&clks IMXRT1170_CLK_USB>;
+ phys = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc1 0>;
+ status = "disabled";
+ };
+
+ usbphy1: usb-phy@40434000 {
+ compatible = "fsl,imx7ulp-usbphy";
+ reg = <0x40434000 0x1000>;
+ interrupts = <90>;
+ clocks = <&clks IMXRT1170_CLK_USB>;
+ #phy-cells = <0>;
+ };
+
+ };
+};
--
2.35.1
Add i.MXRT1170 compatible string to Documentation.
Cc: Giulio Benetti <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- New commit to fix dtbs_check
---
Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
index 19621a2f8beb..b4d98a9c0952 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
@@ -34,6 +34,7 @@ properties:
- fsl,imx6ull-usdhc
- fsl,imx7d-usdhc
- fsl,imx7ulp-usdhc
+ - fsl,imx1050-usdhc
- nxp,s32g2-usdhc
- items:
- enum:
@@ -44,6 +45,11 @@ properties:
- fsl,imx8qm-usdhc
- fsl,imx8qxp-usdhc
- const: fsl,imx7d-usdhc
+ - const: fsl,imxrt1050-usdhc
+ - items:
+ - enum:
+ - fsl,imxrt1170-usdhc
+ - const: fsl,imxrt1050-usdhc
reg:
maxItems: 1
--
2.35.1
Add "fsl,imxrt1170" to imxrt_compat
Cc: Giulio Benetti <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- Nothing done
---
arch/arm/mach-imx/mach-imxrt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/mach-imxrt.c b/arch/arm/mach-imx/mach-imxrt.c
index 2063a3059c84..0070214feb42 100644
--- a/arch/arm/mach-imx/mach-imxrt.c
+++ b/arch/arm/mach-imx/mach-imxrt.c
@@ -10,6 +10,7 @@
static const char *const imxrt_compat[] __initconst = {
"fsl,imxrt1050",
+ "fsl,imxrt1170",
NULL
};
--
2.35.1
Add i.MXRT1170 pinctrl, clocks imxrt_defconfig.
Add support for CHIPIDEA usb host and usb gadget and other usb drives.
Cc: Giulio Benetti <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- Remove USB_CONFIGFS*
---
arch/arm/configs/imxrt_defconfig | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/configs/imxrt_defconfig b/arch/arm/configs/imxrt_defconfig
index 52dba3762996..b3a013686255 100644
--- a/arch/arm/configs/imxrt_defconfig
+++ b/arch/arm/configs/imxrt_defconfig
@@ -17,7 +17,23 @@ CONFIG_SERIAL_FSL_LPUART=y
CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
CONFIG_SERIAL_DEV_BUS=y
CONFIG_PINCTRL_IMXRT1050=y
+CONFIG_PINCTRL_IMXRT1170=y
CONFIG_GPIO_MXC=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_FSL=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_MASS_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
@@ -25,6 +41,7 @@ CONFIG_MMC_SDHCI_ESDHC_IMX=y
CONFIG_DMADEVICES=y
CONFIG_FSL_EDMA=y
CONFIG_CLK_IMXRT1050=y
+CONFIG_CLK_IMXRT1170=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
--
2.35.1
On Thu, 28 Apr 2022 17:48:30 -0400, Jesse Taube wrote:
> Add DT binding documentation for i.MXRT1170 clock driver.
>
> Cc: Giulio Benetti <[email protected]>
> Signed-off-by: Jesse Taube <[email protected]>
> ---
> V1 -> V2:
> - Change title to Clock Controller
> - Rename to add fsl
> ---
> .../bindings/clock/fsl,imxrt1170-clock.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/fsl,imxrt1170-clock.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/clock/fsl,imxrt1170-clock.yaml: $id: relative path/filename doesn't match actual path or filename
expected: http://devicetree.org/schemas/clock/fsl,imxrt1170-clock.yaml#
Documentation/devicetree/bindings/clock/fsl,imxrt1170-clock.example.dts:20:18: fatal error: dt-bindings/clock/imxrt1170-clock.h: No such file or directory
20 | #include <dt-bindings/clock/imxrt1170-clock.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/clock/fsl,imxrt1170-clock.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1401: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On 22-04-28 17:48:34, Jesse Taube wrote:
> Add clock driver support for i.MXRT1170.
>
> Cc: Giulio Benetti <[email protected]>
> Signed-off-by: Jesse Taube <[email protected]>
> ---
> V1 -> V2:
> - Add slab.h and clock-provider.h
> - Add spaces in `root_clocks`
> - Expand and sort macro
> - Move `clk_hw` structs to `clocks_probe`
> - Remove of_irq.h
> - Remove unused code/comments
> ---
> drivers/clk/imx/Kconfig | 7 +
> drivers/clk/imx/Makefile | 1 +
> drivers/clk/imx/clk-imxrt1170.c | 536 ++++++++++++++++++++++++++++++++
> 3 files changed, 544 insertions(+)
> create mode 100644 drivers/clk/imx/clk-imxrt1170.c
>
> diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
> index 45641b8bdc50..009adbe8059f 100644
> --- a/drivers/clk/imx/Kconfig
> +++ b/drivers/clk/imx/Kconfig
> @@ -112,3 +112,10 @@ config CLK_IMXRT1050
> select MXC_CLK
> help
> Build the driver for i.MXRT1050 CCM Clock Driver
> +
> +config CLK_IMXRT1170
> + tristate "IMXRT1170 CCM Clock Driver"
> + depends on SOC_IMXRT
> + select MXC_CLK
> + help
> + Build the driver for i.MXRT1170 CCM Clock Driver
> diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
> index 1e13c5cb37d9..0968d9ffcf6b 100644
> --- a/drivers/clk/imx/Makefile
> +++ b/drivers/clk/imx/Makefile
> @@ -47,4 +47,5 @@ obj-$(CONFIG_CLK_IMX6UL) += clk-imx6ul.o
> obj-$(CONFIG_CLK_IMX7D) += clk-imx7d.o
> obj-$(CONFIG_CLK_IMX7ULP) += clk-imx7ulp.o
> obj-$(CONFIG_CLK_IMXRT1050) += clk-imxrt1050.o
> +obj-$(CONFIG_CLK_IMXRT1170) += clk-imxrt1170.o
> obj-$(CONFIG_CLK_VF610) += clk-vf610.o
> diff --git a/drivers/clk/imx/clk-imxrt1170.c b/drivers/clk/imx/clk-imxrt1170.c
> new file mode 100644
> index 000000000000..bcae3b687be6
> --- /dev/null
> +++ b/drivers/clk/imx/clk-imxrt1170.c
> @@ -0,0 +1,536 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
> +/*
> + * Copyright (C) 2022
> + * Author(s):
> + * Jesse Taube <[email protected]>
> + */
> +#include <linux/clk.h>
> +#include <linux/of_address.h>
> +#include <linux/slab.h>
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/imxrt1170-clock.h>
> +
> +#include "clk.h"
> +
> +#define CLOCK_MUX_DEFAULT "rcosc48M_div2", "osc", "rcosc400M", "rcosc16M"
> +
> +#define LPCG_GATE(gate) (0x6000 + (gate * 0x20))
> +
> +enum root_clock_names {
> + m7,
> + m4,
> + bus,
> + bus_lpsr,
> + semc,
> + cssys,
> + cstrace,
> + m4_systick,
> + m7_systick,
> + adc1,
> + adc2,
> + acmp,
> + flexio1,
> + flexio2,
> + gpt1,
> + gpt2,
> + gpt3,
> + gpt4,
> + gpt5,
> + gpt6,
> + flexspi1,
> + flexspi2,
> + can1,
> + can2,
> + can3,
> + lpuart1,
> + lpuart2,
> + lpuart3,
> + lpuart4,
> + lpuart5,
> + lpuart6,
> + lpuart7,
> + lpuart8,
> + lpuart9,
> + lpuart10,
> + lpuart11,
> + lpuart12,
> + lpi2c1,
> + lpi2c2,
> + lpi2c3,
> + lpi2c4,
> + lpi2c5,
> + lpi2c6,
> + lpspi1,
> + lpspi2,
> + lpspi3,
> + lpspi4,
> + lpspi5,
> + lpspi6,
> + emv1,
> + emv2,
> + enet1,
> + enet2,
> + enet_qos,
> + enet_25m,
> + enet_timer1,
> + enet_timer2,
> + enet_timer3,
> + usdhc1,
> + usdhc2,
> + asrc,
> + mqs,
> + mic,
> + spdif,
> + sai1,
> + sai2,
> + sai3,
> + sai4,
> + gc355,
> + lcdif,
> + lcdifv2,
> + mipi_ref,
> + mipi_esc,
> + csi2,
> + csi2_esc,
> + csi2_ui,
> + csi,
> + cko1,
> + cko2,
> + end,
> +};
> +
> +static const char * const root_clocks[79][8] = {
> + { CLOCK_MUX_DEFAULT, "pll_arm", "pll1_sys", "pll3_sys", "pll_video" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_sys", "pll1_div5" },
> + { CLOCK_MUX_DEFAULT, "pll3_sys", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_sys", "pll1_div5" },
> + { CLOCK_MUX_DEFAULT, "pll1_div5", "pll2_sys", "pll2_pfd1", "pll3_pfd0" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
Please drop these entirely. This root clock array is used multiple
times thoughout. And so goes for the rest of them. Moreover, this is
hard to keep track of. Imagine what happens if someone comes around and
tries to fix a parent for one of the lpuarts.
Just do what the other i.MX clock drivers do. Add dedicated arrays that
are unique and that's it. There aren't that many.
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_pfd1", "pll2_sys" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_pfd0", "pll1_div5" },
> + { CLOCK_MUX_DEFAULT, "pll2_sys", "pll3_div2", "pll1_div5", "pll2_pfd0" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_sys", "pll1_div5", "pll_audio", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll_audio", "pll_video" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll_audio", "pll_video" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll3_pfd2", "pll3_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd0", "pll2_sys", "pll2_pfd2", "pll3_sys" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd0", "pll2_sys", "pll2_pfd2", "pll3_sys" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_pfd3", "pll1_div5" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_pfd3", "pll1_div5" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_pfd3", "pll1_div5" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_pfd3", "pll1_div5" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll2_pfd3", "pll1_div5" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll3_pfd2", "pll1_div5" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll3_pfd2", "pll1_div5" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_div2", "pll1_div5", "pll2_sys", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" },
> + { CLOCK_MUX_DEFAULT, "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" },
> + { CLOCK_MUX_DEFAULT, "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" },
> + { CLOCK_MUX_DEFAULT, "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" },
> + { CLOCK_MUX_DEFAULT, "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" },
> + { CLOCK_MUX_DEFAULT, "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" },
> + { CLOCK_MUX_DEFAULT, "pll1_div2", "pll_audio", "pll1_div5", "pll2_pfd1" },
> + { CLOCK_MUX_DEFAULT, "pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm" },
> + { CLOCK_MUX_DEFAULT, "pll2_pfd2", "pll2_pfd0", "pll1_div5", "pll_arm" },
> + { CLOCK_MUX_DEFAULT, "pll1_div5", "pll3_div2", "pll_audio", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll1_div5", "pll3_div2", "pll_audio", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll_audio", "pll1_div5" },
> + { CLOCK_MUX_DEFAULT, "pll_audio", "pll3_sys", "pll3_pfd2", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll_audio", "pll3_pfd2", "pll1_div5", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll_audio", "pll3_pfd2", "pll1_div5", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll_audio", "pll3_pfd2", "pll1_div5", "pll2_pfd3" },
> + { CLOCK_MUX_DEFAULT, "pll3_pfd3", "pll3_sys", "pll_audio", "pll1_div5" },
> + { CLOCK_MUX_DEFAULT, "pll2_sys", "pll2_pfd1", "pll3_sys", "pll_video" },
> + { CLOCK_MUX_DEFAULT, "pll2_sys", "pll2_pfd2", "pll3_pfd0", "pll_video" },
> + { CLOCK_MUX_DEFAULT, "pll2_sys", "pll2_pfd2", "pll3_pfd0", "pll_video" },
> + { CLOCK_MUX_DEFAULT, "pll2_sys", "pll2_pfd0", "pll3_pfd0", "pll_video" },
> + { CLOCK_MUX_DEFAULT, "pll2_sys", "pll2_pfd0", "pll3_pfd0", "pll_video" },
> + { CLOCK_MUX_DEFAULT, "pll2_pfd2", "pll3_sys", "pll2_pfd0", "pll_video" },
> + { CLOCK_MUX_DEFAULT, "pll2_pfd2", "pll3_sys", "pll2_pfd0", "pll_video" },
> + { CLOCK_MUX_DEFAULT, "pll2_pfd2", "pll3_sys", "pll2_pfd0", "pll_video" },
> + { CLOCK_MUX_DEFAULT, "pll2_pfd2", "pll3_sys", "pll3_pfd1", "pll_video" },
> + { CLOCK_MUX_DEFAULT, "pll2_pfd2", "pll2_sys", "pll3_pfd1", "pll1_div5" },
> + { CLOCK_MUX_DEFAULT, "pll2_pfd3", "rcosc48M", "pll3_pfd1", "pll_audio"}
> +};
> +
> +static const char * const pll_arm_mux[] = {"pll_arm_pre", "osc"};
> +static const char * const pll3_mux[] = {"pll3_pre", "osc"};
> +static const char * const pll2_mux[] = {"pll2_pre", "osc"};
> +
> +static const struct clk_div_table post_div_table[] = {
> + { .val = 3, .div = 1, },
> + { .val = 2, .div = 8, },
> + { .val = 1, .div = 4, },
> + { .val = 0, .div = 2, },
> + { }
> +};
> +
> +static int imxrt1170_clocks_probe(struct platform_device *pdev)
> +{
> + void __iomem *ccm_base;
> + void __iomem *pll_base;
> + struct clk_hw **hws;
> + struct clk_hw_onecell_data *clk_hw_data;
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct device_node *anp;
> + int ret;
> +
> + clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
> + IMXRT1170_CLK_END), GFP_KERNEL);
> + if (WARN_ON(!clk_hw_data))
> + return -ENOMEM;
> +
> + clk_hw_data->num = IMXRT1170_CLK_END;
> + hws = clk_hw_data->hws;
> +
> + hws[IMXRT1170_CLK_OSC] = imx_obtain_fixed_clk_hw(np, "osc");
> + hws[IMXRT1170_CLK_RCOSC_16M] = imx_obtain_fixed_clk_hw(np, "rcosc16M");
> + hws[IMXRT1170_CLK_OSC_32K] = imx_obtain_fixed_clk_hw(np, "osc32k");
> +
> + hws[IMXRT1170_CLK_RCOSC_48M] = imx_clk_hw_fixed_factor("rcosc48M", "rcosc16M", 3, 1);
> + hws[IMXRT1170_CLK_RCOSC_400M] = imx_clk_hw_fixed_factor("rcosc400M", "rcosc16M", 25, 1);
> + hws[IMXRT1170_CLK_RCOSC_48M_DIV2] = imx_clk_hw_fixed_factor("rcosc48M_div2", "rcosc48M", 1, 2);
> +
> + anp = of_find_compatible_node(NULL, NULL, "fsl,imxrt-anatop");
> + pll_base = of_iomap(anp, 0);
> + of_node_put(anp);
> + if (WARN_ON(!pll_base))
> + return -ENOMEM;
> +
> + /* Anatop clocks */
> + hws[IMXRT1170_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0UL);
> +
> + hws[IMXRT1170_CLK_PLL_ARM_PRE] = imx_clk_hw_pllv3(IMX_PLLV3_SYSV2, "pll_arm_pre", "osc", pll_base + 0x200, 0xff);
> + imx_clk_hw_pll3_powerbit(hws[IMXRT1170_CLK_PLL_ARM_PRE], 13);
> + hws[IMXRT1170_CLK_PLL_ARM_BYPASS] = imx_clk_hw_mux("pll_arm_bypass",
> + pll_base + 0x200, 17, 1, pll_arm_mux, 2);
> + hws[IMXRT1170_CLK_PLL_ARM_DIV] = clk_hw_register_divider_table(NULL, "pll_arm_div",
> + "pll_arm_bypass", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
> + pll_base + 0x200, 15, 2, 0, post_div_table, &imx_ccm_lock);
> + hws[IMXRT1170_CLK_PLL_ARM] = imx_clk_hw_gate("pll_arm", "pll_arm_div", pll_base + 0x200, 14);
> +
> + hws[IMXRT1170_CLK_PLL3_PRE] = imx_clk_hw_pllv3(IMX_PLLV3_GENERICV2, "pll3_pre", "osc", pll_base + 0x210, 0x1);
> + imx_clk_hw_pll3_powerbit(hws[IMXRT1170_CLK_PLL3_PRE], 21);
> + hws[IMXRT1170_CLK_PLL3_BYPASS] = imx_clk_hw_mux("pll3_bypass",
> + pll_base + 0x210, 16, 1, pll3_mux, 2);
> + hws[IMXRT1170_CLK_PLL3] = imx_clk_hw_gate("pll3_sys", "pll3_bypass", pll_base + 0x210, 13);
> +
> + hws[IMXRT1170_CLK_PLL2_PRE] = imx_clk_hw_pllv3(IMX_PLLV3_GENERICV2, "pll2_pre", "osc", pll_base + 0x240, 0x1);
> + imx_clk_hw_pll3_powerbit(hws[IMXRT1170_CLK_PLL2_PRE], 23);
> + hws[IMXRT1170_CLK_PLL2_BYPASS] = imx_clk_hw_mux("pll2_bypass",
> + pll_base + 0x240, 16, 1, pll2_mux, 2);
> + hws[IMXRT1170_CLK_PLL2] = imx_clk_hw_gate("pll2_sys", "pll2_bypass", pll_base + 0x240, 13);
> +
> + hws[IMXRT1170_CLK_PLL3_PFD0] = imx_clk_hw_pfd("pll3_pfd0", "pll3_sys", pll_base + 0x230, 0);
> + hws[IMXRT1170_CLK_PLL3_PFD1] = imx_clk_hw_pfd("pll3_pfd1", "pll3_sys", pll_base + 0x230, 1);
> + hws[IMXRT1170_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2", "pll3_sys", pll_base + 0x230, 2);
> + hws[IMXRT1170_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3", "pll3_sys", pll_base + 0x230, 3);
> + hws[IMXRT1170_CLK_PLL3_DIV2_GATE] = imx_clk_hw_fixed_factor("pll3_div2_gate", "pll3_sys", 1, 2);
> + hws[IMXRT1170_CLK_PLL3_DIV2] = imx_clk_hw_gate("pll3_div2", "pll3_sys", pll_base + 0x210, 3);
> +
> + hws[IMXRT1170_CLK_PLL2_PFD0] = imx_clk_hw_pfd("pll2_pfd0", "pll2_sys", pll_base + 0x270, 0);
> + hws[IMXRT1170_CLK_PLL2_PFD1] = imx_clk_hw_pfd("pll2_pfd1", "pll2_sys", pll_base + 0x270, 1);
> + hws[IMXRT1170_CLK_PLL2_PFD2] = imx_clk_hw_pfd("pll2_pfd2", "pll2_sys", pll_base + 0x270, 2);
> + hws[IMXRT1170_CLK_PLL2_PFD3] = imx_clk_hw_pfd("pll2_pfd3", "pll2_sys", pll_base + 0x270, 3);
> +
> + /* CCM clocks */
> + ccm_base = devm_platform_ioremap_resource(pdev, 0);
> + if (WARN_ON(IS_ERR(ccm_base)))
> + return PTR_ERR(ccm_base);
> +
> + hws[IMXRT1170_CLK_M7_SEL] = imx_clk_hw_mux("m7_sel", ccm_base + (m7 * 0x80), 8, 3, root_clocks[m7], 8);
> + hws[IMXRT1170_CLK_M4_SEL] = imx_clk_hw_mux("m4_sel", ccm_base + (m4 * 0x80), 8, 3, root_clocks[m4], 8);
> + hws[IMXRT1170_CLK_BUS_SEL] = imx_clk_hw_mux("bus_sel", ccm_base + (bus * 0x80), 8, 3, root_clocks[bus], 8);
> + hws[IMXRT1170_CLK_BUS_LPSR_SEL] = imx_clk_hw_mux("bus_lpsr_sel", ccm_base + (bus_lpsr * 0x80), 8, 3, root_clocks[bus_lpsr], 8);
> + hws[IMXRT1170_CLK_SEMC_SEL] = imx_clk_hw_mux("semc_sel", ccm_base + (semc * 0x80), 8, 3, root_clocks[semc], 8);
> + hws[IMXRT1170_CLK_CSSYS_SEL] = imx_clk_hw_mux("cssys_sel", ccm_base + (cssys * 0x80), 8, 3, root_clocks[cssys], 8);
> + hws[IMXRT1170_CLK_CSTRACE_SEL] = imx_clk_hw_mux("cstrace_sel", ccm_base + (cstrace * 0x80), 8, 3, root_clocks[cstrace], 8);
> + hws[IMXRT1170_CLK_M4_SYSTICK_SEL] = imx_clk_hw_mux("m4_systick_sel", ccm_base + (m4_systick * 0x80), 8, 3, root_clocks[m4_systick], 8);
> + hws[IMXRT1170_CLK_M7_SYSTICK_SEL] = imx_clk_hw_mux("m7_systick_sel", ccm_base + (m7_systick * 0x80), 8, 3, root_clocks[m7_systick], 8);
> + hws[IMXRT1170_CLK_ADC1_SEL] = imx_clk_hw_mux("adc1_sel", ccm_base + (adc1 * 0x80), 8, 3, root_clocks[adc1], 8);
> + hws[IMXRT1170_CLK_ADC2_SEL] = imx_clk_hw_mux("adc2_sel", ccm_base + (adc2 * 0x80), 8, 3, root_clocks[adc2], 8);
> + hws[IMXRT1170_CLK_ACMP_SEL] = imx_clk_hw_mux("acmp_sel", ccm_base + (acmp * 0x80), 8, 3, root_clocks[acmp], 8);
> + hws[IMXRT1170_CLK_FLEXIO1_SEL] = imx_clk_hw_mux("flexio1_sel", ccm_base + (flexio1 * 0x80), 8, 3, root_clocks[flexio1], 8);
> + hws[IMXRT1170_CLK_FLEXIO2_SEL] = imx_clk_hw_mux("flexio2_sel", ccm_base + (flexio2 * 0x80), 8, 3, root_clocks[flexio2], 8);
> + hws[IMXRT1170_CLK_GPT1_SEL] = imx_clk_hw_mux("gpt1_sel", ccm_base + (gpt1 * 0x80), 8, 3, root_clocks[gpt1], 8);
> + hws[IMXRT1170_CLK_GPT2_SEL] = imx_clk_hw_mux("gpt2_sel", ccm_base + (gpt2 * 0x80), 8, 3, root_clocks[gpt2], 8);
> + hws[IMXRT1170_CLK_GPT3_SEL] = imx_clk_hw_mux("gpt3_sel", ccm_base + (gpt3 * 0x80), 8, 3, root_clocks[gpt3], 8);
> + hws[IMXRT1170_CLK_GPT4_SEL] = imx_clk_hw_mux("gpt4_sel", ccm_base + (gpt4 * 0x80), 8, 3, root_clocks[gpt4], 8);
> + hws[IMXRT1170_CLK_GPT5_SEL] = imx_clk_hw_mux("gpt5_sel", ccm_base + (gpt5 * 0x80), 8, 3, root_clocks[gpt5], 8);
> + hws[IMXRT1170_CLK_GPT6_SEL] = imx_clk_hw_mux("gpt6_sel", ccm_base + (gpt6 * 0x80), 8, 3, root_clocks[gpt6], 8);
> + hws[IMXRT1170_CLK_FLEXSPI1_SEL] = imx_clk_hw_mux("flexspi1_sel", ccm_base + (flexspi1 * 0x80), 8, 3, root_clocks[flexspi1], 8);
> + hws[IMXRT1170_CLK_FLEXSPI2_SEL] = imx_clk_hw_mux("flexspi2_sel", ccm_base + (flexspi2 * 0x80), 8, 3, root_clocks[flexspi2], 8);
> + hws[IMXRT1170_CLK_CAN1_SEL] = imx_clk_hw_mux("can1_sel", ccm_base + (can1 * 0x80), 8, 3, root_clocks[can1], 8);
> + hws[IMXRT1170_CLK_CAN2_SEL] = imx_clk_hw_mux("can2_sel", ccm_base + (can2 * 0x80), 8, 3, root_clocks[can2], 8);
> + hws[IMXRT1170_CLK_CAN3_SEL] = imx_clk_hw_mux("can3_sel", ccm_base + (can3 * 0x80), 8, 3, root_clocks[can3], 8);
> + hws[IMXRT1170_CLK_LPUART1_SEL] = imx_clk_hw_mux("lpuart1_sel", ccm_base + (lpuart1 * 0x80), 8, 3, root_clocks[lpuart1], 8);
> + hws[IMXRT1170_CLK_LPUART2_SEL] = imx_clk_hw_mux("lpuart2_sel", ccm_base + (lpuart2 * 0x80), 8, 3, root_clocks[lpuart2], 8);
> + hws[IMXRT1170_CLK_LPUART3_SEL] = imx_clk_hw_mux("lpuart3_sel", ccm_base + (lpuart3 * 0x80), 8, 3, root_clocks[lpuart3], 8);
> + hws[IMXRT1170_CLK_LPUART4_SEL] = imx_clk_hw_mux("lpuart4_sel", ccm_base + (lpuart4 * 0x80), 8, 3, root_clocks[lpuart4], 8);
> + hws[IMXRT1170_CLK_LPUART5_SEL] = imx_clk_hw_mux("lpuart5_sel", ccm_base + (lpuart5 * 0x80), 8, 3, root_clocks[lpuart5], 8);
> + hws[IMXRT1170_CLK_LPUART6_SEL] = imx_clk_hw_mux("lpuart6_sel", ccm_base + (lpuart6 * 0x80), 8, 3, root_clocks[lpuart6], 8);
> + hws[IMXRT1170_CLK_LPUART7_SEL] = imx_clk_hw_mux("lpuart7_sel", ccm_base + (lpuart7 * 0x80), 8, 3, root_clocks[lpuart7], 8);
> + hws[IMXRT1170_CLK_LPUART8_SEL] = imx_clk_hw_mux("lpuart8_sel", ccm_base + (lpuart8 * 0x80), 8, 3, root_clocks[lpuart8], 8);
> + hws[IMXRT1170_CLK_LPUART9_SEL] = imx_clk_hw_mux("lpuart9_sel", ccm_base + (lpuart9 * 0x80), 8, 3, root_clocks[lpuart9], 8);
> + hws[IMXRT1170_CLK_LPUART10_SEL] = imx_clk_hw_mux("lpuart10_sel", ccm_base + (lpuart10 * 0x80), 8, 3, root_clocks[lpuart10], 8);
> + hws[IMXRT1170_CLK_LPUART11_SEL] = imx_clk_hw_mux("lpuart11_sel", ccm_base + (lpuart11 * 0x80), 8, 3, root_clocks[lpuart11], 8);
> + hws[IMXRT1170_CLK_LPUART12_SEL] = imx_clk_hw_mux("lpuart12_sel", ccm_base + (lpuart12 * 0x80), 8, 3, root_clocks[lpuart12], 8);
> + hws[IMXRT1170_CLK_LPI2C1_SEL] = imx_clk_hw_mux("lpi2c1_sel", ccm_base + (lpi2c1 * 0x80), 8, 3, root_clocks[lpi2c1], 8);
> + hws[IMXRT1170_CLK_LPI2C2_SEL] = imx_clk_hw_mux("lpi2c2_sel", ccm_base + (lpi2c2 * 0x80), 8, 3, root_clocks[lpi2c2], 8);
> + hws[IMXRT1170_CLK_LPI2C3_SEL] = imx_clk_hw_mux("lpi2c3_sel", ccm_base + (lpi2c3 * 0x80), 8, 3, root_clocks[lpi2c3], 8);
> + hws[IMXRT1170_CLK_LPI2C4_SEL] = imx_clk_hw_mux("lpi2c4_sel", ccm_base + (lpi2c4 * 0x80), 8, 3, root_clocks[lpi2c4], 8);
> + hws[IMXRT1170_CLK_LPI2C5_SEL] = imx_clk_hw_mux("lpi2c5_sel", ccm_base + (lpi2c5 * 0x80), 8, 3, root_clocks[lpi2c5], 8);
> + hws[IMXRT1170_CLK_LPI2C6_SEL] = imx_clk_hw_mux("lpi2c6_sel", ccm_base + (lpi2c6 * 0x80), 8, 3, root_clocks[lpi2c6], 8);
> + hws[IMXRT1170_CLK_LPSPI1_SEL] = imx_clk_hw_mux("lpspi1_sel", ccm_base + (lpspi1 * 0x80), 8, 3, root_clocks[lpspi1], 8);
> + hws[IMXRT1170_CLK_LPSPI2_SEL] = imx_clk_hw_mux("lpspi2_sel", ccm_base + (lpspi2 * 0x80), 8, 3, root_clocks[lpspi2], 8);
> + hws[IMXRT1170_CLK_LPSPI3_SEL] = imx_clk_hw_mux("lpspi3_sel", ccm_base + (lpspi3 * 0x80), 8, 3, root_clocks[lpspi3], 8);
> + hws[IMXRT1170_CLK_LPSPI4_SEL] = imx_clk_hw_mux("lpspi4_sel", ccm_base + (lpspi4 * 0x80), 8, 3, root_clocks[lpspi4], 8);
> + hws[IMXRT1170_CLK_LPSPI5_SEL] = imx_clk_hw_mux("lpspi5_sel", ccm_base + (lpspi5 * 0x80), 8, 3, root_clocks[lpspi5], 8);
> + hws[IMXRT1170_CLK_LPSPI6_SEL] = imx_clk_hw_mux("lpspi6_sel", ccm_base + (lpspi6 * 0x80), 8, 3, root_clocks[lpspi6], 8);
> + hws[IMXRT1170_CLK_EMV1_SEL] = imx_clk_hw_mux("emv1_sel", ccm_base + (emv1 * 0x80), 8, 3, root_clocks[emv1], 8);
> + hws[IMXRT1170_CLK_EMV2_SEL] = imx_clk_hw_mux("emv2_sel", ccm_base + (emv2 * 0x80), 8, 3, root_clocks[emv2], 8);
> + hws[IMXRT1170_CLK_ENET1_SEL] = imx_clk_hw_mux("enet1_sel", ccm_base + (enet1 * 0x80), 8, 3, root_clocks[enet1], 8);
> + hws[IMXRT1170_CLK_ENET2_SEL] = imx_clk_hw_mux("enet2_sel", ccm_base + (enet2 * 0x80), 8, 3, root_clocks[enet2], 8);
> + hws[IMXRT1170_CLK_ENET_QOS_SEL] = imx_clk_hw_mux("enet_qos_sel", ccm_base + (enet_qos * 0x80), 8, 3, root_clocks[enet_qos], 8);
> + hws[IMXRT1170_CLK_ENET_25M_SEL] = imx_clk_hw_mux("enet_25m_sel", ccm_base + (enet_25m * 0x80), 8, 3, root_clocks[enet_25m], 8);
> + hws[IMXRT1170_CLK_ENET_TIMER1_SEL] = imx_clk_hw_mux("enet_timer1_sel", ccm_base + (enet_timer1 * 0x80), 8, 3, root_clocks[enet_timer1], 8);
> + hws[IMXRT1170_CLK_ENET_TIMER2_SEL] = imx_clk_hw_mux("enet_timer2_sel", ccm_base + (enet_timer2 * 0x80), 8, 3, root_clocks[enet_timer2], 8);
> + hws[IMXRT1170_CLK_ENET_TIMER3_SEL] = imx_clk_hw_mux("enet_timer3_sel", ccm_base + (enet_timer3 * 0x80), 8, 3, root_clocks[enet_timer3], 8);
> + hws[IMXRT1170_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", ccm_base + (usdhc1 * 0x80), 8, 3, root_clocks[usdhc1], 8);
> + hws[IMXRT1170_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", ccm_base + (usdhc2 * 0x80), 8, 3, root_clocks[usdhc2], 8);
> + hws[IMXRT1170_CLK_ASRC_SEL] = imx_clk_hw_mux("asrc_sel", ccm_base + (asrc * 0x80), 8, 3, root_clocks[asrc], 8);
> + hws[IMXRT1170_CLK_MQS_SEL] = imx_clk_hw_mux("mqs_sel", ccm_base + (mqs * 0x80), 8, 3, root_clocks[mqs], 8);
> + hws[IMXRT1170_CLK_MIC_SEL] = imx_clk_hw_mux("mic_sel", ccm_base + (mic * 0x80), 8, 3, root_clocks[mic], 8);
> + hws[IMXRT1170_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel", ccm_base + (spdif * 0x80), 8, 3, root_clocks[spdif], 8);
> + hws[IMXRT1170_CLK_SAI1_SEL] = imx_clk_hw_mux("sai1_sel", ccm_base + (sai1 * 0x80), 8, 3, root_clocks[sai1], 8);
> + hws[IMXRT1170_CLK_SAI2_SEL] = imx_clk_hw_mux("sai2_sel", ccm_base + (sai2 * 0x80), 8, 3, root_clocks[sai2], 8);
> + hws[IMXRT1170_CLK_SAI3_SEL] = imx_clk_hw_mux("sai3_sel", ccm_base + (sai3 * 0x80), 8, 3, root_clocks[sai3], 8);
> + hws[IMXRT1170_CLK_SAI4_SEL] = imx_clk_hw_mux("sai4_sel", ccm_base + (sai4 * 0x80), 8, 3, root_clocks[sai4], 8);
> + hws[IMXRT1170_CLK_GC355_SEL] = imx_clk_hw_mux("gc355_sel", ccm_base + (gc355 * 0x80), 8, 3, root_clocks[gc355], 8);
> + hws[IMXRT1170_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel", ccm_base + (lcdif * 0x80), 8, 3, root_clocks[lcdif], 8);
> + hws[IMXRT1170_CLK_LCDIFV2_SEL] = imx_clk_hw_mux("lcdifv2_sel", ccm_base + (lcdifv2 * 0x80), 8, 3, root_clocks[lcdifv2], 8);
> + hws[IMXRT1170_CLK_MIPI_REF_SEL] = imx_clk_hw_mux("mipi_ref_sel", ccm_base + (mipi_ref * 0x80), 8, 3, root_clocks[mipi_ref], 8);
> + hws[IMXRT1170_CLK_MIPI_ESC_SEL] = imx_clk_hw_mux("mipi_esc_sel", ccm_base + (mipi_esc * 0x80), 8, 3, root_clocks[mipi_esc], 8);
> + hws[IMXRT1170_CLK_CSI2_SEL] = imx_clk_hw_mux("csi2_sel", ccm_base + (csi2 * 0x80), 8, 3, root_clocks[csi2], 8);
> + hws[IMXRT1170_CLK_CSI2_ESC_SEL] = imx_clk_hw_mux("csi2_esc_sel", ccm_base + (csi2_esc * 0x80), 8, 3, root_clocks[csi2_esc], 8);
> + hws[IMXRT1170_CLK_CSI2_UI_SEL] = imx_clk_hw_mux("csi2_ui_sel", ccm_base + (csi2_ui * 0x80), 8, 3, root_clocks[csi2_ui], 8);
> + hws[IMXRT1170_CLK_CSI_SEL] = imx_clk_hw_mux("csi_sel", ccm_base + (csi * 0x80), 8, 3, root_clocks[csi], 8);
> + hws[IMXRT1170_CLK_CKO1_SEL] = imx_clk_hw_mux("cko1_sel", ccm_base + (cko1 * 0x80), 8, 3, root_clocks[cko1], 8);
> + hws[IMXRT1170_CLK_CKO2_SEL] = imx_clk_hw_mux("cko2_sel", ccm_base + (cko2 * 0x80), 8, 3, root_clocks[cko2], 8);
> +
> + hws[IMXRT1170_CLK_M7_GATE] = imx_clk_hw_gate_dis_flags("m7_gate", "m7_sel", ccm_base + (m7 * 0x80), 24, CLK_IS_CRITICAL);
> + hws[IMXRT1170_CLK_M4_GATE] = imx_clk_hw_gate_dis_flags("m4_gate", "m4_sel", ccm_base + (m4 * 0x80), 24, CLK_IS_CRITICAL);
> + hws[IMXRT1170_CLK_BUS_GATE] = imx_clk_hw_gate_dis_flags("bus_gate", "bus_sel", ccm_base + (bus * 0x80), 24, CLK_IS_CRITICAL);
> + hws[IMXRT1170_CLK_BUS_LPSR_GATE] = imx_clk_hw_gate_dis_flags("bus_lpsr_gate", "bus_lpsr_sel", ccm_base + (bus_lpsr * 0x80), 24, CLK_IS_CRITICAL);
> + hws[IMXRT1170_CLK_SEMC_GATE] = imx_clk_hw_gate_dis_flags("semc_gate", "semc_sel", ccm_base + (semc * 0x80), 24, CLK_IS_CRITICAL);
> + hws[IMXRT1170_CLK_CSSYS_GATE] = imx_clk_hw_gate_dis_flags("cssys_gate", "cssys_sel", ccm_base + (cssys * 0x80), 24, CLK_IS_CRITICAL);
> + hws[IMXRT1170_CLK_CSTRACE_GATE] = imx_clk_hw_gate_dis_flags("cstrace_gate", "cstrace_sel", ccm_base + (cstrace * 0x80), 24, CLK_IS_CRITICAL);
> + hws[IMXRT1170_CLK_M4_SYSTICK_GATE] = imx_clk_hw_gate_dis_flags("m4_systick_gate", "m4_systick_sel", ccm_base + (m4_systick * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_M7_SYSTICK_GATE] = imx_clk_hw_gate_dis_flags("m7_systick_gate", "m7_systick_sel", ccm_base + (m7_systick * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_ADC1_GATE] = imx_clk_hw_gate_dis_flags("adc1_gate", "adc1_sel", ccm_base + (adc1 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_ADC2_GATE] = imx_clk_hw_gate_dis_flags("adc2_gate", "adc2_sel", ccm_base + (adc2 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_ACMP_GATE] = imx_clk_hw_gate_dis_flags("acmp_gate", "acmp_sel", ccm_base + (acmp * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_FLEXIO1_GATE] = imx_clk_hw_gate_dis_flags("flexio1_gate", "flexio1_sel", ccm_base + (flexio1 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_FLEXIO2_GATE] = imx_clk_hw_gate_dis_flags("flexio2_gate", "flexio2_sel", ccm_base + (flexio2 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_GPT1_GATE] = imx_clk_hw_gate_dis_flags("gpt1_gate", "gpt1_sel", ccm_base + (gpt1 * 0x80), 24, CLK_IS_CRITICAL);
> + hws[IMXRT1170_CLK_GPT2_GATE] = imx_clk_hw_gate_dis_flags("gpt2_gate", "gpt2_sel", ccm_base + (gpt2 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_GPT3_GATE] = imx_clk_hw_gate_dis_flags("gpt3_gate", "gpt3_sel", ccm_base + (gpt3 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_GPT4_GATE] = imx_clk_hw_gate_dis_flags("gpt4_gate", "gpt4_sel", ccm_base + (gpt4 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_GPT5_GATE] = imx_clk_hw_gate_dis_flags("gpt5_gate", "gpt5_sel", ccm_base + (gpt5 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_GPT6_GATE] = imx_clk_hw_gate_dis_flags("gpt6_gate", "gpt6_sel", ccm_base + (gpt6 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_FLEXSPI1_GATE] = imx_clk_hw_gate_dis_flags("flexspi1_gate", "flexspi1_sel", ccm_base + (flexspi1 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_FLEXSPI2_GATE] = imx_clk_hw_gate_dis_flags("flexspi2_gate", "flexspi2_sel", ccm_base + (flexspi2 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_CAN1_GATE] = imx_clk_hw_gate_dis_flags("can1_gate", "can1_sel", ccm_base + (can1 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_CAN2_GATE] = imx_clk_hw_gate_dis_flags("can2_gate", "can2_sel", ccm_base + (can2 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_CAN3_GATE] = imx_clk_hw_gate_dis_flags("can3_gate", "can3_sel", ccm_base + (can3 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPUART1_GATE] = imx_clk_hw_gate_dis_flags("lpuart1_gate", "lpuart1_sel", ccm_base + (lpuart1 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPUART2_GATE] = imx_clk_hw_gate_dis_flags("lpuart2_gate", "lpuart2_sel", ccm_base + (lpuart2 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPUART3_GATE] = imx_clk_hw_gate_dis_flags("lpuart3_gate", "lpuart3_sel", ccm_base + (lpuart3 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPUART4_GATE] = imx_clk_hw_gate_dis_flags("lpuart4_gate", "lpuart4_sel", ccm_base + (lpuart4 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPUART5_GATE] = imx_clk_hw_gate_dis_flags("lpuart5_gate", "lpuart5_sel", ccm_base + (lpuart5 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPUART6_GATE] = imx_clk_hw_gate_dis_flags("lpuart6_gate", "lpuart6_sel", ccm_base + (lpuart6 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPUART7_GATE] = imx_clk_hw_gate_dis_flags("lpuart7_gate", "lpuart7_sel", ccm_base + (lpuart7 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPUART8_GATE] = imx_clk_hw_gate_dis_flags("lpuart8_gate", "lpuart8_sel", ccm_base + (lpuart8 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPUART9_GATE] = imx_clk_hw_gate_dis_flags("lpuart9_gate", "lpuart9_sel", ccm_base + (lpuart9 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPUART10_GATE] = imx_clk_hw_gate_dis_flags("lpuart10_gate", "lpuart10_sel", ccm_base + (lpuart10 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPUART11_GATE] = imx_clk_hw_gate_dis_flags("lpuart11_gate", "lpuart11_sel", ccm_base + (lpuart11 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPUART12_GATE] = imx_clk_hw_gate_dis_flags("lpuart12_gate", "lpuart12_sel", ccm_base + (lpuart12 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPI2C1_GATE] = imx_clk_hw_gate_dis_flags("lpi2c1_gate", "lpi2c1_sel", ccm_base + (lpi2c1 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPI2C2_GATE] = imx_clk_hw_gate_dis_flags("lpi2c2_gate", "lpi2c2_sel", ccm_base + (lpi2c2 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPI2C3_GATE] = imx_clk_hw_gate_dis_flags("lpi2c3_gate", "lpi2c3_sel", ccm_base + (lpi2c3 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPI2C4_GATE] = imx_clk_hw_gate_dis_flags("lpi2c4_gate", "lpi2c4_sel", ccm_base + (lpi2c4 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPI2C5_GATE] = imx_clk_hw_gate_dis_flags("lpi2c5_gate", "lpi2c5_sel", ccm_base + (lpi2c5 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPI2C6_GATE] = imx_clk_hw_gate_dis_flags("lpi2c6_gate", "lpi2c6_sel", ccm_base + (lpi2c6 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPSPI1_GATE] = imx_clk_hw_gate_dis_flags("lpspi1_gate", "lpspi1_sel", ccm_base + (lpspi1 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPSPI2_GATE] = imx_clk_hw_gate_dis_flags("lpspi2_gate", "lpspi2_sel", ccm_base + (lpspi2 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPSPI3_GATE] = imx_clk_hw_gate_dis_flags("lpspi3_gate", "lpspi3_sel", ccm_base + (lpspi3 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPSPI4_GATE] = imx_clk_hw_gate_dis_flags("lpspi4_gate", "lpspi4_sel", ccm_base + (lpspi4 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPSPI5_GATE] = imx_clk_hw_gate_dis_flags("lpspi5_gate", "lpspi5_sel", ccm_base + (lpspi5 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LPSPI6_GATE] = imx_clk_hw_gate_dis_flags("lpspi6_gate", "lpspi6_sel", ccm_base + (lpspi6 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_EMV1_GATE] = imx_clk_hw_gate_dis_flags("emv1_gate", "emv1_sel", ccm_base + (emv1 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_EMV2_GATE] = imx_clk_hw_gate_dis_flags("emv2_gate", "emv2_sel", ccm_base + (emv2 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_ENET1_GATE] = imx_clk_hw_gate_dis_flags("enet1_gate", "enet1_sel", ccm_base + (enet1 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_ENET2_GATE] = imx_clk_hw_gate_dis_flags("enet2_gate", "enet2_sel", ccm_base + (enet2 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_ENET_QOS_GATE] = imx_clk_hw_gate_dis_flags("enet_qos_gate", "enet_qos_sel", ccm_base + (enet_qos * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_ENET_25M_GATE] = imx_clk_hw_gate_dis_flags("enet_25m_gate", "enet_25m_sel", ccm_base + (enet_25m * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_ENET_TIMER1_GATE] = imx_clk_hw_gate_dis_flags("enet_timer1_gate", "enet_timer1_sel", ccm_base + (enet_timer1 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_ENET_TIMER2_GATE] = imx_clk_hw_gate_dis_flags("enet_timer2_gate", "enet_timer2_sel", ccm_base + (enet_timer2 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_ENET_TIMER3_GATE] = imx_clk_hw_gate_dis_flags("enet_timer3_gate", "enet_timer3_sel", ccm_base + (enet_timer3 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_USDHC1_GATE] = imx_clk_hw_gate_dis_flags("usdhc1_gate", "usdhc1_sel", ccm_base + (usdhc1 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_USDHC2_GATE] = imx_clk_hw_gate_dis_flags("usdhc2_gate", "usdhc2_sel", ccm_base + (usdhc2 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_ASRC_GATE] = imx_clk_hw_gate_dis_flags("asrc_gate", "asrc_sel", ccm_base + (asrc * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_MQS_GATE] = imx_clk_hw_gate_dis_flags("mqs_gate", "mqs_sel", ccm_base + (mqs * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_MIC_GATE] = imx_clk_hw_gate_dis_flags("mic_gate", "mic_sel", ccm_base + (mic * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_SPDIF_GATE] = imx_clk_hw_gate_dis_flags("spdif_gate", "spdif_sel", ccm_base + (spdif * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_SAI1_GATE] = imx_clk_hw_gate_dis_flags("sai1_gate", "sai1_sel", ccm_base + (sai1 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_SAI2_GATE] = imx_clk_hw_gate_dis_flags("sai2_gate", "sai2_sel", ccm_base + (sai2 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_SAI3_GATE] = imx_clk_hw_gate_dis_flags("sai3_gate", "sai3_sel", ccm_base + (sai3 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_SAI4_GATE] = imx_clk_hw_gate_dis_flags("sai4_gate", "sai4_sel", ccm_base + (sai4 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_GC355_GATE] = imx_clk_hw_gate_dis_flags("gc355_gate", "gc355_sel", ccm_base + (gc355 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LCDIF_GATE] = imx_clk_hw_gate_dis_flags("lcdif_gate", "lcdif_sel", ccm_base + (lcdif * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_LCDIFV2_GATE] = imx_clk_hw_gate_dis_flags("lcdifv2_gate", "lcdifv2_sel", ccm_base + (lcdifv2 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_MIPI_REF_GATE] = imx_clk_hw_gate_dis_flags("mipi_ref_gate", "mipi_ref_sel", ccm_base + (mipi_ref * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_MIPI_ESC_GATE] = imx_clk_hw_gate_dis_flags("mipi_esc_gate", "mipi_esc_sel", ccm_base + (mipi_esc * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_CSI2_GATE] = imx_clk_hw_gate_dis_flags("csi2_gate", "csi2_sel", ccm_base + (csi2 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_CSI2_ESC_GATE] = imx_clk_hw_gate_dis_flags("csi2_esc_gate", "csi2_esc_sel", ccm_base + (csi2_esc * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_CSI2_UI_GATE] = imx_clk_hw_gate_dis_flags("csi2_ui_gate", "csi2_ui_sel", ccm_base + (csi2_ui * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_CSI_GATE] = imx_clk_hw_gate_dis_flags("csi_gate", "csi_sel", ccm_base + (csi * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_CKO1_GATE] = imx_clk_hw_gate_dis_flags("cko1_gate", "cko1_sel", ccm_base + (cko1 * 0x80), 24, 0);
> + hws[IMXRT1170_CLK_CKO2_GATE] = imx_clk_hw_gate_dis_flags("cko2_gate", "cko2_sel", ccm_base + (cko2 * 0x80), 24, 0);
> +
> + hws[IMXRT1170_CLK_M7] = imx_clk_hw_divider("m7", "m7_gate", ccm_base + (m7 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_M4] = imx_clk_hw_divider("m4", "m4_gate", ccm_base + (m4 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_BUS] = imx_clk_hw_divider("bus", "bus_gate", ccm_base + (bus * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_BUS_LPSR] = imx_clk_hw_divider("bus_lpsr", "bus_lpsr_gate", ccm_base + (bus_lpsr * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_SEMC] = imx_clk_hw_divider("semc", "semc_gate", ccm_base + (semc * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_CSSYS] = imx_clk_hw_divider("cssys", "cssys_gate", ccm_base + (cssys * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_CSTRACE] = imx_clk_hw_divider("cstrace", "cstrace_gate", ccm_base + (cstrace * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_M4_SYSTICK] = imx_clk_hw_divider("m4_systick", "m4_systick_gate", ccm_base + (m4_systick * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_M7_SYSTICK] = imx_clk_hw_divider("m7_systick", "m7_systick_gate", ccm_base + (m7_systick * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_ADC1] = imx_clk_hw_divider("adc1", "adc1_gate", ccm_base + (adc1 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_ADC2] = imx_clk_hw_divider("adc2", "adc2_gate", ccm_base + (adc2 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_ACMP] = imx_clk_hw_divider("acmp", "acmp_gate", ccm_base + (acmp * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_FLEXIO1] = imx_clk_hw_divider("flexio1", "flexio1_gate", ccm_base + (flexio1 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_FLEXIO2] = imx_clk_hw_divider("flexio2", "flexio2_gate", ccm_base + (flexio2 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_GPT1] = imx_clk_hw_divider("gpt1", "gpt1_gate", ccm_base + (gpt1 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_GPT2] = imx_clk_hw_divider("gpt2", "gpt2_gate", ccm_base + (gpt2 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_GPT3] = imx_clk_hw_divider("gpt3", "gpt3_gate", ccm_base + (gpt3 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_GPT4] = imx_clk_hw_divider("gpt4", "gpt4_gate", ccm_base + (gpt4 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_GPT5] = imx_clk_hw_divider("gpt5", "gpt5_gate", ccm_base + (gpt5 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_GPT6] = imx_clk_hw_divider("gpt6", "gpt6_gate", ccm_base + (gpt6 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_FLEXSPI1] = imx_clk_hw_divider("flexspi1", "flexspi1_gate", ccm_base + (flexspi1 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_FLEXSPI2] = imx_clk_hw_divider("flexspi2", "flexspi2_gate", ccm_base + (flexspi2 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_CAN1] = imx_clk_hw_divider("can1", "can1_gate", ccm_base + (can1 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_CAN2] = imx_clk_hw_divider("can2", "can2_gate", ccm_base + (can2 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_CAN3] = imx_clk_hw_divider("can3", "can3_gate", ccm_base + (can3 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPUART1] = imx_clk_hw_divider("lpuart1", "lpuart1_gate", ccm_base + (lpuart1 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPUART2] = imx_clk_hw_divider("lpuart2", "lpuart2_gate", ccm_base + (lpuart2 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPUART3] = imx_clk_hw_divider("lpuart3", "lpuart3_gate", ccm_base + (lpuart3 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPUART4] = imx_clk_hw_divider("lpuart4", "lpuart4_gate", ccm_base + (lpuart4 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPUART5] = imx_clk_hw_divider("lpuart5", "lpuart5_gate", ccm_base + (lpuart5 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPUART6] = imx_clk_hw_divider("lpuart6", "lpuart6_gate", ccm_base + (lpuart6 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPUART7] = imx_clk_hw_divider("lpuart7", "lpuart7_gate", ccm_base + (lpuart7 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPUART8] = imx_clk_hw_divider("lpuart8", "lpuart8_gate", ccm_base + (lpuart8 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPUART9] = imx_clk_hw_divider("lpuart9", "lpuart9_gate", ccm_base + (lpuart9 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPUART10] = imx_clk_hw_divider("lpuart10", "lpuart10_gate", ccm_base + (lpuart10 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPUART11] = imx_clk_hw_divider("lpuart11", "lpuart11_gate", ccm_base + (lpuart11 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPUART12] = imx_clk_hw_divider("lpuart12", "lpuart12_gate", ccm_base + (lpuart12 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPI2C1] = imx_clk_hw_divider("lpi2c1", "lpi2c1_gate", ccm_base + (lpi2c1 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPI2C2] = imx_clk_hw_divider("lpi2c2", "lpi2c2_gate", ccm_base + (lpi2c2 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPI2C3] = imx_clk_hw_divider("lpi2c3", "lpi2c3_gate", ccm_base + (lpi2c3 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPI2C4] = imx_clk_hw_divider("lpi2c4", "lpi2c4_gate", ccm_base + (lpi2c4 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPI2C5] = imx_clk_hw_divider("lpi2c5", "lpi2c5_gate", ccm_base + (lpi2c5 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPI2C6] = imx_clk_hw_divider("lpi2c6", "lpi2c6_gate", ccm_base + (lpi2c6 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPSPI1] = imx_clk_hw_divider("lpspi1", "lpspi1_gate", ccm_base + (lpspi1 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPSPI2] = imx_clk_hw_divider("lpspi2", "lpspi2_gate", ccm_base + (lpspi2 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPSPI3] = imx_clk_hw_divider("lpspi3", "lpspi3_gate", ccm_base + (lpspi3 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPSPI4] = imx_clk_hw_divider("lpspi4", "lpspi4_gate", ccm_base + (lpspi4 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPSPI5] = imx_clk_hw_divider("lpspi5", "lpspi5_gate", ccm_base + (lpspi5 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LPSPI6] = imx_clk_hw_divider("lpspi6", "lpspi6_gate", ccm_base + (lpspi6 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_EMV1] = imx_clk_hw_divider("emv1", "emv1_gate", ccm_base + (emv1 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_EMV2] = imx_clk_hw_divider("emv2", "emv2_gate", ccm_base + (emv2 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_ENET1] = imx_clk_hw_divider("enet1", "enet1_gate", ccm_base + (enet1 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_ENET2] = imx_clk_hw_divider("enet2", "enet2_gate", ccm_base + (enet2 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_ENET_QOS] = imx_clk_hw_divider("enet_qos", "enet_qos_gate", ccm_base + (enet_qos * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_ENET_25M] = imx_clk_hw_divider("enet_25m", "enet_25m_gate", ccm_base + (enet_25m * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_ENET_TIMER1] = imx_clk_hw_divider("enet_timer1", "enet_timer1_gate", ccm_base + (enet_timer1 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_ENET_TIMER2] = imx_clk_hw_divider("enet_timer2", "enet_timer2_gate", ccm_base + (enet_timer2 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_ENET_TIMER3] = imx_clk_hw_divider("enet_timer3", "enet_timer3_gate", ccm_base + (enet_timer3 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_USDHC1] = imx_clk_hw_divider("usdhc1", "usdhc1_gate", ccm_base + (usdhc1 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_USDHC2] = imx_clk_hw_divider("usdhc2", "usdhc2_gate", ccm_base + (usdhc2 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_ASRC] = imx_clk_hw_divider("asrc", "asrc_gate", ccm_base + (asrc * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_MQS] = imx_clk_hw_divider("mqs", "mqs_gate", ccm_base + (mqs * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_MIC] = imx_clk_hw_divider("mic", "mic_gate", ccm_base + (mic * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_SPDIF] = imx_clk_hw_divider("spdif", "spdif_gate", ccm_base + (spdif * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_SAI1] = imx_clk_hw_divider("sai1", "sai1_gate", ccm_base + (sai1 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_SAI2] = imx_clk_hw_divider("sai2", "sai2_gate", ccm_base + (sai2 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_SAI3] = imx_clk_hw_divider("sai3", "sai3_gate", ccm_base + (sai3 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_SAI4] = imx_clk_hw_divider("sai4", "sai4_gate", ccm_base + (sai4 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_GC355] = imx_clk_hw_divider("gc355", "gc355_gate", ccm_base + (gc355 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LCDIF] = imx_clk_hw_divider("lcdif", "lcdif_gate", ccm_base + (lcdif * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_LCDIFV2] = imx_clk_hw_divider("lcdifv2", "lcdifv2_gate", ccm_base + (lcdifv2 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_MIPI_REF] = imx_clk_hw_divider("mipi_ref", "mipi_ref_gate", ccm_base + (mipi_ref * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_MIPI_ESC] = imx_clk_hw_divider("mipi_esc", "mipi_esc_gate", ccm_base + (mipi_esc * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_CSI2] = imx_clk_hw_divider("csi2", "csi2_gate", ccm_base + (csi2 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_CSI2_ESC] = imx_clk_hw_divider("csi2_esc", "csi2_esc_gate", ccm_base + (csi2_esc * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_CSI2_UI] = imx_clk_hw_divider("csi2_ui", "csi2_ui_gate", ccm_base + (csi2_ui * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_CSI] = imx_clk_hw_divider("csi", "csi_gate", ccm_base + (csi * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_CKO1] = imx_clk_hw_divider("cko1", "cko1_gate", ccm_base + (cko1 * 0x80), 0, 8);
> + hws[IMXRT1170_CLK_CKO2] = imx_clk_hw_divider("cko2", "cko2_gate", ccm_base + (cko2 * 0x80), 0, 8);
> +
> + hws[IMXRT1170_CLK_USB] = imx_clk_hw_gate("usb", "bus", ccm_base + LPCG_GATE(115), 0);
> +
> + imx_check_clk_hws(hws, IMXRT1170_CLK_END);
> +
> + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
> + if (ret < 0) {
> + dev_err(dev, "Failed to register clks for i.MXRT1170.\n");
> + imx_unregister_hw_clocks(hws, IMXRT1170_CLK_END);
> + }
> + return ret;
> +}
> +
> +static const struct of_device_id imxrt1170_clk_of_match[] = {
> + { .compatible = "fsl,imxrt1170-ccm" },
> + { /* Sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, imxrt1170_clk_of_match);
> +
> +static struct platform_driver imxrt1170_clk_driver = {
> + .probe = imxrt1170_clocks_probe,
> + .driver = {
> + .name = "imxrt1170-ccm",
> + .of_match_table = imxrt1170_clk_of_match,
> + },
> +};
> +module_platform_driver(imxrt1170_clk_driver);
> --
> 2.35.1
>
Add the pinctrl driver support for i.MXRT1170.
Cc: Giulio Benetti <[email protected]>
Signed-off-by: Jesse Taube <[email protected]>
---
V1 -> V2:
- Nothing done
---
drivers/pinctrl/freescale/Kconfig | 7 +
drivers/pinctrl/freescale/Makefile | 1 +
drivers/pinctrl/freescale/pinctrl-imxrt1170.c | 349 ++++++++++++++++++
3 files changed, 357 insertions(+)
create mode 100644 drivers/pinctrl/freescale/pinctrl-imxrt1170.c
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index 21fa21c6547b..15af3d80e119 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -192,3 +192,10 @@ config PINCTRL_IMX23
config PINCTRL_IMX28
bool
select PINCTRL_MXS
+
+config PINCTRL_IMXRT1170
+ bool "IMXRT1170 pinctrl driver"
+ depends on ARCH_MXC
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imxrt1170 pinctrl driver
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index c44930b1b362..c2c088ca33cc 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -30,3 +30,4 @@ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
+obj-$(CONFIG_PINCTRL_IMXRT1170) += pinctrl-imxrt1170.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imxrt1170.c b/drivers/pinctrl/freescale/pinctrl-imxrt1170.c
new file mode 100644
index 000000000000..5da1545fde91
--- /dev/null
+++ b/drivers/pinctrl/freescale/pinctrl-imxrt1170.c
@@ -0,0 +1,349 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022
+ * Author(s): Jesse Taube <[email protected]>
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/platform_device.h>
+
+#include "pinctrl-imx.h"
+
+enum imxrt1170_pads {
+ IMXRT1170_PAD_RESERVE0,
+ IMXRT1170_PAD_RESERVE1,
+ IMXRT1170_PAD_RESERVE2,
+ IMXRT1170_PAD_RESERVE3,
+ IMXRT1170_PAD_EMC_B1_00,
+ IMXRT1170_PAD_EMC_B1_01,
+ IMXRT1170_PAD_EMC_B1_02,
+ IMXRT1170_PAD_EMC_B1_03,
+ IMXRT1170_PAD_EMC_B1_04,
+ IMXRT1170_PAD_EMC_B1_05,
+ IMXRT1170_PAD_EMC_B1_06,
+ IMXRT1170_PAD_EMC_B1_07,
+ IMXRT1170_PAD_EMC_B1_08,
+ IMXRT1170_PAD_EMC_B1_09,
+ IMXRT1170_PAD_EMC_B1_10,
+ IMXRT1170_PAD_EMC_B1_11,
+ IMXRT1170_PAD_EMC_B1_12,
+ IMXRT1170_PAD_EMC_B1_13,
+ IMXRT1170_PAD_EMC_B1_14,
+ IMXRT1170_PAD_EMC_B1_15,
+ IMXRT1170_PAD_EMC_B1_16,
+ IMXRT1170_PAD_EMC_B1_17,
+ IMXRT1170_PAD_EMC_B1_18,
+ IMXRT1170_PAD_EMC_B1_19,
+ IMXRT1170_PAD_EMC_B1_20,
+ IMXRT1170_PAD_EMC_B1_21,
+ IMXRT1170_PAD_EMC_B1_22,
+ IMXRT1170_PAD_EMC_B1_23,
+ IMXRT1170_PAD_EMC_B1_24,
+ IMXRT1170_PAD_EMC_B1_25,
+ IMXRT1170_PAD_EMC_B1_26,
+ IMXRT1170_PAD_EMC_B1_27,
+ IMXRT1170_PAD_EMC_B1_28,
+ IMXRT1170_PAD_EMC_B1_29,
+ IMXRT1170_PAD_EMC_B1_30,
+ IMXRT1170_PAD_EMC_B1_31,
+ IMXRT1170_PAD_EMC_B1_32,
+ IMXRT1170_PAD_EMC_B1_33,
+ IMXRT1170_PAD_EMC_B1_34,
+ IMXRT1170_PAD_EMC_B1_35,
+ IMXRT1170_PAD_EMC_B1_36,
+ IMXRT1170_PAD_EMC_B1_37,
+ IMXRT1170_PAD_EMC_B1_38,
+ IMXRT1170_PAD_EMC_B1_39,
+ IMXRT1170_PAD_EMC_B1_40,
+ IMXRT1170_PAD_EMC_B1_41,
+ IMXRT1170_PAD_EMC_B2_00,
+ IMXRT1170_PAD_EMC_B2_01,
+ IMXRT1170_PAD_EMC_B2_02,
+ IMXRT1170_PAD_EMC_B2_03,
+ IMXRT1170_PAD_EMC_B2_04,
+ IMXRT1170_PAD_EMC_B2_05,
+ IMXRT1170_PAD_EMC_B2_06,
+ IMXRT1170_PAD_EMC_B2_07,
+ IMXRT1170_PAD_EMC_B2_08,
+ IMXRT1170_PAD_EMC_B2_09,
+ IMXRT1170_PAD_EMC_B2_10,
+ IMXRT1170_PAD_EMC_B2_11,
+ IMXRT1170_PAD_EMC_B2_12,
+ IMXRT1170_PAD_EMC_B2_13,
+ IMXRT1170_PAD_EMC_B2_14,
+ IMXRT1170_PAD_EMC_B2_15,
+ IMXRT1170_PAD_EMC_B2_16,
+ IMXRT1170_PAD_EMC_B2_17,
+ IMXRT1170_PAD_EMC_B2_18,
+ IMXRT1170_PAD_EMC_B2_19,
+ IMXRT1170_PAD_EMC_B2_20,
+ IMXRT1170_PAD_AD_00,
+ IMXRT1170_PAD_AD_01,
+ IMXRT1170_PAD_AD_02,
+ IMXRT1170_PAD_AD_03,
+ IMXRT1170_PAD_AD_04,
+ IMXRT1170_PAD_AD_05,
+ IMXRT1170_PAD_AD_06,
+ IMXRT1170_PAD_AD_07,
+ IMXRT1170_PAD_AD_08,
+ IMXRT1170_PAD_AD_09,
+ IMXRT1170_PAD_AD_10,
+ IMXRT1170_PAD_AD_11,
+ IMXRT1170_PAD_AD_12,
+ IMXRT1170_PAD_AD_13,
+ IMXRT1170_PAD_AD_14,
+ IMXRT1170_PAD_AD_15,
+ IMXRT1170_PAD_AD_16,
+ IMXRT1170_PAD_AD_17,
+ IMXRT1170_PAD_AD_18,
+ IMXRT1170_PAD_AD_19,
+ IMXRT1170_PAD_AD_20,
+ IMXRT1170_PAD_AD_21,
+ IMXRT1170_PAD_AD_22,
+ IMXRT1170_PAD_AD_23,
+ IMXRT1170_PAD_AD_24,
+ IMXRT1170_PAD_AD_25,
+ IMXRT1170_PAD_AD_26,
+ IMXRT1170_PAD_AD_27,
+ IMXRT1170_PAD_AD_28,
+ IMXRT1170_PAD_AD_29,
+ IMXRT1170_PAD_AD_30,
+ IMXRT1170_PAD_AD_31,
+ IMXRT1170_PAD_AD_32,
+ IMXRT1170_PAD_AD_33,
+ IMXRT1170_PAD_AD_34,
+ IMXRT1170_PAD_AD_35,
+ IMXRT1170_PAD_SD_B1_00,
+ IMXRT1170_PAD_SD_B1_01,
+ IMXRT1170_PAD_SD_B1_02,
+ IMXRT1170_PAD_SD_B1_03,
+ IMXRT1170_PAD_SD_B1_04,
+ IMXRT1170_PAD_SD_B1_05,
+ IMXRT1170_PAD_SD_B2_00,
+ IMXRT1170_PAD_SD_B2_01,
+ IMXRT1170_PAD_SD_B2_02,
+ IMXRT1170_PAD_SD_B2_03,
+ IMXRT1170_PAD_SD_B2_04,
+ IMXRT1170_PAD_SD_B2_05,
+ IMXRT1170_PAD_SD_B2_06,
+ IMXRT1170_PAD_SD_B2_07,
+ IMXRT1170_PAD_SD_B2_08,
+ IMXRT1170_PAD_SD_B2_09,
+ IMXRT1170_PAD_SD_B2_10,
+ IMXRT1170_PAD_SD_B2_11,
+ IMXRT1170_PAD_DISP_B1_00,
+ IMXRT1170_PAD_DISP_B1_01,
+ IMXRT1170_PAD_DISP_B1_02,
+ IMXRT1170_PAD_DISP_B1_03,
+ IMXRT1170_PAD_DISP_B1_04,
+ IMXRT1170_PAD_DISP_B1_05,
+ IMXRT1170_PAD_DISP_B1_06,
+ IMXRT1170_PAD_DISP_B1_07,
+ IMXRT1170_PAD_DISP_B1_08,
+ IMXRT1170_PAD_DISP_B1_09,
+ IMXRT1170_PAD_DISP_B1_10,
+ IMXRT1170_PAD_DISP_B1_11,
+ IMXRT1170_PAD_DISP_B2_00,
+ IMXRT1170_PAD_DISP_B2_01,
+ IMXRT1170_PAD_DISP_B2_02,
+ IMXRT1170_PAD_DISP_B2_03,
+ IMXRT1170_PAD_DISP_B2_04,
+ IMXRT1170_PAD_DISP_B2_05,
+ IMXRT1170_PAD_DISP_B2_06,
+ IMXRT1170_PAD_DISP_B2_07,
+ IMXRT1170_PAD_DISP_B2_08,
+ IMXRT1170_PAD_DISP_B2_09,
+ IMXRT1170_PAD_DISP_B2_10,
+ IMXRT1170_PAD_DISP_B2_11,
+ IMXRT1170_PAD_DISP_B2_12,
+ IMXRT1170_PAD_DISP_B2_13,
+ IMXRT1170_PAD_DISP_B2_14,
+ IMXRT1170_PAD_DISP_B2_15,
+};
+
+/* Pad names for the pinmux subsystem */
+static const struct pinctrl_pin_desc imxrt1170_pinctrl_pads[] = {
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE0),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE1),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE2),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE3),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_00),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_01),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_02),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_03),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_04),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_05),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_06),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_07),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_08),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_09),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_10),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_11),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_12),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_13),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_14),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_15),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_16),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_17),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_18),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_19),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_20),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_21),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_22),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_23),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_24),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_25),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_26),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_27),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_28),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_29),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_30),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_31),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_32),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_33),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_34),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_35),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_36),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_37),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_38),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_39),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_40),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_41),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_00),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_01),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_02),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_03),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_04),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_05),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_06),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_07),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_08),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_09),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_10),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_11),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_12),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_13),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_14),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_15),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_16),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_17),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_18),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_19),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_20),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_00),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_01),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_02),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_03),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_04),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_05),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_06),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_07),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_08),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_09),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_10),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_11),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_12),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_13),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_14),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_15),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_16),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_17),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_18),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_19),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_20),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_21),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_22),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_23),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_24),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_25),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_26),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_27),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_28),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_29),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_30),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_31),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_32),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_33),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_34),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_35),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_00),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_01),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_02),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_03),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_04),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_05),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_00),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_01),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_02),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_03),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_04),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_05),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_06),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_07),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_08),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_09),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_10),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_11),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_00),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_01),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_02),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_03),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_04),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_05),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_06),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_07),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_08),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_09),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_10),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_11),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_00),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_01),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_02),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_03),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_04),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_05),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_06),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_07),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_08),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_09),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_10),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_11),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_12),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_13),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_14),
+ IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_15),
+};
+
+static const struct imx_pinctrl_soc_info imxrt1170_pinctrl_info = {
+ .pins = imxrt1170_pinctrl_pads,
+ .npins = ARRAY_SIZE(imxrt1170_pinctrl_pads),
+ .gpr_compatible = "fsl,imxrt1170-iomuxc-gpr",
+};
+
+static const struct of_device_id imxrt1170_pinctrl_of_match[] = {
+ { .compatible = "fsl,imxrt1170-iomuxc", .data = &imxrt1170_pinctrl_info, },
+ { /* sentinel */ }
+};
+
+static int imxrt1170_pinctrl_probe(struct platform_device *pdev)
+{
+ return imx_pinctrl_probe(pdev, &imxrt1170_pinctrl_info);
+}
+
+static struct platform_driver imxrt1170_pinctrl_driver = {
+ .driver = {
+ .name = "imxrt1170-pinctrl",
+ .of_match_table = of_match_ptr(imxrt1170_pinctrl_of_match),
+ .suppress_bind_attrs = true,
+ },
+ .probe = imxrt1170_pinctrl_probe,
+};
+
+static int __init imxrt1170_pinctrl_init(void)
+{
+ return platform_driver_register(&imxrt1170_pinctrl_driver);
+}
+arch_initcall(imxrt1170_pinctrl_init);
--
2.35.1
On Thu, 28 Apr 2022 17:48:24 -0400, Jesse Taube wrote:
> Recently the imxrt1050 was added but the cpu compatible node wasn't
> added. Add both i.MXRT1170 and 1050 compatibles to fsl.yaml.
>
> Signed-off-by: Jesse Taube <[email protected]>
> ---
> V1 -> V2:
> - Swap order of soc's
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
Acked-by: Rob Herring <[email protected]>
On Thu, Apr 28, 2022 at 05:48:33PM -0400, Jesse Taube wrote:
> Add the clock binding doc for i.MXRT1170.
>
> Cc: Giulio Benetti <[email protected]>
> Signed-off-by: Jesse Taube <[email protected]>
> ---
> V1 -> V2:
> - Change to GPL-2.0-only
> ---
> include/dt-bindings/clock/imxrt1170-clock.h | 282 ++++++++++++++++++++
> 1 file changed, 282 insertions(+)
> create mode 100644 include/dt-bindings/clock/imxrt1170-clock.h
>
> diff --git a/include/dt-bindings/clock/imxrt1170-clock.h b/include/dt-bindings/clock/imxrt1170-clock.h
> new file mode 100644
> index 000000000000..a88137f6cbc1
> --- /dev/null
> +++ b/include/dt-bindings/clock/imxrt1170-clock.h
> @@ -0,0 +1,282 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
Should be:
(GPL-2.0-only OR BSD-2-Clause)
Unless there's a reason you can't.
> +/*
> + * Copyright(C) 2022
> + * Author(s): Jesse Taube <[email protected]>
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_IMXRT1170_H
> +#define __DT_BINDINGS_CLOCK_IMXRT1170_H
> +
> +#define IMXRT1170_CLK_DUMMY 0
> +#define IMXRT1170_CLK_OSC 1
> +#define IMXRT1170_CLK_OSC_32K 2
> +#define IMXRT1170_CLK_RCOSC_16M 3
> +#define IMXRT1170_CLK_RCOSC_48M 4
> +#define IMXRT1170_CLK_RCOSC_48M_DIV2 5
> +#define IMXRT1170_CLK_RCOSC_400M 6
> +#define IMXRT1170_CLK_PLL_ARM_PRE 7
> +#define IMXRT1170_CLK_PLL_ARM_BYPASS 8
> +#define IMXRT1170_CLK_PLL_ARM_DIV 9
> +#define IMXRT1170_CLK_PLL_ARM 10
> +#define IMXRT1170_CLK_PLL_AUDIO 11
> +#define IMXRT1170_CLK_PLL_VIDEO 12
> +#define IMXRT1170_CLK_PLL1 13
> +#define IMXRT1170_CLK_PLL1_DIV2 14
> +#define IMXRT1170_CLK_PLL1_DIV5 15
> +#define IMXRT1170_CLK_PLL2_PRE 16
> +#define IMXRT1170_CLK_PLL2_BYPASS 17
> +#define IMXRT1170_CLK_PLL2 18
> +#define IMXRT1170_CLK_PLL2_PFD0 19
> +#define IMXRT1170_CLK_PLL2_PFD1 20
> +#define IMXRT1170_CLK_PLL2_PFD2 21
> +#define IMXRT1170_CLK_PLL2_PFD3 22
> +#define IMXRT1170_CLK_PLL3_PRE 23
> +#define IMXRT1170_CLK_PLL3_BYPASS 24
> +#define IMXRT1170_CLK_PLL3 25
> +#define IMXRT1170_CLK_PLL3_DIV2_GATE 26
> +#define IMXRT1170_CLK_PLL3_DIV2 27
> +#define IMXRT1170_CLK_PLL3_PFD0 28
> +#define IMXRT1170_CLK_PLL3_PFD1 29
> +#define IMXRT1170_CLK_PLL3_PFD2 30
> +#define IMXRT1170_CLK_PLL3_PFD3 31
> +#define IMXRT1170_CLK_M7_SEL 32
> +#define IMXRT1170_CLK_M7_GATE 33
> +#define IMXRT1170_CLK_M7 34
> +#define IMXRT1170_CLK_M4_SEL 35
> +#define IMXRT1170_CLK_M4_GATE 36
> +#define IMXRT1170_CLK_M4 37
> +#define IMXRT1170_CLK_BUS_SEL 38
> +#define IMXRT1170_CLK_BUS_GATE 39
> +#define IMXRT1170_CLK_BUS 40
> +#define IMXRT1170_CLK_BUS_LPSR_SEL 41
> +#define IMXRT1170_CLK_BUS_LPSR_GATE 42
> +#define IMXRT1170_CLK_BUS_LPSR 43
> +#define IMXRT1170_CLK_SEMC_SEL 44
> +#define IMXRT1170_CLK_SEMC_GATE 45
> +#define IMXRT1170_CLK_SEMC 46
> +#define IMXRT1170_CLK_CSSYS_SEL 47
> +#define IMXRT1170_CLK_CSSYS_GATE 48
> +#define IMXRT1170_CLK_CSSYS 49
> +#define IMXRT1170_CLK_CSTRACE_SEL 50
> +#define IMXRT1170_CLK_CSTRACE_GATE 51
> +#define IMXRT1170_CLK_CSTRACE 52
> +#define IMXRT1170_CLK_M4_SYSTICK_SEL 53
> +#define IMXRT1170_CLK_M4_SYSTICK_GATE 54
> +#define IMXRT1170_CLK_M4_SYSTICK 55
> +#define IMXRT1170_CLK_M7_SYSTICK_SEL 56
> +#define IMXRT1170_CLK_M7_SYSTICK_GATE 57
> +#define IMXRT1170_CLK_M7_SYSTICK 58
> +#define IMXRT1170_CLK_ADC1_SEL 59
> +#define IMXRT1170_CLK_ADC1_GATE 60
> +#define IMXRT1170_CLK_ADC1 61
> +#define IMXRT1170_CLK_ADC2_SEL 62
> +#define IMXRT1170_CLK_ADC2_GATE 63
> +#define IMXRT1170_CLK_ADC2 64
> +#define IMXRT1170_CLK_ACMP_SEL 65
> +#define IMXRT1170_CLK_ACMP_GATE 66
> +#define IMXRT1170_CLK_ACMP 67
> +#define IMXRT1170_CLK_FLEXIO1_SEL 68
> +#define IMXRT1170_CLK_FLEXIO1_GATE 69
> +#define IMXRT1170_CLK_FLEXIO1 70
> +#define IMXRT1170_CLK_FLEXIO2_SEL 71
> +#define IMXRT1170_CLK_FLEXIO2_GATE 72
> +#define IMXRT1170_CLK_FLEXIO2 73
> +#define IMXRT1170_CLK_GPT1_SEL 74
> +#define IMXRT1170_CLK_GPT1_GATE 75
> +#define IMXRT1170_CLK_GPT1 76
> +#define IMXRT1170_CLK_GPT2_SEL 77
> +#define IMXRT1170_CLK_GPT2_GATE 78
> +#define IMXRT1170_CLK_GPT2 79
> +#define IMXRT1170_CLK_GPT3_SEL 80
> +#define IMXRT1170_CLK_GPT3_GATE 81
> +#define IMXRT1170_CLK_GPT3 82
> +#define IMXRT1170_CLK_GPT4_SEL 83
> +#define IMXRT1170_CLK_GPT4_GATE 84
> +#define IMXRT1170_CLK_GPT4 85
> +#define IMXRT1170_CLK_GPT5_SEL 86
> +#define IMXRT1170_CLK_GPT5_GATE 87
> +#define IMXRT1170_CLK_GPT5 88
> +#define IMXRT1170_CLK_GPT6_SEL 89
> +#define IMXRT1170_CLK_GPT6_GATE 90
> +#define IMXRT1170_CLK_GPT6 91
> +#define IMXRT1170_CLK_FLEXSPI1_SEL 92
> +#define IMXRT1170_CLK_FLEXSPI1_GATE 93
> +#define IMXRT1170_CLK_FLEXSPI1 94
> +#define IMXRT1170_CLK_FLEXSPI2_SEL 95
> +#define IMXRT1170_CLK_FLEXSPI2_GATE 96
> +#define IMXRT1170_CLK_FLEXSPI2 97
> +#define IMXRT1170_CLK_CAN1_SEL 98
> +#define IMXRT1170_CLK_CAN1_GATE 99
> +#define IMXRT1170_CLK_CAN1 100
> +#define IMXRT1170_CLK_CAN2_SEL 101
> +#define IMXRT1170_CLK_CAN2_GATE 102
> +#define IMXRT1170_CLK_CAN2 103
> +#define IMXRT1170_CLK_CAN3_SEL 104
> +#define IMXRT1170_CLK_CAN3_GATE 105
> +#define IMXRT1170_CLK_CAN3 106
> +#define IMXRT1170_CLK_LPUART1_SEL 107
> +#define IMXRT1170_CLK_LPUART1_GATE 108
> +#define IMXRT1170_CLK_LPUART1 109
> +#define IMXRT1170_CLK_LPUART2_SEL 110
> +#define IMXRT1170_CLK_LPUART2_GATE 111
> +#define IMXRT1170_CLK_LPUART2 112
> +#define IMXRT1170_CLK_LPUART3_SEL 113
> +#define IMXRT1170_CLK_LPUART3_GATE 114
> +#define IMXRT1170_CLK_LPUART3 115
> +#define IMXRT1170_CLK_LPUART4_SEL 116
> +#define IMXRT1170_CLK_LPUART4_GATE 117
> +#define IMXRT1170_CLK_LPUART4 118
> +#define IMXRT1170_CLK_LPUART5_SEL 119
> +#define IMXRT1170_CLK_LPUART5_GATE 120
> +#define IMXRT1170_CLK_LPUART5 121
> +#define IMXRT1170_CLK_LPUART6_SEL 122
> +#define IMXRT1170_CLK_LPUART6_GATE 123
> +#define IMXRT1170_CLK_LPUART6 124
> +#define IMXRT1170_CLK_LPUART7_SEL 125
> +#define IMXRT1170_CLK_LPUART7_GATE 126
> +#define IMXRT1170_CLK_LPUART7 127
> +#define IMXRT1170_CLK_LPUART8_SEL 128
> +#define IMXRT1170_CLK_LPUART8_GATE 129
> +#define IMXRT1170_CLK_LPUART8 130
> +#define IMXRT1170_CLK_LPUART9_SEL 131
> +#define IMXRT1170_CLK_LPUART9_GATE 132
> +#define IMXRT1170_CLK_LPUART9 133
> +#define IMXRT1170_CLK_LPUART10_SEL 134
> +#define IMXRT1170_CLK_LPUART10_GATE 135
> +#define IMXRT1170_CLK_LPUART10 136
> +#define IMXRT1170_CLK_LPUART11_SEL 137
> +#define IMXRT1170_CLK_LPUART11_GATE 138
> +#define IMXRT1170_CLK_LPUART11 139
> +#define IMXRT1170_CLK_LPUART12_SEL 140
> +#define IMXRT1170_CLK_LPUART12_GATE 141
> +#define IMXRT1170_CLK_LPUART12 142
> +#define IMXRT1170_CLK_LPI2C1_SEL 143
> +#define IMXRT1170_CLK_LPI2C1_GATE 144
> +#define IMXRT1170_CLK_LPI2C1 145
> +#define IMXRT1170_CLK_LPI2C2_SEL 146
> +#define IMXRT1170_CLK_LPI2C2_GATE 147
> +#define IMXRT1170_CLK_LPI2C2 148
> +#define IMXRT1170_CLK_LPI2C3_SEL 149
> +#define IMXRT1170_CLK_LPI2C3_GATE 150
> +#define IMXRT1170_CLK_LPI2C3 151
> +#define IMXRT1170_CLK_LPI2C4_SEL 152
> +#define IMXRT1170_CLK_LPI2C4_GATE 153
> +#define IMXRT1170_CLK_LPI2C4 154
> +#define IMXRT1170_CLK_LPI2C5_SEL 155
> +#define IMXRT1170_CLK_LPI2C5_GATE 156
> +#define IMXRT1170_CLK_LPI2C5 157
> +#define IMXRT1170_CLK_LPI2C6_SEL 158
> +#define IMXRT1170_CLK_LPI2C6_GATE 159
> +#define IMXRT1170_CLK_LPI2C6 160
> +#define IMXRT1170_CLK_LPSPI1_SEL 161
> +#define IMXRT1170_CLK_LPSPI1_GATE 162
> +#define IMXRT1170_CLK_LPSPI1 163
> +#define IMXRT1170_CLK_LPSPI2_SEL 164
> +#define IMXRT1170_CLK_LPSPI2_GATE 165
> +#define IMXRT1170_CLK_LPSPI2 166
> +#define IMXRT1170_CLK_LPSPI3_SEL 167
> +#define IMXRT1170_CLK_LPSPI3_GATE 168
> +#define IMXRT1170_CLK_LPSPI3 169
> +#define IMXRT1170_CLK_LPSPI4_SEL 170
> +#define IMXRT1170_CLK_LPSPI4_GATE 171
> +#define IMXRT1170_CLK_LPSPI4 172
> +#define IMXRT1170_CLK_LPSPI5_SEL 173
> +#define IMXRT1170_CLK_LPSPI5_GATE 174
> +#define IMXRT1170_CLK_LPSPI5 175
> +#define IMXRT1170_CLK_LPSPI6_SEL 176
> +#define IMXRT1170_CLK_LPSPI6_GATE 177
> +#define IMXRT1170_CLK_LPSPI6 178
> +#define IMXRT1170_CLK_EMV1_SEL 179
> +#define IMXRT1170_CLK_EMV1_GATE 180
> +#define IMXRT1170_CLK_EMV1 181
> +#define IMXRT1170_CLK_EMV2_SEL 182
> +#define IMXRT1170_CLK_EMV2_GATE 183
> +#define IMXRT1170_CLK_EMV2 184
> +#define IMXRT1170_CLK_ENET1_SEL 185
> +#define IMXRT1170_CLK_ENET1_GATE 186
> +#define IMXRT1170_CLK_ENET1 187
> +#define IMXRT1170_CLK_ENET2_SEL 188
> +#define IMXRT1170_CLK_ENET2_GATE 189
> +#define IMXRT1170_CLK_ENET2 190
> +#define IMXRT1170_CLK_ENET_QOS_SEL 191
> +#define IMXRT1170_CLK_ENET_QOS_GATE 192
> +#define IMXRT1170_CLK_ENET_QOS 193
> +#define IMXRT1170_CLK_ENET_25M_SEL 194
> +#define IMXRT1170_CLK_ENET_25M_GATE 195
> +#define IMXRT1170_CLK_ENET_25M 196
> +#define IMXRT1170_CLK_ENET_TIMER1_SEL 197
> +#define IMXRT1170_CLK_ENET_TIMER1_GATE 198
> +#define IMXRT1170_CLK_ENET_TIMER1 199
> +#define IMXRT1170_CLK_ENET_TIMER2_SEL 200
> +#define IMXRT1170_CLK_ENET_TIMER2_GATE 201
> +#define IMXRT1170_CLK_ENET_TIMER2 202
> +#define IMXRT1170_CLK_ENET_TIMER3_SEL 203
> +#define IMXRT1170_CLK_ENET_TIMER3_GATE 204
> +#define IMXRT1170_CLK_ENET_TIMER3 205
> +#define IMXRT1170_CLK_USDHC1_SEL 206
> +#define IMXRT1170_CLK_USDHC1_GATE 207
> +#define IMXRT1170_CLK_USDHC1 208
> +#define IMXRT1170_CLK_USDHC2_SEL 209
> +#define IMXRT1170_CLK_USDHC2_GATE 210
> +#define IMXRT1170_CLK_USDHC2 211
> +#define IMXRT1170_CLK_ASRC_SEL 212
> +#define IMXRT1170_CLK_ASRC_GATE 213
> +#define IMXRT1170_CLK_ASRC 214
> +#define IMXRT1170_CLK_MQS_SEL 215
> +#define IMXRT1170_CLK_MQS_GATE 216
> +#define IMXRT1170_CLK_MQS 217
> +#define IMXRT1170_CLK_MIC_SEL 218
> +#define IMXRT1170_CLK_MIC_GATE 219
> +#define IMXRT1170_CLK_MIC 220
> +#define IMXRT1170_CLK_SPDIF_SEL 221
> +#define IMXRT1170_CLK_SPDIF_GATE 222
> +#define IMXRT1170_CLK_SPDIF 223
> +#define IMXRT1170_CLK_SAI1_SEL 224
> +#define IMXRT1170_CLK_SAI1_GATE 225
> +#define IMXRT1170_CLK_SAI1 226
> +#define IMXRT1170_CLK_SAI2_SEL 227
> +#define IMXRT1170_CLK_SAI2_GATE 228
> +#define IMXRT1170_CLK_SAI2 229
> +#define IMXRT1170_CLK_SAI3_SEL 230
> +#define IMXRT1170_CLK_SAI3_GATE 231
> +#define IMXRT1170_CLK_SAI3 232
> +#define IMXRT1170_CLK_SAI4_SEL 233
> +#define IMXRT1170_CLK_SAI4_GATE 234
> +#define IMXRT1170_CLK_SAI4 235
> +#define IMXRT1170_CLK_GC355_SEL 236
> +#define IMXRT1170_CLK_GC355_GATE 237
> +#define IMXRT1170_CLK_GC355 238
> +#define IMXRT1170_CLK_LCDIF_SEL 239
> +#define IMXRT1170_CLK_LCDIF_GATE 240
> +#define IMXRT1170_CLK_LCDIF 241
> +#define IMXRT1170_CLK_LCDIFV2_SEL 242
> +#define IMXRT1170_CLK_LCDIFV2_GATE 243
> +#define IMXRT1170_CLK_LCDIFV2 244
> +#define IMXRT1170_CLK_MIPI_REF_SEL 245
> +#define IMXRT1170_CLK_MIPI_REF_GATE 246
> +#define IMXRT1170_CLK_MIPI_REF 247
> +#define IMXRT1170_CLK_MIPI_ESC_SEL 248
> +#define IMXRT1170_CLK_MIPI_ESC_GATE 249
> +#define IMXRT1170_CLK_MIPI_ESC 250
> +#define IMXRT1170_CLK_CSI2_SEL 251
> +#define IMXRT1170_CLK_CSI2_GATE 252
> +#define IMXRT1170_CLK_CSI2 253
> +#define IMXRT1170_CLK_CSI2_ESC_SEL 254
> +#define IMXRT1170_CLK_CSI2_ESC_GATE 255
> +#define IMXRT1170_CLK_CSI2_ESC 256
> +#define IMXRT1170_CLK_CSI2_UI_SEL 257
> +#define IMXRT1170_CLK_CSI2_UI_GATE 258
> +#define IMXRT1170_CLK_CSI2_UI 259
> +#define IMXRT1170_CLK_CSI_SEL 260
> +#define IMXRT1170_CLK_CSI_GATE 261
> +#define IMXRT1170_CLK_CSI 262
> +#define IMXRT1170_CLK_CKO1_SEL 263
> +#define IMXRT1170_CLK_CKO1_GATE 264
> +#define IMXRT1170_CLK_CKO1 265
> +#define IMXRT1170_CLK_CKO2_SEL 266
> +#define IMXRT1170_CLK_CKO2_GATE 267
> +#define IMXRT1170_CLK_CKO2 268
> +#define IMXRT1170_CLK_USB 269
> +#define IMXRT1170_CLK_END 270
> +
> +#endif /* __DT_BINDINGS_CLOCK_IMXRT1170_H */
> --
> 2.35.1
>
>
On Thu, 28 Apr 2022 17:48:26 -0400, Jesse Taube wrote:
> Both the i.MXRT1170 and 1050 have the same gpio controller as
> "fsl,imx35-gpio". Add i.MXRT to the compatible list.
>
> Signed-off-by: Jesse Taube <[email protected]>
> ---
> V1 -> V2:
> - New commit to fix dtbs_check
> ---
> Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <[email protected]>
On Thu, May 5, 2022 at 1:23 PM Jesse Taube <[email protected]> wrote:
> > If I get a review from a Freescale maintainer on this driver and the bindings
> > I can merge it separately, correct?
> That's fine with me.
> I cant speak for Abel or Freescale/NXP maintainers though.
I give them some time to review and if I lose my patience I
usually just merge the patches.
Yours,
Linus Walleij
On 5/4/22 17:38, Linus Walleij wrote:
> On Thu, Apr 28, 2022 at 11:49 PM Jesse Taube <[email protected]> wrote:
>
>> Add the pinctrl driver support for i.MXRT1170.
>>
>> Cc: Giulio Benetti <[email protected]>
>> Signed-off-by: Jesse Taube <[email protected]>
>> ---
>> V1 -> V2:
>> - Nothing done
>
> If I get a review from a Freescale maintainer on this driver and the bindings
> I can merge it separately, correct?
That's fine with me.
I cant speak for Abel or Freescale/NXP maintainers though.
Thanks,
Jesse Taube
> Yours,
> Linus Walleij
On Thu, Apr 28, 2022 at 11:49 PM Jesse Taube <[email protected]> wrote:
> Add the pinctrl driver support for i.MXRT1170.
>
> Cc: Giulio Benetti <[email protected]>
> Signed-off-by: Jesse Taube <[email protected]>
> ---
> V1 -> V2:
> - Nothing done
If I get a review from a Freescale maintainer on this driver and the bindings
I can merge it separately, correct?
Yours,
Linus Walleij
> From: Jesse Taube <[email protected]>
> Sent: Friday, April 29, 2022 5:49 AM
>
> Add the pinctrl driver support for i.MXRT1170.
>
> Cc: Giulio Benetti <[email protected]>
> Signed-off-by: Jesse Taube <[email protected]>
> ---
> V1 -> V2:
> - Nothing done
> ---
> drivers/pinctrl/freescale/Kconfig | 7 +
> drivers/pinctrl/freescale/Makefile | 1 +
> drivers/pinctrl/freescale/pinctrl-imxrt1170.c | 349 ++++++++++++++++++
> 3 files changed, 357 insertions(+)
> create mode 100644 drivers/pinctrl/freescale/pinctrl-imxrt1170.c
>
> diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
> index 21fa21c6547b..15af3d80e119 100644
> --- a/drivers/pinctrl/freescale/Kconfig
> +++ b/drivers/pinctrl/freescale/Kconfig
> @@ -192,3 +192,10 @@ config PINCTRL_IMX23 config PINCTRL_IMX28
> bool
> select PINCTRL_MXS
> +
> +config PINCTRL_IMXRT1170
> + bool "IMXRT1170 pinctrl driver"
> + depends on ARCH_MXC
Should it be better SOC_IMXRT?
Otherwise:
Reviewed-by: Dong Aisheng <[email protected]>
Regards
Aisheng