This patchset proposes a currently viable and forward
compatible way to expose the bitmanip/scalar crypto
capability of the platform to the userspace.
Currently viable refers to the property that hardware
platforms can easily modify the riscv,isa field in DT to
tell the kernel it has the capability. Note that QEMU
has already done so in its device tree.
Forward compatible refers to the property that userspace
can still detect the capability of the environment by
using HWCAP regardless of how the mechanism changes
below kernel in the future. I do know that it has not
been settled how to discover a capability, but I think
kernel has to offer some API after all, and HWCAP
is the preferred way among other mechanisms for now.
More discussion on userspace discovering
can be found on my PR to openssl
https://github.com/openssl/openssl/pull/18197
Hongren (Zenithal) Zheng (3):
RISC-V: add Bitmanip/Scalar Crypto parsing from DT
RISC-V: uapi: add HWCAP for Bitmanip/Scalar Crypto
RISC-V: HWCAP: parse Bitmanip/Scalar Crypto HWCAP from DT
arch/riscv/include/asm/elf.h | 2 +
arch/riscv/include/asm/hwcap.h | 16 ++++++
arch/riscv/include/uapi/asm/hwcap.h | 22 ++++++++
arch/riscv/kernel/cpu.c | 14 +++++
arch/riscv/kernel/cpufeature.c | 79 +++++++++++++++++++++++++----
5 files changed, 123 insertions(+), 10 deletions(-)
--
2.35.1
userspace currently lacks a way to detect whether the
platform has Bitmanip/Scalar Crypto capability,
this commit provides a way such that the userspace
can detect it.
RISC-V currently still has no mature mechanism,
but no matter how things in the spec changes,
(no matter how "M" mode things change), the kernel
still needs to offer some API to the userspace.
More discussion can be found at
https://github.com/openssl/openssl/pull/18197
Userspace currently has to use env var to detect them.
This commit along does not assume any specific mechanism
below kernel.
Tested-by: Jiatai He <[email protected]>
Signed-off-by: Hongren (Zenithal) Zheng <[email protected]>
---
arch/riscv/include/uapi/asm/hwcap.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/riscv/include/uapi/asm/hwcap.h b/arch/riscv/include/uapi/asm/hwcap.h
index 46dc3f5ee99f..bfed3e5c338c 100644
--- a/arch/riscv/include/uapi/asm/hwcap.h
+++ b/arch/riscv/include/uapi/asm/hwcap.h
@@ -22,4 +22,26 @@
#define COMPAT_HWCAP_ISA_D (1 << ('D' - 'A'))
#define COMPAT_HWCAP_ISA_C (1 << ('C' - 'A'))
+/*
+ * HWCAP2 flags - for elf_hwcap2 (in kernel) and AT_HWCAP2
+ *
+ * As only 32 bits of elf_hwcap (in kernel) could be used
+ * and RISC-V has reserved 26 bits of it, other caps like
+ * bitmanip and crypto can not be placed in AT_HWCAP
+ */
+#define COMPAT_HWCAP2_ISA_ZBA (1 << 0)
+#define COMPAT_HWCAP2_ISA_ZBB (1 << 1)
+#define COMPAT_HWCAP2_ISA_ZBC (1 << 2)
+#define COMPAT_HWCAP2_ISA_ZBS (1 << 3)
+#define COMPAT_HWCAP2_ISA_ZBKB (1 << 4)
+#define COMPAT_HWCAP2_ISA_ZBKC (1 << 5)
+#define COMPAT_HWCAP2_ISA_ZBKX (1 << 6)
+#define COMPAT_HWCAP2_ISA_ZKND (1 << 7)
+#define COMPAT_HWCAP2_ISA_ZKNE (1 << 8)
+#define COMPAT_HWCAP2_ISA_ZKNH (1 << 9)
+#define COMPAT_HWCAP2_ISA_ZKSED (1 << 10)
+#define COMPAT_HWCAP2_ISA_ZKSH (1 << 11)
+#define COMPAT_HWCAP2_ISA_ZKR (1 << 12)
+#define COMPAT_HWCAP2_ISA_ZKT (1 << 13)
+
#endif /* _UAPI_ASM_RISCV_HWCAP_H */
--
2.35.1