2022-05-15 21:36:19

by Robert Marko

Subject: [PATCH v4 4/6] mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock controller support

IPQ8074 has the APSS clock controller utilizing the same register space as
the APCS, so provide access to the APSS utilizing a child device like
IPQ6018 does as well, but just by utilizing the IPQ8074 specific APSS
clock driver.

Also, APCS register space in IPQ8074 is 0x6000 so max_register needs to be
updated to 0x5FFC.

Signed-off-by: Robert Marko <[email protected]>
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 80a54d81412e..b3b9debf5673 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -33,6 +33,10 @@ static const struct qcom_apcs_ipc_data ipq6018_apcs_data = {
.offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
};

+static const struct qcom_apcs_ipc_data ipq8074_apcs_data = {
+ .offset = 8, .clk_name = "qcom,apss-ipq8074-clk"
+};
+
static const struct qcom_apcs_ipc_data msm8916_apcs_data = {
.offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
};
@@ -57,7 +61,7 @@ static const struct regmap_config apcs_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
- .max_register = 0x1008,
+ .max_register = 0x5FFC,
.fast_io = true,
};

@@ -142,7 +146,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
/* .data is the offset of the ipc register within the global block */
static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data },
- { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &msm8994_apcs_data },
+ { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data },
{ .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data },
{ .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data },
{ .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data },
--
2.36.1

2022-06-30 23:01:49

by Bjorn Andersson

Subject: Re: [PATCH v4 4/6] mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock controller support

On Sun 15 May 15:45 CDT 2022, Robert Marko wrote:

> IPQ8074 has the APSS clock controller utilizing the same register space as
> the APCS, so provide access to the APSS utilizing a child device like
> IPQ6018 does as well, but just by utilizing the IPQ8074 specific APSS
> clock driver.
>
> Also, APCS register space in IPQ8074 is 0x6000 so max_register needs to be
> updated to 0x5FFC.
>
> Signed-off-by: Robert Marko <[email protected]>
> ---
> drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> index 80a54d81412e..b3b9debf5673 100644
> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> @@ -33,6 +33,10 @@ static const struct qcom_apcs_ipc_data ipq6018_apcs_data = {
> .offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
> };
>
> +static const struct qcom_apcs_ipc_data ipq8074_apcs_data = {
> + .offset = 8, .clk_name = "qcom,apss-ipq8074-clk"
> +};
> +
> static const struct qcom_apcs_ipc_data msm8916_apcs_data = {
> .offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
> };
> @@ -57,7 +61,7 @@ static const struct regmap_config apcs_regmap_config = {
> .reg_bits = 32,
> .reg_stride = 4,
> .val_bits = 32,
> - .max_register = 0x1008,
> + .max_register = 0x5FFC,

Please use lower case hex digits.

And please send the mailbox patches separately, to make it clear for the
maintainers that this can be picked independently of others.

Regards,
Bjorn

> .fast_io = true,
> };
>
> @@ -142,7 +146,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
> /* .data is the offset of the ipc register within the global block */
> static const struct of_device_id qcom_apcs_ipc_of_match[] = {
> { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data },
> - { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &msm8994_apcs_data },
> + { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data },
> { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data },
> { .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data },
> { .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data },
> --
> 2.36.1
>

2022-07-04 19:41:56

by Robert Marko

Subject: Re: [PATCH v4 4/6] mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock controller support

On Fri, 1 Jul 2022 at 00:59, Bjorn Andersson <[email protected]> wrote:
>
> On Sun 15 May 15:45 CDT 2022, Robert Marko wrote:
>
> > IPQ8074 has the APSS clock controller utilizing the same register space as
> > the APCS, so provide access to the APSS utilizing a child device like
> > IPQ6018 does as well, but just by utilizing the IPQ8074 specific APSS
> > clock driver.
> >
> > Also, APCS register space in IPQ8074 is 0x6000 so max_register needs to be
> > updated to 0x5FFC.
> >
> > Signed-off-by: Robert Marko <[email protected]>
> > ---
> > drivers/mailbox/qcom-apcs-ipc-mailbox.c | 8 ++++++--
> > 1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> > index 80a54d81412e..b3b9debf5673 100644
> > --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> > +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> > @@ -33,6 +33,10 @@ static const struct qcom_apcs_ipc_data ipq6018_apcs_data = {
> > .offset = 8, .clk_name = "qcom,apss-ipq6018-clk"
> > };
> >
> > +static const struct qcom_apcs_ipc_data ipq8074_apcs_data = {
> > + .offset = 8, .clk_name = "qcom,apss-ipq8074-clk"
> > +};
> > +
> > static const struct qcom_apcs_ipc_data msm8916_apcs_data = {
> > .offset = 8, .clk_name = "qcom-apcs-msm8916-clk"
> > };
> > @@ -57,7 +61,7 @@ static const struct regmap_config apcs_regmap_config = {
> > .reg_bits = 32,
> > .reg_stride = 4,
> > .val_bits = 32,
> > - .max_register = 0x1008,
> > + .max_register = 0x5FFC,
>
> Please use lower case hex digits.

Hi,
Will fix it in v5.

>
> And please send the mailbox patches separately, to make it clear for the
> maintainers that this can be picked independently of others.

Ok, will send patches 4-6 separately.

Regards,
Robert
>
> Regards,
> Bjorn
>
> > .fast_io = true,
> > };
> >
> > @@ -142,7 +146,7 @@ static int qcom_apcs_ipc_remove(struct platform_device *pdev)
> > /* .data is the offset of the ipc register within the global block */
> > static const struct of_device_id qcom_apcs_ipc_of_match[] = {
> > { .compatible = "qcom,ipq6018-apcs-apps-global", .data = &ipq6018_apcs_data },
> > - { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &msm8994_apcs_data },
> > + { .compatible = "qcom,ipq8074-apcs-apps-global", .data = &ipq8074_apcs_data },
> > { .compatible = "qcom,msm8916-apcs-kpss-global", .data = &msm8916_apcs_data },
> > { .compatible = "qcom,msm8939-apcs-kpss-global", .data = &msm8916_apcs_data },
> > { .compatible = "qcom,msm8953-apcs-kpss-global", .data = &msm8994_apcs_data },
> > --
> > 2.36.1
> >