This series adds support for the PCIe controllers found on SC8280XP and
SA8540P.
Included are also three patches that clean up the way the driver handles
different IP revisions (e.g. by modelling optional clocks as being truly
optional).
These patches depend on the recently merged (but currently held off?)
PIPE clock series:
https://lore.kernel.org/all/[email protected]/
as well as the about-to-be-merged MSI series (v17):
https://lore.kernel.org/all/[email protected]/
Note that the final patch in the PIPE clock series is currently missing
from the pci/ctrl/qcom-pending branch:
https://lore.kernel.org/all/[email protected]/
Johan
Changes in v2
- drop the two DT schema fixes which have been applied by Bjorn H and
squashed into the MSI v17 series by Dmitry, respectively
- rebase on pci/ctrl/qcom-pending (2022-07-14)
- fix compatible sort order (Krzysztof)
- amend commit message for first patch to clarify motivation
(Krzysztof)
- add acks and reviewed-by tags from Dmitry, Krzysztof, Mani and Rob
Johan Hovold (8):
dt-bindings: PCI: qcom: Enumerate platforms with single msi interrupt
dt-bindings: PCI: qcom: Add SC8280XP to binding
dt-bindings: PCI: qcom: Add SA8540P to binding
PCI: qcom: Add support for SC8280XP
PCI: qcom: Add support for SA8540P
PCI: qcom: Make all optional clocks optional
PCI: qcom: Clean up IP configurations
PCI: qcom: Sort device-id table
.../devicetree/bindings/pci/qcom,pcie.yaml | 70 +++++++++-
drivers/pci/controller/dwc/pcie-qcom.c | 121 +++++++-----------
2 files changed, 114 insertions(+), 77 deletions(-)
--
2.35.1
The kernel is not a devicetree validator and does not need to re-encode
information which is already available in the devicetree.
This is specifically true for the optional PCIe clocks, some of which
are really interconnect clocks.
Treat also the 2.7.0 optional clocks as truly optional instead of
maintaining a list of clocks per compatible (including two compatible
strings for the two identical controllers on sm8450) just to validate
the devicetree.
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom.c | 28 ++++----------------------
1 file changed, 4 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 699cd8b0f38e..1339f05bee65 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -212,10 +212,6 @@ struct qcom_pcie_ops {
struct qcom_pcie_cfg {
const struct qcom_pcie_ops *ops;
- unsigned int has_tbu_clk:1;
- unsigned int has_ddrss_sf_tbu_clk:1;
- unsigned int has_aggre0_clk:1;
- unsigned int has_aggre1_clk:1;
};
struct qcom_pcie {
@@ -1193,14 +1189,6 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
res->clks[idx++].id = "bus_master";
res->clks[idx++].id = "bus_slave";
res->clks[idx++].id = "slave_q2a";
- if (pcie->cfg->has_tbu_clk)
- res->clks[idx++].id = "tbu";
- if (pcie->cfg->has_ddrss_sf_tbu_clk)
- res->clks[idx++].id = "ddrss_sf_tbu";
- if (pcie->cfg->has_aggre0_clk)
- res->clks[idx++].id = "aggre0";
- if (pcie->cfg->has_aggre1_clk)
- res->clks[idx++].id = "aggre1";
num_clks = idx;
@@ -1208,6 +1196,10 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
if (ret < 0)
return ret;
+ res->clks[idx++].id = "tbu";
+ res->clks[idx++].id = "ddrss_sf_tbu";
+ res->clks[idx++].id = "aggre0";
+ res->clks[idx++].id = "aggre1";
res->clks[idx++].id = "noc_aggr_4";
res->clks[idx++].id = "noc_aggr_south_sf";
res->clks[idx++].id = "cnoc_qx";
@@ -1636,17 +1628,14 @@ static const struct qcom_pcie_cfg ipq4019_cfg = {
static const struct qcom_pcie_cfg sa8540p_cfg = {
.ops = &ops_1_9_0,
- .has_ddrss_sf_tbu_clk = true,
};
static const struct qcom_pcie_cfg sc8280xp_cfg = {
.ops = &ops_1_9_0,
- .has_ddrss_sf_tbu_clk = true,
};
static const struct qcom_pcie_cfg sdm845_cfg = {
.ops = &ops_2_7_0,
- .has_tbu_clk = true,
};
static const struct qcom_pcie_cfg sm8150_cfg = {
@@ -1658,31 +1647,22 @@ static const struct qcom_pcie_cfg sm8150_cfg = {
static const struct qcom_pcie_cfg sm8250_cfg = {
.ops = &ops_1_9_0,
- .has_tbu_clk = true,
- .has_ddrss_sf_tbu_clk = true,
};
static const struct qcom_pcie_cfg sm8450_pcie0_cfg = {
.ops = &ops_1_9_0,
- .has_ddrss_sf_tbu_clk = true,
- .has_aggre0_clk = true,
- .has_aggre1_clk = true,
};
static const struct qcom_pcie_cfg sm8450_pcie1_cfg = {
.ops = &ops_1_9_0,
- .has_ddrss_sf_tbu_clk = true,
- .has_aggre1_clk = true,
};
static const struct qcom_pcie_cfg sc7280_cfg = {
.ops = &ops_1_9_0,
- .has_tbu_clk = true,
};
static const struct qcom_pcie_cfg sc8180x_cfg = {
.ops = &ops_1_9_0,
- .has_tbu_clk = true,
};
static const struct qcom_pcie_cfg ipq6018_cfg = {
--
2.35.1
SA8540P is a new platform related to SC8280XP but which uses a single
host interrupt for MSI routing.
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 577d166a7476..22a2aac4c23f 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -25,6 +25,7 @@ properties:
- qcom,pcie-ipq4019
- qcom,pcie-ipq8074
- qcom,pcie-qcs404
+ - qcom,pcie-sa8540p
- qcom,pcie-sc7280
- qcom,pcie-sc8180x
- qcom,pcie-sc8280xp
@@ -603,6 +604,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,pcie-sa8540p
- qcom,pcie-sc8280xp
then:
properties:
@@ -721,6 +723,7 @@ allOf:
- qcom,pcie-ipq8064-v2
- qcom,pcie-ipq8074
- qcom,pcie-qcs404
+ - qcom,pcie-sa8540p
then:
properties:
interrupts:
--
2.35.1
The SA8540P platform has five PCIe controllers: two 4-lane, two 2-lane
and one 1-lane.
Add a new "qcom,pcie-sa8540p" compatible string and reuse the 1.9.0 ops.
Note that like for SC8280XP, the SA8540P controllers need two or three
interconnect clocks to be enabled.
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
drivers/pci/controller/dwc/pcie-qcom.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 7a79bec81bba..699cd8b0f38e 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -1634,6 +1634,11 @@ static const struct qcom_pcie_cfg ipq4019_cfg = {
.ops = &ops_2_4_0,
};
+static const struct qcom_pcie_cfg sa8540p_cfg = {
+ .ops = &ops_1_9_0,
+ .has_ddrss_sf_tbu_clk = true,
+};
+
static const struct qcom_pcie_cfg sc8280xp_cfg = {
.ops = &ops_1_9_0,
.has_ddrss_sf_tbu_clk = true,
@@ -1803,6 +1808,7 @@ static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-ipq8074", .data = &ipq8074_cfg },
{ .compatible = "qcom,pcie-ipq4019", .data = &ipq4019_cfg },
{ .compatible = "qcom,pcie-qcs404", .data = &ipq4019_cfg },
+ { .compatible = "qcom,pcie-sa8540p", .data = &sa8540p_cfg },
{ .compatible = "qcom,pcie-sdm845", .data = &sdm845_cfg },
{ .compatible = "qcom,pcie-sm8150", .data = &sm8150_cfg },
{ .compatible = "qcom,pcie-sm8250", .data = &sm8250_cfg },
--
2.35.1
Explicitly enumerate the older platforms that have a single msi host
interrupt. This allows for adding further platforms with, for example,
four msi interrupts without resorting to nested conditionals.
Drop the redundant comment about older chipsets instead of moving it.
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 70984037df73..8142c891f18b 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -625,7 +625,6 @@ allOf:
- reset-names
# On newer chipsets support either 1 or 8 msi interrupts
- # On older chipsets it's always 1 msi interrupt
- if:
properties:
compatible:
@@ -660,7 +659,21 @@ allOf:
- const: msi5
- const: msi6
- const: msi7
- else:
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-apq8064
+ - qcom,pcie-apq8084
+ - qcom,pcie-ipq4019
+ - qcom,pcie-ipq6018
+ - qcom,pcie-ipq8064
+ - qcom,pcie-ipq8064-v2
+ - qcom,pcie-ipq8074
+ - qcom,pcie-qcs404
+ then:
properties:
interrupts:
maxItems: 1
--
2.35.1
Add the SC8280XP platform to the binding.
SC8280XP use four host interrupts for MSI routing so remove the obsolete
comment referring to newer chipsets supporting one or eight interrupts
(e.g. for backwards compatibility).
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Johan Hovold <[email protected]>
---
.../devicetree/bindings/pci/qcom,pcie.yaml | 50 ++++++++++++++++++-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
index 8142c891f18b..577d166a7476 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,pcie-qcs404
- qcom,pcie-sc7280
- qcom,pcie-sc8180x
+ - qcom,pcie-sc8280xp
- qcom,pcie-sdm845
- qcom,pcie-sm8150
- qcom,pcie-sm8250
@@ -181,6 +182,7 @@ allOf:
enum:
- qcom,pcie-sc7280
- qcom,pcie-sc8180x
+ - qcom,pcie-sc8280xp
- qcom,pcie-sm8250
- qcom,pcie-sm8450-pcie0
- qcom,pcie-sm8450-pcie1
@@ -596,6 +598,35 @@ allOf:
items:
- const: pci # PCIe core reset
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-sc8280xp
+ then:
+ properties:
+ clocks:
+ minItems: 8
+ maxItems: 9
+ clock-names:
+ minItems: 8
+ items:
+ - const: aux # Auxiliary clock
+ - const: cfg # Configuration clock
+ - const: bus_master # Master AXI clock
+ - const: bus_slave # Slave AXI clock
+ - const: slave_q2a # Slave Q2A clock
+ - const: ddrss_sf_tbu # PCIe SF TBU clock
+ - const: noc_aggr_4 # NoC aggregate 4 clock
+ - const: noc_aggr_south_sf # NoC aggregate South SF clock
+ - const: cnoc_qx # Configuration NoC QX clock
+ resets:
+ maxItems: 1
+ reset-names:
+ items:
+ - const: pci # PCIe core reset
+
- if:
not:
properties:
@@ -624,7 +655,6 @@ allOf:
- resets
- reset-names
- # On newer chipsets support either 1 or 8 msi interrupts
- if:
properties:
compatible:
@@ -660,6 +690,24 @@ allOf:
- const: msi6
- const: msi7
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,pcie-sc8280xp
+ then:
+ properties:
+ interrupts:
+ minItems: 4
+ maxItems: 4
+ interrupt-names:
+ items:
+ - const: msi0
+ - const: msi1
+ - const: msi2
+ - const: msi3
+
- if:
properties:
compatible:
--
2.35.1
On 14/07/2022 09:13, Johan Hovold wrote:
> Explicitly enumerate the older platforms that have a single msi host
> interrupt. This allows for adding further platforms with, for example,
> four msi interrupts without resorting to nested conditionals.
>
> Drop the redundant comment about older chipsets instead of moving it.
>
> Reviewed-by: Manivannan Sadhasivam <[email protected]>
> Signed-off-by: Johan Hovold <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Thu, Jul 14, 2022 at 09:13:45AM +0200, Johan Hovold wrote:
> The SA8540P platform has five PCIe controllers: two 4-lane, two 2-lane
> and one 1-lane.
>
> Add a new "qcom,pcie-sa8540p" compatible string and reuse the 1.9.0 ops.
>
> Note that like for SC8280XP, the SA8540P controllers need two or three
> interconnect clocks to be enabled.
>
> Reviewed-by: Rob Herring <[email protected]>
> Reviewed-by: Manivannan Sadhasivam <[email protected]>
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Brian Masney <[email protected]>
On Thu, Jul 14, 2022 at 09:13:46AM +0200, Johan Hovold wrote:
> The kernel is not a devicetree validator and does not need to re-encode
> information which is already available in the devicetree.
>
> This is specifically true for the optional PCIe clocks, some of which
> are really interconnect clocks.
>
> Treat also the 2.7.0 optional clocks as truly optional instead of
> maintaining a list of clocks per compatible (including two compatible
> strings for the two identical controllers on sm8450) just to validate
> the devicetree.
>
> Reviewed-by: Rob Herring <[email protected]>
> Reviewed-by: Manivannan Sadhasivam <[email protected]>
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Brian Masney <[email protected]>
On Thu, Jul 14, 2022 at 09:13:43AM +0200, Johan Hovold wrote:
> SA8540P is a new platform related to SC8280XP but which uses a single
> host interrupt for MSI routing.
>
> Acked-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Johan Hovold <[email protected]>
Reviewed-by: Brian Masney <[email protected]>
On Thu, Jul 14, 2022 at 09:13:40AM +0200, Johan Hovold wrote:
> This series adds support for the PCIe controllers found on SC8280XP and
> SA8540P.
These look fairly straightforward, and I don't mind doing minor tweaks
and conflict resolution, but given that we've got four or five cooks
in the qcom kitchen, I'm looking for an ack from Stan before spending
too much time on this.
> Included are also three patches that clean up the way the driver handles
> different IP revisions (e.g. by modelling optional clocks as being truly
> optional).
>
> These patches depend on the recently merged (but currently held off?)
> PIPE clock series:
>
> https://lore.kernel.org/all/[email protected]/
As far as I know it's on pci/ctrl/qcom [1], in -next, and ready to go.
It's based on Bjorn A's immutable branch [2].
> as well as the about-to-be-merged MSI series (v17):
>
> https://lore.kernel.org/all/[email protected]/
>
> Note that the final patch in the PIPE clock series is currently missing
> from the pci/ctrl/qcom-pending branch:
>
> https://lore.kernel.org/all/[email protected]/
I think I fixed that, let me know if not; see [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git/log/?h=839fbdee4c08
[2] https://lore.kernel.org/linux-pci/[email protected]/
> Changes in v2
> - drop the two DT schema fixes which have been applied by Bjorn H and
> squashed into the MSI v17 series by Dmitry, respectively
> - rebase on pci/ctrl/qcom-pending (2022-07-14)
> - fix compatible sort order (Krzysztof)
> - amend commit message for first patch to clarify motivation
> (Krzysztof)
> - add acks and reviewed-by tags from Dmitry, Krzysztof, Mani and Rob
>
>
> Johan Hovold (8):
> dt-bindings: PCI: qcom: Enumerate platforms with single msi interrupt
> dt-bindings: PCI: qcom: Add SC8280XP to binding
> dt-bindings: PCI: qcom: Add SA8540P to binding
> PCI: qcom: Add support for SC8280XP
> PCI: qcom: Add support for SA8540P
> PCI: qcom: Make all optional clocks optional
> PCI: qcom: Clean up IP configurations
> PCI: qcom: Sort device-id table
>
> .../devicetree/bindings/pci/qcom,pcie.yaml | 70 +++++++++-
> drivers/pci/controller/dwc/pcie-qcom.c | 121 +++++++-----------
> 2 files changed, 114 insertions(+), 77 deletions(-)
>
> --
> 2.35.1
>
Hi Johan,
Thank you for your work, especially for for the last three patches ;-)
On 7/14/22 10:13, Johan Hovold wrote:
> This series adds support for the PCIe controllers found on SC8280XP and
> SA8540P.
>
> Included are also three patches that clean up the way the driver handles
> different IP revisions (e.g. by modelling optional clocks as being truly
> optional).
>
> These patches depend on the recently merged (but currently held off?)
> PIPE clock series:
>
> https://lore.kernel.org/all/[email protected]/
>
> as well as the about-to-be-merged MSI series (v17):
>
> https://lore.kernel.org/all/[email protected]/
>
> Note that the final patch in the PIPE clock series is currently missing
> from the pci/ctrl/qcom-pending branch:
>
> https://lore.kernel.org/all/[email protected]/
>
> Johan
>
>
> Changes in v2
> - drop the two DT schema fixes which have been applied by Bjorn H and
> squashed into the MSI v17 series by Dmitry, respectively
> - rebase on pci/ctrl/qcom-pending (2022-07-14)
> - fix compatible sort order (Krzysztof)
> - amend commit message for first patch to clarify motivation
> (Krzysztof)
> - add acks and reviewed-by tags from Dmitry, Krzysztof, Mani and Rob
>
>
> Johan Hovold (8):
> dt-bindings: PCI: qcom: Enumerate platforms with single msi interrupt
> dt-bindings: PCI: qcom: Add SC8280XP to binding
> dt-bindings: PCI: qcom: Add SA8540P to binding
> PCI: qcom: Add support for SC8280XP
> PCI: qcom: Add support for SA8540P
> PCI: qcom: Make all optional clocks optional
> PCI: qcom: Clean up IP configurations
> PCI: qcom: Sort device-id table
>
> .../devicetree/bindings/pci/qcom,pcie.yaml | 70 +++++++++-
> drivers/pci/controller/dwc/pcie-qcom.c | 121 +++++++-----------
> 2 files changed, 114 insertions(+), 77 deletions(-)
>
For the whole set:
Acked-by: Stanimir Varbanov <[email protected]>
--
regards,
Stan
On Fri, Jul 15, 2022 at 05:37:28PM -0500, Bjorn Helgaas wrote:
> On Thu, Jul 14, 2022 at 09:13:40AM +0200, Johan Hovold wrote:
> > This series adds support for the PCIe controllers found on SC8280XP and
> > SA8540P.
>
> These look fairly straightforward, and I don't mind doing minor tweaks
> and conflict resolution, but given that we've got four or five cooks
> in the qcom kitchen, I'm looking for an ack from Stan before spending
> too much time on this.
Sounds good. Stan's acked the series now too.
Since I rebased v2 on qcom-pending (and added the missing pipe clock
patch), there shouldn't be any conflicts and the only fixup I'm aware of
is the sort order of the "qcom,pcie-ipq4019" entry in patch 8/8.
Let me know if you prefer I fix that in a v3 otherwise these can be
applied once the MSI series has been merged.
I saw Stan acking the binding in that series, not sure if the intention
was to ack the whole series?
https://lore.kernel.org/all/[email protected]/
> > Included are also three patches that clean up the way the driver handles
> > different IP revisions (e.g. by modelling optional clocks as being truly
> > optional).
> >
> > These patches depend on the recently merged (but currently held off?)
> > PIPE clock series:
> >
> > https://lore.kernel.org/all/[email protected]/
>
> As far as I know it's on pci/ctrl/qcom [1], in -next, and ready to go.
> It's based on Bjorn A's immutable branch [2].
Right.
> > as well as the about-to-be-merged MSI series (v17):
> >
> > https://lore.kernel.org/all/[email protected]/
> >
> > Note that the final patch in the PIPE clock series is currently missing
> > from the pci/ctrl/qcom-pending branch:
> >
> > https://lore.kernel.org/all/[email protected]/
>
> I think I fixed that, let me know if not; see [1].
>
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git/log/?h=839fbdee4c08
> [2] https://lore.kernel.org/linux-pci/[email protected]/
It appears to have been fixed in your branch now, but it hasn't yet made
it into -next.
> > Changes in v2
> > - drop the two DT schema fixes which have been applied by Bjorn H and
> > squashed into the MSI v17 series by Dmitry, respectively
> > - rebase on pci/ctrl/qcom-pending (2022-07-14)
> > - fix compatible sort order (Krzysztof)
> > - amend commit message for first patch to clarify motivation
> > (Krzysztof)
> > - add acks and reviewed-by tags from Dmitry, Krzysztof, Mani and Rob
> >
> >
> > Johan Hovold (8):
> > dt-bindings: PCI: qcom: Enumerate platforms with single msi interrupt
> > dt-bindings: PCI: qcom: Add SC8280XP to binding
> > dt-bindings: PCI: qcom: Add SA8540P to binding
> > PCI: qcom: Add support for SC8280XP
> > PCI: qcom: Add support for SA8540P
> > PCI: qcom: Make all optional clocks optional
> > PCI: qcom: Clean up IP configurations
> > PCI: qcom: Sort device-id table
Johan
On Mon, Jul 18, 2022 at 10:49:40AM +0300, Stanimir Varbanov wrote:
> Hi Johan,
>
> Thank you for your work, especially for for the last three patches ;-)
>
> On 7/14/22 10:13, Johan Hovold wrote:
> > This series adds support for the PCIe controllers found on SC8280XP and
> > SA8540P.
> >
> > Included are also three patches that clean up the way the driver handles
> > different IP revisions (e.g. by modelling optional clocks as being truly
> > optional).
> For the whole set:
>
> Acked-by: Stanimir Varbanov <[email protected]>
Thanks for the ack.
Could you take a look at Dmitry's MSI series that this series depends on
as well?
I saw you acking the binding, but not the rest of the series it seems:
https://lore.kernel.org/all/[email protected]/
Johan
On 14/07/2022 10:13, Johan Hovold wrote:
> The kernel is not a devicetree validator and does not need to re-encode
> information which is already available in the devicetree.
>
> This is specifically true for the optional PCIe clocks, some of which
> are really interconnect clocks.
>
> Treat also the 2.7.0 optional clocks as truly optional instead of
> maintaining a list of clocks per compatible (including two compatible
> strings for the two identical controllers on sm8450) just to validate
> the devicetree.
>
> Reviewed-by: Rob Herring <[email protected]>
> Reviewed-by: Manivannan Sadhasivam <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
> Signed-off-by: Johan Hovold <[email protected]>--
With best wishes
Dmitry
On Mon, Jul 18, 2022 at 12:18:11PM +0200, Johan Hovold wrote:
> On Mon, Jul 18, 2022 at 10:49:40AM +0300, Stanimir Varbanov wrote:
> > Hi Johan,
> >
> > Thank you for your work, especially for for the last three patches ;-)
> >
> > On 7/14/22 10:13, Johan Hovold wrote:
> > > This series adds support for the PCIe controllers found on SC8280XP and
> > > SA8540P.
> > >
> > > Included are also three patches that clean up the way the driver handles
> > > different IP revisions (e.g. by modelling optional clocks as being truly
> > > optional).
>
> > For the whole set:
> >
> > Acked-by: Stanimir Varbanov <[email protected]>
>
> Thanks for the ack.
>
> Could you take a look at Dmitry's MSI series that this series depends on
> as well?
>
> I saw you acking the binding, but not the rest of the series it seems:
>
> https://lore.kernel.org/all/[email protected]/
Of course you only acked the single patched that touched the Qualcomm
driver. Sorry about the noise.
Johan
On Thu, 14 Jul 2022 09:13:40 +0200, Johan Hovold wrote:
> This series adds support for the PCIe controllers found on SC8280XP and
> SA8540P.
>
> Included are also three patches that clean up the way the driver handles
> different IP revisions (e.g. by modelling optional clocks as being truly
> optional).
>
> [...]
I tweaked commits as-per thread discussion (please check them, I had
to fix minor rebase conflicts) and applied to pci/qcom, thanks!
[1/8] dt-bindings: PCI: qcom: Enumerate platforms with single msi interrupt
https://git.kernel.org/lpieralisi/pci/c/a871c90977a4
[2/8] dt-bindings: PCI: qcom: Add SC8280XP to binding
https://git.kernel.org/lpieralisi/pci/c/0122ab0115a9
[3/8] dt-bindings: PCI: qcom: Add SA8540P to binding
https://git.kernel.org/lpieralisi/pci/c/fe9681a74d04
[4/8] PCI: qcom: Add support for SC8280XP
https://git.kernel.org/lpieralisi/pci/c/e37d881f9f3a
[5/8] PCI: qcom: Add support for SA8540P
https://git.kernel.org/lpieralisi/pci/c/b325dc5f9d39
[6/8] PCI: qcom: Make all optional clocks optional
https://git.kernel.org/lpieralisi/pci/c/4c4ef240b58a
[7/8] PCI: qcom: Clean up IP configurations
https://git.kernel.org/lpieralisi/pci/c/4daa5e24813e
[8/8] PCI: qcom: Sort device-id table
https://git.kernel.org/lpieralisi/pci/c/46bafd187104
Thanks,
Lorenzo
On Fri, Aug 19, 2022 at 10:40:49AM +0200, Lorenzo Pieralisi wrote:
> On Thu, 14 Jul 2022 09:13:40 +0200, Johan Hovold wrote:
> > This series adds support for the PCIe controllers found on SC8280XP and
> > SA8540P.
> >
> > Included are also three patches that clean up the way the driver handles
> > different IP revisions (e.g. by modelling optional clocks as being truly
> > optional).
> >
> > [...]
>
> I tweaked commits as-per thread discussion (please check them, I had
> to fix minor rebase conflicts) and applied to pci/qcom, thanks!
Not sure if you missed that Stanimir had acked the whole series:
https://lore.kernel.org/all/[email protected]/
Looks good, otherwise. Thanks!
Johan