From: Aswath Govindraju <[email protected]>
Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, eDP and USB.
Cc: Vignesh Raghavendra <[email protected]>
Cc: Nishanth Menon <[email protected]>
Acked-by: Matt Ranostay <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 70 ++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index f7e359da8690..f1e02d896168 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -5,6 +5,13 @@
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
+/ {
+ serdes_refclk: serdes-refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -33,6 +40,13 @@ scm_conf: scm-conf@104000 {
#size-cells = <1>;
ranges = <0x00 0x00 0x00104000 0x18000>;
+ serdes_ln_ctrl: mux-controller@80 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
+ <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
+ };
+
usb_serdes_mux: mux-controller@0 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
@@ -728,6 +742,62 @@ usb0: usb@6000000 {
};
};
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,j721e-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ ranges = <0x5060000 0x0 0x5060000 0x10000>;
+
+ assigned-clocks = <&k3_clks 365 3>;
+ assigned-clock-parents = <&k3_clks 365 7>;
+
+ wiz0_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-output-names = "wiz0_pll0_refclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 365 3>;
+ };
+
+ wiz0_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-output-names = "wiz0_pll1_refclk";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 365 3>;
+ };
+
+ wiz0_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-output-names = "wiz0_refclk_dig";
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 365 3>;
+ };
+
+ wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
+ clocks = <&wiz0_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&wiz0_pll0_refclk>;
+ clock-names = "refclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.36.1
On 10/08/22 15:09, Matt Ranostay wrote:
> From: Aswath Govindraju <[email protected]>
>
> Add dt node for the single instance of WIZ (SERDES wrapper) and
> SERDES module shared by PCIe, eDP and USB.
>
> Cc: Vignesh Raghavendra <[email protected]>
> Cc: Nishanth Menon <[email protected]>
> Acked-by: Matt Ranostay <[email protected]>
> Signed-off-by: Aswath Govindraju <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 70 ++++++++++++++++++++++
> 1 file changed, 70 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index f7e359da8690..f1e02d896168 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -5,6 +5,13 @@
> * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> +/ {
> + serdes_refclk: serdes-refclk {
clk-X
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + };
> +};
> +
> &cbass_main {
> msmc_ram: sram@70000000 {
> compatible = "mmio-sram";
> @@ -33,6 +40,13 @@ scm_conf: scm-conf@104000 {
> #size-cells = <1>;
> ranges = <0x00 0x00 0x00104000 0x18000>;
>
> + serdes_ln_ctrl: mux-controller@80 {
mux-controller-X
> + compatible = "mmio-mux";
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
> + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
> + };
> +
> usb_serdes_mux: mux-controller@0 {
> compatible = "mmio-mux";
> #mux-control-cells = <1>;
> @@ -728,6 +742,62 @@ usb0: usb@6000000 {
> };
> };
>
> + serdes_wiz0: wiz@5060000 {
> + compatible = "ti,j721e-wiz-10g";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> + num-lanes = <4>;
> + #reset-cells = <1>;
> + ranges = <0x5060000 0x0 0x5060000 0x10000>;
> +
> + assigned-clocks = <&k3_clks 365 3>;
> + assigned-clock-parents = <&k3_clks 365 7>;
> +
> + wiz0_pll0_refclk: pll0-refclk {
please use generic node name clk-X here and elsewhere in the patch
> + clocks = <&k3_clks 365 3>, <&serdes_refclk>;
> + clock-output-names = "wiz0_pll0_refclk";
> + #clock-cells = <0>;
> + assigned-clocks = <&wiz0_pll0_refclk>;
> + assigned-clock-parents = <&k3_clks 365 3>;
> + };
> +
> + wiz0_pll1_refclk: pll1-refclk {
ditto
> + clocks = <&k3_clks 365 3>, <&serdes_refclk>;
> + clock-output-names = "wiz0_pll1_refclk";
> + #clock-cells = <0>;
> + assigned-clocks = <&wiz0_pll1_refclk>;
> + assigned-clock-parents = <&k3_clks 365 3>;
> + };
> +
> + wiz0_refclk_dig: refclk-dig {
ditto
> + clocks = <&k3_clks 365 3>, <&serdes_refclk>;
> + clock-output-names = "wiz0_refclk_dig";
> + #clock-cells = <0>;
> + assigned-clocks = <&wiz0_refclk_dig>;
> + assigned-clock-parents = <&k3_clks 365 3>;
> + };
> +
> + wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
ditto
> + clocks = <&wiz0_refclk_dig>;
> + #clock-cells = <0>;
> + };
> +
> + serdes0: serdes@5060000 {
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x05060000 0x00010000>;
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz0 0>;
> + reset-names = "torrent_reset";
> + clocks = <&wiz0_pll0_refclk>;
> + clock-names = "refclk";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> main_mcan0: can@2701000 {
> compatible = "bosch,m_can";
> reg = <0x00 0x02701000 0x00 0x200>,
--
Regards
Vignesh
On Thu, Sep 01, 2022 at 02:15:28PM +0530, Vignesh Raghavendra wrote:
>
>
> On 10/08/22 15:09, Matt Ranostay wrote:
> > From: Aswath Govindraju <[email protected]>
> >
> > Add dt node for the single instance of WIZ (SERDES wrapper) and
> > SERDES module shared by PCIe, eDP and USB.
> >
> > Cc: Vignesh Raghavendra <[email protected]>
> > Cc: Nishanth Menon <[email protected]>
> > Acked-by: Matt Ranostay <[email protected]>
> > Signed-off-by: Aswath Govindraju <[email protected]>
> > ---
> > arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 70 ++++++++++++++++++++++
> > 1 file changed, 70 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> > index f7e359da8690..f1e02d896168 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> > @@ -5,6 +5,13 @@
> > * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
> > */
> >
> > +/ {
> > + serdes_refclk: serdes-refclk {
>
> clk-X
>
So something like 'serdes_refclk: clock-cmnrefclk' would seem to match the current
naming style of other K3 platforms (albeit except j7200).
> > + #clock-cells = <0>;
> > + compatible = "fixed-clock";
> > + };
> > +};
> > +
> > &cbass_main {
> > msmc_ram: sram@70000000 {
> > compatible = "mmio-sram";
> > @@ -33,6 +40,13 @@ scm_conf: scm-conf@104000 {
> > #size-cells = <1>;
> > ranges = <0x00 0x00 0x00104000 0x18000>;
> >
> > + serdes_ln_ctrl: mux-controller@80 {
>
> mux-controller-X
>
80 is the index into the mmio region. So should it still have @ for the node
name?
Also this is how the rest of the K3 platforms reference the mux controller.
> > + compatible = "mmio-mux";
> > + #mux-control-cells = <1>;
> > + mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
> > + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
> > + };
> > +
> > usb_serdes_mux: mux-controller@0 {
> > compatible = "mmio-mux";
> > #mux-control-cells = <1>;
> > @@ -728,6 +742,62 @@ usb0: usb@6000000 {
> > };
> > };
> >
> > + serdes_wiz0: wiz@5060000 {
> > + compatible = "ti,j721e-wiz-10g";
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
> > + clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
> > + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> > + num-lanes = <4>;
> > + #reset-cells = <1>;
> > + ranges = <0x5060000 0x0 0x5060000 0x10000>;
> > +
> > + assigned-clocks = <&k3_clks 365 3>;
> > + assigned-clock-parents = <&k3_clks 365 7>;
> > +
> > + wiz0_pll0_refclk: pll0-refclk {
>
> please use generic node name clk-X here and elsewhere in the patch
So something like 'wiz0_pll0_refclk: clk-refpll0'?
- Matt
>
> > + clocks = <&k3_clks 365 3>, <&serdes_refclk>;
> > + clock-output-names = "wiz0_pll0_refclk";
> > + #clock-cells = <0>;
> > + assigned-clocks = <&wiz0_pll0_refclk>;
> > + assigned-clock-parents = <&k3_clks 365 3>;
> > + };
> > +
> > + wiz0_pll1_refclk: pll1-refclk {
>
> ditto
>
> > + clocks = <&k3_clks 365 3>, <&serdes_refclk>;
> > + clock-output-names = "wiz0_pll1_refclk";
> > + #clock-cells = <0>;
> > + assigned-clocks = <&wiz0_pll1_refclk>;
> > + assigned-clock-parents = <&k3_clks 365 3>;
> > + };
> > +
> > + wiz0_refclk_dig: refclk-dig {
>
> ditto
>
> > + clocks = <&k3_clks 365 3>, <&serdes_refclk>;
> > + clock-output-names = "wiz0_refclk_dig";
> > + #clock-cells = <0>;
> > + assigned-clocks = <&wiz0_refclk_dig>;
> > + assigned-clock-parents = <&k3_clks 365 3>;
> > + };
> > +
> > + wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
>
> ditto
>
> > + clocks = <&wiz0_refclk_dig>;
> > + #clock-cells = <0>;
> > + };
> > +
> > + serdes0: serdes@5060000 {
> > + compatible = "ti,j721e-serdes-10g";
> > + reg = <0x05060000 0x00010000>;
> > + reg-names = "torrent_phy";
> > + resets = <&serdes_wiz0 0>;
> > + reset-names = "torrent_reset";
> > + clocks = <&wiz0_pll0_refclk>;
> > + clock-names = "refclk";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
> > + };
> > +
> > main_mcan0: can@2701000 {
> > compatible = "bosch,m_can";
> > reg = <0x00 0x02701000 0x00 0x200>,
>
> --
> Regards
> Vignesh
On 02/09/22 05:17, Matt Ranostay wrote:
> On Thu, Sep 01, 2022 at 02:15:28PM +0530, Vignesh Raghavendra wrote:
>>
>>
>> On 10/08/22 15:09, Matt Ranostay wrote:
>>> From: Aswath Govindraju <[email protected]>
>>>
>>> Add dt node for the single instance of WIZ (SERDES wrapper) and
>>> SERDES module shared by PCIe, eDP and USB.
>>>
>>> Cc: Vignesh Raghavendra <[email protected]>
>>> Cc: Nishanth Menon <[email protected]>
>>> Acked-by: Matt Ranostay <[email protected]>
>>> Signed-off-by: Aswath Govindraju <[email protected]>
>>> ---
>>> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 70 ++++++++++++++++++++++
>>> 1 file changed, 70 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>>> index f7e359da8690..f1e02d896168 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
>>> @@ -5,6 +5,13 @@
>>> * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
>>> */
>>>
>>> +/ {
>>> + serdes_refclk: serdes-refclk {
>>
>> clk-X
>>
>
Sorry for the confusion, I meant clock-<abc>. DT specification says all
clock nodes should follow above naming convention
> So something like 'serdes_refclk: clock-cmnrefclk' would seem to match the current
> naming style of other K3 platforms (albeit except j7200).
>
Make sense...
>>> + #clock-cells = <0>;
>>> + compatible = "fixed-clock";
>>> + };
>>> +};
>>> +
>>> &cbass_main {
>>> msmc_ram: sram@70000000 {
>>> compatible = "mmio-sram";
>>> @@ -33,6 +40,13 @@ scm_conf: scm-conf@104000 {
>>> #size-cells = <1>;
>>> ranges = <0x00 0x00 0x00104000 0x18000>;
>>>
>>> + serdes_ln_ctrl: mux-controller@80 {
>>
>> mux-controller-X
>>
>
> 80 is the index into the mmio region. So should it still have @ for the node
> name?
>
@addr can only be used with nodes that have reg property. And since
there is no reg here -> would follow mux-controller-<abc> convention.
> Also this is how the rest of the K3 platforms reference the mux controller.
We need to fix other dtsi files to drop @addr part as they are now
falling make dtbs_check
>
>>> + compatible = "mmio-mux";
>>> + #mux-control-cells = <1>;
>>> + mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
>>> + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
>>> + };
>>> +
>>> usb_serdes_mux: mux-controller@0 {
>>> compatible = "mmio-mux";
>>> #mux-control-cells = <1>;
>>> @@ -728,6 +742,62 @@ usb0: usb@6000000 {
>>> };
>>> };
>>>
>>> + serdes_wiz0: wiz@5060000 {
>>> + compatible = "ti,j721e-wiz-10g";
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> + power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
>>> + clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
>>> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
>>> + num-lanes = <4>;
>>> + #reset-cells = <1>;
>>> + ranges = <0x5060000 0x0 0x5060000 0x10000>;
>>> +
>>> + assigned-clocks = <&k3_clks 365 3>;
>>> + assigned-clock-parents = <&k3_clks 365 7>;
>>> +
>>> + wiz0_pll0_refclk: pll0-refclk {
>>
>> please use generic node name clk-X here and elsewhere in the patch
>
> So something like 'wiz0_pll0_refclk: clk-refpll0'?
Sorry, clock-refpll0 perhaps
[...]
--
Regards
Vignesh