From: Lad Prabhakar <[email protected]>
Hi All,
The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
entry-class social infrastructure gateway control and industrial gateway
control.
This patch series adds initial SoC DTSi support for Renesas RZ/Five
(R9A07G043) SoC and updates the bindings for the same. Below is the list
of IP blocks added in the initial SoC DTSI which can be used to boot via
initramfs on RZ/Five SMARC EVK:
- AX45MP CPU
- CPG
- PINCTRL
- PLIC
- SCIF0
- SYSC
Useful links:
-------------
[0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
[1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
Patch series depends on the below (which are already in -next apart from the last one):
--------------------------------------------------
[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/[email protected]/
[1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/[email protected]/
[2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/[email protected]/
v3 -> v4:
-------
* Rebased patches on -next
* Included RB tags
* Fixed review comments pointed by Conor and Geert
v3: https://lore.kernel.org/lkml/[email protected]/
v2: https://lore.kernel.org/all/[email protected]/
v1: https://lore.kernel.org/lkml/[email protected]/
Below are the logs from RZ/Five SMARC EVK:
------------------------------------------
/ # uname -ra
Linux (none) 6.0.0-rc6-next-20220920-00025-gc002c40ce550-dirty #136 SMP Tue Sep 20 13:47:31 BST 2022 riscv64 GNU/Linux
/ # cat /proc/cpuinfo
processor : 0
hart : 0
isa : rv64imafdc
mmu : sv39
uarch : andestech,ax45mp
mvendorid : 0x31e
marchid : 0x8000000000008a45
mimpid : 0x500
/ # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/
soc0/$i; done
machine: Renesas SMARC EVK based on r9a07g043f01
family: RZ/Five
soc_id: r9a07g043
revision: 0
/ #
/ # cat /proc/interrupts
CPU0
1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err
2: 33 SiFive PLIC 414 Level 1004b800.serial:rx full
3: 919 SiFive PLIC 415 Level 1004b800.serial:tx empty
4: 0 SiFive PLIC 413 Level 1004b800.serial:break
5: 44106 RISC-V INTC 5 Edge riscv-timer
6: 62 SiFive PLIC 416 Level 1004b800.serial:rx ready
IPI0: 0 Rescheduling interrupts
IPI1: 0 Function call interrupts
IPI2: 0 CPU stop interrupts
IPI3: 0 IRQ work interrupts
IPI4: 0 Timer broadcast interrupts
/ #
/ # cat /proc/meminfo
MemTotal: 882308 kB
MemFree: 861440 kB
MemAvailable: 859188 kB
Buffers: 0 kB
Cached: 1796 kB
SwapCached: 0 kB
Active: 0 kB
Inactive: 84 kB
Active(anon): 0 kB
Inactive(anon): 84 kB
Active(file): 0 kB
Inactive(file): 0 kB
Unevictable: 1796 kB
Mlocked: 0 kB
SwapTotal: 0 kB
SwapFree: 0 kB
Dirty: 0 kB
Writeback: 0 kB
AnonPages: 120 kB
Mapped: 1200 kB
Shmem: 0 kB
KReclaimable: 6732 kB
Slab: 12088 kB
SReclaimable: 6732 kB
SUnreclaim: 5356 kB
KernelStack: 636 kB
PageTables: 32 kB
NFS_Unstable: 0 kB
Bounce: 0 kB
WritebackTmp: 0 kB
CommitLimit: 441152 kB
Committed_AS: 592 kB
VmallocTotal: 67108864 kB
VmallocUsed: 840 kB
VmallocChunk: 0 kB
Percpu: 84 kB
HugePages_Total: 0
HugePages_Free: 0
HugePages_Rsvd: 0
HugePages_Surp: 0
Hugepagesize: 2048 kB
Hugetlb: 0 kB
/ #
-------------------
Lad Prabhakar (10):
dt-bindings: soc: renesas: Move renesas.yaml from arm to soc
dt-bindings: riscv: Sort the CPU core list alphabetically
dt-bindings: riscv: Add Andes AX45MP core to the list
dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC
riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
riscv: dts: r9a07g043: Add placeholder nodes
riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
MAINTAINERS: Add entry for Renesas RISC-V architecture
riscv: configs: defconfig: Enable Renesas RZ/Five SoC
.../devicetree/bindings/riscv/cpus.yaml | 11 +-
.../{arm => soc/renesas}/renesas.yaml | 5 +-
MAINTAINERS | 4 +-
arch/riscv/Kconfig.socs | 5 +
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/Makefile | 2 +
arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 270 ++++++++++++++++++
.../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++
.../boot/dts/renesas/rzfive-smarc-som.dtsi | 19 ++
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 15 +
arch/riscv/configs/defconfig | 3 +
11 files changed, 353 insertions(+), 9 deletions(-)
rename Documentation/devicetree/bindings/{arm => soc/renesas}/renesas.yaml (98%)
create mode 100644 arch/riscv/boot/dts/renesas/Makefile
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
--
2.25.1
From: Lad Prabhakar <[email protected]>
Sort the CPU cores list alphabetically for maintenance.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
---
v3 -> v4
* Included RB tag from Heiko
v2 -> v3
* Included RB tag from Geert
v1 -> v2
* Included RB tag from Krzysztof
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 873dd12f6e89..2a1c5ae5b0aa 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -27,17 +27,17 @@ properties:
oneOf:
- items:
- enum:
- - sifive,rocket0
+ - canaan,k210
- sifive,bullet0
- sifive,e5
- sifive,e7
- sifive,e71
- - sifive,u74-mc
- - sifive,u54
- - sifive,u74
+ - sifive,rocket0
- sifive,u5
+ - sifive,u54
- sifive,u7
- - canaan,k210
+ - sifive,u74
+ - sifive,u74-mc
- const: riscv
- items:
- enum:
--
2.25.1
From: Lad Prabhakar <[email protected]>
Enable Renesas RZ/Five SoC config in defconfig. It allows the default
upstream kernel to boot on RZ/Five SMARC EVK board.
Alongside enable SERIAL_SH_SCI config so that the serial driver used by
RZ/Five SoC is built-in.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
---
v3 -> v4
* Explicitly enabled ARCH_R9A07G043 config (note I have restored the RB
tags with this change)
* Used riscv instead of RISC-V in subject line
v2 -> v3
* Included RB tags
* Updated commit description
v1 -> v2
* New patch
---
arch/riscv/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 05fd5fcf24f9..97fba7884d7a 100644
--- a/arch/riscv/configs/defconfig
+++ b/arch/riscv/configs/defconfig
@@ -29,6 +29,8 @@ CONFIG_SOC_MICROCHIP_POLARFIRE=y
CONFIG_SOC_SIFIVE=y
CONFIG_SOC_STARFIVE=y
CONFIG_SOC_VIRT=y
+CONFIG_ARCH_RENESAS=y
+CONFIG_ARCH_R9A07G043=y
CONFIG_SMP=y
CONFIG_HOTPLUG_CPU=y
CONFIG_PM=y
@@ -123,6 +125,7 @@ CONFIG_INPUT_MOUSEDEV=y
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SH_SCI=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_VIRTIO=y
--
2.25.1
From: Lad Prabhakar <[email protected]>
Enable the minimal blocks required for booting the Renesas RZ/Five
SMARC EVK with initramfs.
Below are the which are enabled:
- CPG
- CPU0
- DDR (memory regions)
- PINCTRL
- PLIC
- SCIF0
As we are reusing the RZ/G2UL SMARC SoM [0] and carrier [1] board DTSIs
which enables almost all the blocks supported by the RZ/G2UL SoC and
whereas on RZ/Five SoC we will be gradually adding the blocks hence the
aliases for ETH and I2C are deleted as support for these blocks is not
yet enabled on RZ/Five SoC.
[0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
[1] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
Signed-off-by: Lad Prabhakar <[email protected]>
---
v3 -> v4
* Dropped deleting place holder nodes
* Updated SW1 settings comment
* Update commit message
v2 -> v3
* Dropped RB tags from Conor and Geert
* Now re-using the SoM and carrier board DTS/I from RZ/G2UL
v1 -> v2
* New patch
---
arch/riscv/boot/dts/Makefile | 1 +
arch/riscv/boot/dts/renesas/Makefile | 2 ++
.../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 +++++++++++++++++++
.../boot/dts/renesas/rzfive-smarc-som.dtsi | 19 +++++++++++++
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 15 +++++++++++
5 files changed, 64 insertions(+)
create mode 100644 arch/riscv/boot/dts/renesas/Makefile
create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index ff174996cdfd..b0ff5fbabb0c 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -3,5 +3,6 @@ subdir-y += sifive
subdir-y += starfive
subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
subdir-y += microchip
+subdir-y += renesas
obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y))
diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile
new file mode 100644
index 000000000000..2d3f5751a649
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb
diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
new file mode 100644
index 000000000000..487d0d5e6d2e
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+
+/*
+ * DIP-Switch SW1 setting
+ * 1 : High; 0: Low
+ * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
+ * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
+ * Please change below macros according to SW1 setting on the SoM
+ */
+#define SW_SW0_DEV_SEL 1
+#define SW_ET0_EN_N 1
+
+#include "r9a07g043.dtsi"
+#include "rzfive-smarc-som.dtsi"
+#include "rzfive-smarc.dtsi"
+
+/ {
+ model = "Renesas SMARC EVK based on r9a07g043f01";
+ compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043";
+};
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
new file mode 100644
index 000000000000..d8168eb920ab
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK SOM
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
+
+/ {
+ aliases {
+ /delete-property/ ethernet0;
+ /delete-property/ ethernet1;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ };
+};
diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
new file mode 100644
index 000000000000..6f44a6946897
--- /dev/null
+++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the RZ/Five SMARC EVK carrier board
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ */
+
+#include <arm64/renesas/rzg2ul-smarc.dtsi>
+
+/ {
+ aliases {
+ /delete-property/ i2c0;
+ /delete-property/ i2c1;
+ };
+};
--
2.25.1
From: Lad Prabhakar <[email protected]>
Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs.
We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC.
Signed-off-by: Lad Prabhakar <[email protected]>
---
v3 -> v4
* Dropped SOC_RENESAS_RZFIVE config option
* Dropped explicitly selecting SOC_BUS/GPIOLIB/PINCTRL configs
under ARCH_RENESAS
* Updated commit message
* Dropped RB tag
* Used riscv instead of RISC-V in subject line
v2 -> v3
* Included RB tag from Geert
v1 -> v2
* No Change
---
arch/riscv/Kconfig.socs | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 69774bb362d6..5c420ed55ef9 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -80,4 +80,9 @@ config SOC_CANAAN_K210_DTB_SOURCE
endif # SOC_CANAAN
+config ARCH_RENESAS
+ bool "Renesas RISC-V SoCs"
+ help
+ This enables support for the RISC-V based Renesas SoCs.
+
endmenu # "SoC selection"
--
2.25.1
On Tue, Sep 20, 2022 at 07:48:59PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <[email protected]>
>
> Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs.
> We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> ---
> v3 -> v4
> * Dropped SOC_RENESAS_RZFIVE config option
> * Dropped explicitly selecting SOC_BUS/GPIOLIB/PINCTRL configs
> under ARCH_RENESAS
> * Updated commit message
> * Dropped RB tag
> * Used riscv instead of RISC-V in subject line
>
> v2 -> v3
> * Included RB tag from Geert
>
> v1 -> v2
> * No Change
> ---
> arch/riscv/Kconfig.socs | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> index 69774bb362d6..5c420ed55ef9 100644
> --- a/arch/riscv/Kconfig.socs
> +++ b/arch/riscv/Kconfig.socs
> @@ -80,4 +80,9 @@ config SOC_CANAAN_K210_DTB_SOURCE
>
> endif # SOC_CANAAN
I am not asking for a respin for this since no-one likely cares, but
I think a future goal would be to sort the file alphabetically. I'll
probably do it with the other 30-something patches my Kconfig.socs
rework series has got to now - but if you *are* respinning sorting
alphabetically (ignoring the CANAAN) would reduce future churn.
Thanks,
Conor.
>
> +config ARCH_RENESAS
> + bool "Renesas RISC-V SoCs"
> + help
> + This enables support for the RISC-V based Renesas SoCs.
> +
> endmenu # "SoC selection"
> --
> 2.25.1
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
From: Lad Prabhakar <[email protected]>
Document Renesas RZ/Five (R9A07G043) SoC.
More info about RZ/Five SoC:
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
Signed-off-by: Lad Prabhakar <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
---
v3 -> v4
* No change
v2 -> v3
* Dropped "(RISC-V core)" comment
* Included ACK and RB tags
v1 -> v2
* New patch
---
Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index 07c5e6ebd5a0..2789022b52eb 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -431,11 +431,12 @@ properties:
- renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
- const: renesas,r9a06g032
- - description: RZ/G2UL (R9A07G043)
+ - description: RZ/Five and RZ/G2UL (R9A07G043)
items:
- enum:
- renesas,smarc-evk # SMARC EVK
- enum:
+ - renesas,r9a07g043f01 # RZ/Five
- renesas,r9a07g043u11 # RZ/G2UL Type-1
- renesas,r9a07g043u12 # RZ/G2UL Type-2
- const: renesas,r9a07g043
--
2.25.1
From: Lad Prabhakar <[email protected]>
Add RISC-V architecture as part of ARM/Renesas architecture, as they have
the same maintainers, use the same development collaboration
infrastructure, and share many files.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
---
v3 -> v4
* Included RB tag from Geert
v2 -> v3
* Merged as part of ARM
v1 -> v2
* New patch
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 48c5a152f743..fbf507cd3f41 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2671,7 +2671,7 @@ F: arch/arm/boot/dts/rtd*
F: arch/arm/mach-realtek/
F: arch/arm64/boot/dts/realtek/
-ARM/RENESAS ARCHITECTURE
+ARM/RISC-V/RENESAS ARCHITECTURE
M: Geert Uytterhoeven <[email protected]>
M: Magnus Damm <[email protected]>
L: [email protected]
@@ -2692,6 +2692,7 @@ F: arch/arm/configs/shmobile_defconfig
F: arch/arm/include/debug/renesas-scif.S
F: arch/arm/mach-shmobile/
F: arch/arm64/boot/dts/renesas/
+F: arch/riscv/boot/dts/renesas/
F: drivers/soc/renesas/
F: include/linux/soc/renesas/
--
2.25.1
Hey Prabhakar,
On Tue, Sep 20, 2022 at 07:48:54PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <[email protected]>
>
> Hi All,
>
> The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> entry-class social infrastructure gateway control and industrial gateway
> control.
>
> This patch series adds initial SoC DTSi support for Renesas RZ/Five
> (R9A07G043) SoC and updates the bindings for the same. Below is the list
> of IP blocks added in the initial SoC DTSI which can be used to boot via
> initramfs on RZ/Five SMARC EVK:
> - AX45MP CPU
> - CPG
> - PINCTRL
> - PLIC
> - SCIF0
> - SYSC
Ran into one complaint from dtbs_check:
arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c50200: '#phy-cells' is a required property
From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c70200: '#phy-cells' is a required property
From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
Other than that which should be a trivial fix the whole lot looks good
to me...
Reviewed-by: Conor Dooley <[email protected]>
Thanks,
Conor.
>
> Useful links:
> -------------
> [0] https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
> [1] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/
>
> Patch series depends on the below (which are already in -next apart from the last one):
> --------------------------------------------------
> [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/[email protected]/
> [1] https://patchwork.kernel.org/project/linux-renesas-soc/cover/[email protected]/
> [2] https://patchwork.kernel.org/project/linux-renesas-soc/patch/[email protected]/
>
> v3 -> v4:
> -------
> * Rebased patches on -next
> * Included RB tags
> * Fixed review comments pointed by Conor and Geert
>
> v3: https://lore.kernel.org/lkml/[email protected]/
> v2: https://lore.kernel.org/all/[email protected]/
> v1: https://lore.kernel.org/lkml/[email protected]/
>
> Below are the logs from RZ/Five SMARC EVK:
> ------------------------------------------
> / # uname -ra
> Linux (none) 6.0.0-rc6-next-20220920-00025-gc002c40ce550-dirty #136 SMP Tue Sep 20 13:47:31 BST 2022 riscv64 GNU/Linux
> / # cat /proc/cpuinfo
> processor : 0
> hart : 0
> isa : rv64imafdc
> mmu : sv39
> uarch : andestech,ax45mp
> mvendorid : 0x31e
> marchid : 0x8000000000008a45
> mimpid : 0x500
>
> / # for i in machine family soc_id revision; do echo -n "$i: ";cat /sys/devices/
> soc0/$i; done
> machine: Renesas SMARC EVK based on r9a07g043f01
> family: RZ/Five
> soc_id: r9a07g043
> revision: 0
> / #
> / # cat /proc/interrupts
> CPU0
> 1: 0 SiFive PLIC 412 Level 1004b800.serial:rx err
> 2: 33 SiFive PLIC 414 Level 1004b800.serial:rx full
> 3: 919 SiFive PLIC 415 Level 1004b800.serial:tx empty
> 4: 0 SiFive PLIC 413 Level 1004b800.serial:break
> 5: 44106 RISC-V INTC 5 Edge riscv-timer
> 6: 62 SiFive PLIC 416 Level 1004b800.serial:rx ready
> IPI0: 0 Rescheduling interrupts
> IPI1: 0 Function call interrupts
> IPI2: 0 CPU stop interrupts
> IPI3: 0 IRQ work interrupts
> IPI4: 0 Timer broadcast interrupts
> / #
> / # cat /proc/meminfo
> MemTotal: 882308 kB
> MemFree: 861440 kB
> MemAvailable: 859188 kB
> Buffers: 0 kB
> Cached: 1796 kB
> SwapCached: 0 kB
> Active: 0 kB
> Inactive: 84 kB
> Active(anon): 0 kB
> Inactive(anon): 84 kB
> Active(file): 0 kB
> Inactive(file): 0 kB
> Unevictable: 1796 kB
> Mlocked: 0 kB
> SwapTotal: 0 kB
> SwapFree: 0 kB
> Dirty: 0 kB
> Writeback: 0 kB
> AnonPages: 120 kB
> Mapped: 1200 kB
> Shmem: 0 kB
> KReclaimable: 6732 kB
> Slab: 12088 kB
> SReclaimable: 6732 kB
> SUnreclaim: 5356 kB
> KernelStack: 636 kB
> PageTables: 32 kB
> NFS_Unstable: 0 kB
> Bounce: 0 kB
> WritebackTmp: 0 kB
> CommitLimit: 441152 kB
> Committed_AS: 592 kB
> VmallocTotal: 67108864 kB
> VmallocUsed: 840 kB
> VmallocChunk: 0 kB
> Percpu: 84 kB
> HugePages_Total: 0
> HugePages_Free: 0
> HugePages_Rsvd: 0
> HugePages_Surp: 0
> Hugepagesize: 2048 kB
> Hugetlb: 0 kB
> / #
>
> -------------------
>
>
> Lad Prabhakar (10):
> dt-bindings: soc: renesas: Move renesas.yaml from arm to soc
> dt-bindings: riscv: Sort the CPU core list alphabetically
> dt-bindings: riscv: Add Andes AX45MP core to the list
> dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC
> riscv: Kconfig.socs: Add ARCH_RENESAS kconfig option
> riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC
> riscv: dts: r9a07g043: Add placeholder nodes
> riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK
> MAINTAINERS: Add entry for Renesas RISC-V architecture
> riscv: configs: defconfig: Enable Renesas RZ/Five SoC
>
> .../devicetree/bindings/riscv/cpus.yaml | 11 +-
> .../{arm => soc/renesas}/renesas.yaml | 5 +-
> MAINTAINERS | 4 +-
> arch/riscv/Kconfig.socs | 5 +
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/renesas/Makefile | 2 +
> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 270 ++++++++++++++++++
> .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 ++
> .../boot/dts/renesas/rzfive-smarc-som.dtsi | 19 ++
> arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 15 +
> arch/riscv/configs/defconfig | 3 +
> 11 files changed, 353 insertions(+), 9 deletions(-)
> rename Documentation/devicetree/bindings/{arm => soc/renesas}/renesas.yaml (98%)
> create mode 100644 arch/riscv/boot/dts/renesas/Makefile
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
> create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
>
> --
> 2.25.1
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
From: Lad Prabhakar <[email protected]>
renesas.yaml lists out all the Renesas SoC's and the platforms/EVK's which
is either ARM32/ARM64. It would rather make sense if we move renesas.yaml
to the soc/renesas folder instead. This is in preparation for adding a new
SoC (RZ/Five) from Renesas which is based on RISC-V.
While at it drop the old entry for renesas.yaml from MAINTAINERS file and
there is no need to update the new file path of renesas.yaml as we already
have an entry for Documentation/devicetree/bindings/soc/renesas/ folder.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
---
v3 -> v4
* Updated the path in the DT binding
* Included RB tag from Geert
v3:
* New patch along with this series previously posted as a standalone
patch [0].
[0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/[email protected]/
---
.../devicetree/bindings/{arm => soc/renesas}/renesas.yaml | 2 +-
MAINTAINERS | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
rename Documentation/devicetree/bindings/{arm => soc/renesas}/renesas.yaml (99%)
diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
similarity index 99%
rename from Documentation/devicetree/bindings/arm/renesas.yaml
rename to Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index f51464a08aff..07c5e6ebd5a0 100644
--- a/Documentation/devicetree/bindings/arm/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/renesas.yaml#
+$id: http://devicetree.org/schemas/soc/renesas/renesas.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas SH-Mobile, R-Mobile, and R-Car Platform
diff --git a/MAINTAINERS b/MAINTAINERS
index d71b20527224..48c5a152f743 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2679,7 +2679,6 @@ S: Supported
Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/
C: irc://irc.libera.chat/renesas-soc
T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
-F: Documentation/devicetree/bindings/arm/renesas.yaml
F: Documentation/devicetree/bindings/hwinfo/renesas,prr.yaml
F: Documentation/devicetree/bindings/soc/renesas/
F: arch/arm/boot/dts/emev2*
--
2.25.1
On Tue, Sep 20, 2022 at 09:24:05PM +0200, Geert Uytterhoeven wrote:
> Hi Conor,
>
> On Tue, Sep 20, 2022 at 9:20 PM Conor Dooley <[email protected]> wrote:
> > On Tue, Sep 20, 2022 at 07:48:54PM +0100, Prabhakar wrote:
> > > From: Lad Prabhakar <[email protected]>
> > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > entry-class social infrastructure gateway control and industrial gateway
> > > control.
> > >
> > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > (R9A07G043) SoC and updates the bindings for the same. Below is the list
> > > of IP blocks added in the initial SoC DTSI which can be used to boot via
> > > initramfs on RZ/Five SMARC EVK:
> > > - AX45MP CPU
> > > - CPG
> > > - PINCTRL
> > > - PLIC
> > > - SCIF0
> > > - SYSC
> >
> > Ran into one complaint from dtbs_check:
> > arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c50200: '#phy-cells' is a required property
> > From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
> > arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c70200: '#phy-cells' is a required property
> > From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
> >
> > Other than that which should be a trivial fix the whole lot looks good
> > to me...
>
> That's due to the placeholders...
Right, but #phy-cells will be added into the usb-phys once you (plural)
figure out how to integrate with the existing CMO stuff?
> Currently it is not yet a requirement that "make dtbs_check" is warning-free.
I was really hoping that it could be a requirement for 6.1 onwards. I've
managed to clear all of the other ones from arch/riscv.
> I'm wondering how we have to handle new SoCs with existing boards in
> the future. Probably just more properties in the placeholders...
New SoCs to existing boards is less of a problem then new CPUs to
existing SoCs from what I can see...
I know we just discussed it earlier today, but is it possible to make
these particular placeholders more complete so that dtbs_check shuts up
about them?
Thanks,
Conor.
Hi Conor,
On Tue, Sep 20, 2022 at 9:20 PM Conor Dooley <[email protected]> wrote:
> On Tue, Sep 20, 2022 at 07:48:54PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <[email protected]>
> > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > entry-class social infrastructure gateway control and industrial gateway
> > control.
> >
> > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > (R9A07G043) SoC and updates the bindings for the same. Below is the list
> > of IP blocks added in the initial SoC DTSI which can be used to boot via
> > initramfs on RZ/Five SMARC EVK:
> > - AX45MP CPU
> > - CPG
> > - PINCTRL
> > - PLIC
> > - SCIF0
> > - SYSC
>
> Ran into one complaint from dtbs_check:
> arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c50200: '#phy-cells' is a required property
> From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
> arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c70200: '#phy-cells' is a required property
> From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
>
> Other than that which should be a trivial fix the whole lot looks good
> to me...
That's due to the placeholders...
Currently it is not yet a requirement that "make dtbs_check" is warning-free.
I'm wondering how we have to handle new SoCs with existing boards in
the future. Probably just more properties in the placeholders...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Tue, Sep 20, 2022 at 10:04:06PM +0100, Lad, Prabhakar wrote:
> To clarify, shall I add ARCH_RENESAS to the beginning of the file or
> after the SOC_MICROCHIP_POLARFIRE config?
>
> As rest of the configs start with SOC and for Renesas it starts with
> ARCH, so to avoid another re-spin hence this query.
I'd say sort it based on Renesas so that everything else can be swapped
over in place. I don't care that much to be honest, was just an "if
you're already respinning" kind of thing.
Thanks,
Conor.
Hi Conor,
Thank you for the review.
On Tue, Sep 20, 2022 at 8:38 PM Conor Dooley <[email protected]> wrote:
>
> On Tue, Sep 20, 2022 at 09:24:05PM +0200, Geert Uytterhoeven wrote:
> > Hi Conor,
> >
> > On Tue, Sep 20, 2022 at 9:20 PM Conor Dooley <[email protected]> wrote:
> > > On Tue, Sep 20, 2022 at 07:48:54PM +0100, Prabhakar wrote:
> > > > From: Lad Prabhakar <[email protected]>
> > > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > > entry-class social infrastructure gateway control and industrial gateway
> > > > control.
> > > >
> > > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > > (R9A07G043) SoC and updates the bindings for the same. Below is the list
> > > > of IP blocks added in the initial SoC DTSI which can be used to boot via
> > > > initramfs on RZ/Five SMARC EVK:
> > > > - AX45MP CPU
> > > > - CPG
> > > > - PINCTRL
> > > > - PLIC
> > > > - SCIF0
> > > > - SYSC
> > >
> > > Ran into one complaint from dtbs_check:
> > > arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c50200: '#phy-cells' is a required property
> > > From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
> > > arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy@11c70200: '#phy-cells' is a required property
> > > From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
> > >
> > > Other than that which should be a trivial fix the whole lot looks good
> > > to me...
> >
> > That's due to the placeholders...
>
> Right, but #phy-cells will be added into the usb-phys once you (plural)
> figure out how to integrate with the existing CMO stuff?
>
Yes indeed.
> > Currently it is not yet a requirement that "make dtbs_check" is warning-free.
>
> I was really hoping that it could be a requirement for 6.1 onwards. I've
> managed to clear all of the other ones from arch/riscv.
>
Maybe i'll fix it and respin the series (along with the Kconfig.socs sorted).
Cheers,
Prabhakar
Hi Conor,
Thank you for the review.
On Tue, Sep 20, 2022 at 8:04 PM Conor Dooley <[email protected]> wrote:
>
> On Tue, Sep 20, 2022 at 07:48:59PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <[email protected]>
> >
> > Add ARCH_RENESAS config option to allow selecting the Renesas RISC-V SoCs.
> > We currently have the newly added RZ/Five (R9A07G043) RISC-V based SoC.
> >
> > Signed-off-by: Lad Prabhakar <[email protected]>
> > ---
> > v3 -> v4
> > * Dropped SOC_RENESAS_RZFIVE config option
> > * Dropped explicitly selecting SOC_BUS/GPIOLIB/PINCTRL configs
> > under ARCH_RENESAS
> > * Updated commit message
> > * Dropped RB tag
> > * Used riscv instead of RISC-V in subject line
> >
> > v2 -> v3
> > * Included RB tag from Geert
> >
> > v1 -> v2
> > * No Change
> > ---
> > arch/riscv/Kconfig.socs | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> > index 69774bb362d6..5c420ed55ef9 100644
> > --- a/arch/riscv/Kconfig.socs
> > +++ b/arch/riscv/Kconfig.socs
> > @@ -80,4 +80,9 @@ config SOC_CANAAN_K210_DTB_SOURCE
> >
> > endif # SOC_CANAAN
>
> I am not asking for a respin for this since no-one likely cares, but
> I think a future goal would be to sort the file alphabetically. I'll
> probably do it with the other 30-something patches my Kconfig.socs
> rework series has got to now - but if you *are* respinning sorting
> alphabetically (ignoring the CANAAN) would reduce future churn.
>
To clarify, shall I add ARCH_RENESAS to the beginning of the file or
after the SOC_MICROCHIP_POLARFIRE config?
As rest of the configs start with SOC and for Renesas it starts with
ARCH, so to avoid another re-spin hence this query.
Cheers,
Prabhakar
On 20/09/2022 20:48, Prabhakar wrote:
> From: Lad Prabhakar <[email protected]>
>
> renesas.yaml lists out all the Renesas SoC's and the platforms/EVK's which
> is either ARM32/ARM64. It would rather make sense if we move renesas.yaml
> to the soc/renesas folder instead. This is in preparation for adding a new
> SoC (RZ/Five) from Renesas which is based on RISC-V.
>
> While at it drop the old entry for renesas.yaml from MAINTAINERS file and
> there is no need to update the new file path of renesas.yaml as we already
> have an entry for Documentation/devicetree/bindings/soc/renesas/ folder.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Geert Uytterhoeven <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Tue, Sep 20, 2022 at 8:50 PM Prabhakar <[email protected]> wrote:
> From: Lad Prabhakar <[email protected]>
>
> Document Renesas RZ/Five (R9A07G043) SoC.
>
> More info about RZ/Five SoC:
> https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Acked-by: Krzysztof Kozlowski <[email protected]>
> Reviewed-by: Geert Uytterhoeven <[email protected]>
> ---
> v3 -> v4
> * No change
Will queue in renesas-devel for v6.2.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Tue, Sep 20, 2022 at 8:50 PM Prabhakar <[email protected]> wrote:
> From: Lad Prabhakar <[email protected]>
>
> renesas.yaml lists out all the Renesas SoC's and the platforms/EVK's which
> is either ARM32/ARM64. It would rather make sense if we move renesas.yaml
> to the soc/renesas folder instead. This is in preparation for adding a new
> SoC (RZ/Five) from Renesas which is based on RISC-V.
>
> While at it drop the old entry for renesas.yaml from MAINTAINERS file and
> there is no need to update the new file path of renesas.yaml as we already
> have an entry for Documentation/devicetree/bindings/soc/renesas/ folder.
>
> Signed-off-by: Lad Prabhakar <[email protected]>
> Reviewed-by: Geert Uytterhoeven <[email protected]>
> ---
> v3 -> v4
> * Updated the path in the DT binding
> * Included RB tag from Geert
Will queue in renesas-devel for v6.2.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds