This is a forward port / upstream refactor of code delivered
downstream by Qualcomm over at [0] to enable the DWMAC5 based
implementation called EMAC3 on the sa8540p-ride dev board.
From what I can tell with the board schematic in hand,
as well as the code delivered, the main changes needed are:
1. A new address space layout for dwmac5/EMAC3 MTL/DMA regs
2. A new programming sequence required for the EMAC3 base platforms
This series addresses the devicetree changes to support this
hardware bringup.
As requested[1], it has been split up by compile deps / maintainer tree.
The associated v4 of the netdev specific changes can be found at [2],
and is merged.
The clock patch from this series was picked up from v5, leaving just the
devicetree bits here.
Together, they result in the ethernet controller working for
both controllers on this platform.
References:
[0] https://git.codelinaro.org/clo/la/kernel/ark-5.14/-/commit/510235ad02d7f0df478146fb00d7a4ba74821b17
[1] https://lore.kernel.org/netdev/[email protected]/
[2] https://lore.kernel.org/netdev/[email protected]/T/#t
Older versions:
v5: https://lore.kernel.org/linux-arm-msm/[email protected]/
v4: https://lore.kernel.org/netdev/[email protected]/
v3: https://lore.kernel.org/netdev/[email protected]/T/#m2f267485d215903494d9572507417793e600b2bf
v2: https://lore.kernel.org/netdev/[email protected]/
v1: https://lore.kernel.org/netdev/[email protected]/
Thanks,
Andrew
Andrew Halaney (2):
arm64: dts: qcom: sc8280xp: Add ethernet nodes
arm64: dts: qcom: sa8540p-ride: Add ethernet nodes
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 238 ++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 60 ++++++
2 files changed, 298 insertions(+)
--
2.40.0
This platform has 2 MACs integrated in it, go ahead and describe them.
Reviewed-by: Konrad Dybcio <[email protected]>
Tested-by: Brian Masney <[email protected]>
Signed-off-by: Andrew Halaney <[email protected]>
---
Changes since v5:
* None
Changes since v4:
* Be consistent in newlines (Brian)
* Add Tested-by (Brian)
Changes since v3:
* Order soc node via unit address (Konrad)
* Add Reviewed-by (Konrad)
Changes since v2:
* Fix spacing (Konrad)
Changes since v1:
* None
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 60 ++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 8fa9fbfe5d00..a2320f880795 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -768,6 +768,36 @@ soc: soc@0 {
ranges = <0 0 0 0 0x10 0>;
dma-ranges = <0 0 0 0 0x10 0>;
+ ethernet0: ethernet@20000 {
+ compatible = "qcom,sc8280xp-ethqos";
+ reg = <0x0 0x00020000 0x0 0x10000>,
+ <0x0 0x00036000 0x0 0x100>;
+ reg-names = "stmmaceth", "rgmii";
+
+ clocks = <&gcc GCC_EMAC0_AXI_CLK>,
+ <&gcc GCC_EMAC0_SLV_AHB_CLK>,
+ <&gcc GCC_EMAC0_PTP_CLK>,
+ <&gcc GCC_EMAC0_RGMII_CLK>;
+ clock-names = "stmmaceth",
+ "pclk",
+ "ptp_ref",
+ "rgmii";
+
+ interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
+
+ iommus = <&apps_smmu 0x4c0 0xf>;
+ power-domains = <&gcc EMAC_0_GDSC>;
+
+ snps,tso;
+ snps,pbl = <32>;
+ rx-fifo-depth = <4096>;
+ tx-fifo-depth = <4096>;
+
+ status = "disabled";
+ };
+
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sc8280xp";
reg = <0x0 0x00100000 0x0 0x1f0000>;
@@ -4706,6 +4736,36 @@ dispcc1: clock-controller@22100000 {
status = "disabled";
};
+
+ ethernet1: ethernet@23000000 {
+ compatible = "qcom,sc8280xp-ethqos";
+ reg = <0x0 0x23000000 0x0 0x10000>,
+ <0x0 0x23016000 0x0 0x100>;
+ reg-names = "stmmaceth", "rgmii";
+
+ clocks = <&gcc GCC_EMAC1_AXI_CLK>,
+ <&gcc GCC_EMAC1_SLV_AHB_CLK>,
+ <&gcc GCC_EMAC1_PTP_CLK>,
+ <&gcc GCC_EMAC1_RGMII_CLK>;
+ clock-names = "stmmaceth",
+ "pclk",
+ "ptp_ref",
+ "rgmii";
+
+ interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_lpi";
+
+ iommus = <&apps_smmu 0x40 0xf>;
+ power-domains = <&gcc EMAC_1_GDSC>;
+
+ snps,tso;
+ snps,pbl = <32>;
+ rx-fifo-depth = <4096>;
+ tx-fifo-depth = <4096>;
+
+ status = "disabled";
+ };
};
sound: sound {
--
2.40.0
Enable both the MACs found on the board.
ethernet0 and ethernet1 both ultimately go to a series of on board
switches which aren't managed by this processor.
ethernet0 is connected to a Marvell 88EA1512 phy via RGMII. That goes to
the series of switches via SGMII on the "media" side of the phy.
RGMII_SGMII mode is enabled via devicetree register descriptions.
The switch on the "media" side has auto-negotiation disabled, so
configuration from userspace similar to:
ethtool -s eth0 autoneg off speed 1000 duplex full
is necessary to get traffic flowing on that interface.
ethernet1 is in a mac2mac/fixed-link configuration going to the same
series of switches directly via RGMII.
Tested-by: Brian Masney <[email protected]>
Signed-off-by: Andrew Halaney <[email protected]>
---
Changes since v5:
* Move mtl nodes into ethernet nodes so they're evaluated when
running the dtbs_check (Stephen)
Changes since v4:
* Remove needless interrupt-parent (Konrad)
* Add Tested-by (Brian)
Changes since v3:
* Compatible goes first in node (Krzysztof)
Changes since v1 and v2:
* None
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 238 ++++++++++++++++++++++
1 file changed, 238 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
index 24fa449d48a6..21e9eaf914dd 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -151,6 +151,184 @@ vreg_l8g: ldo8 {
};
};
+ðernet0 {
+ snps,mtl-rx-config = <ðernet0_mtl_rx_setup>;
+ snps,mtl-tx-config = <ðernet0_mtl_tx_setup>;
+
+ max-speed = <1000>;
+ phy-handle = <&rgmii_phy>;
+ phy-mode = "rgmii-txid";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <ðernet0_default>;
+
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* Marvell 88EA1512 */
+ rgmii_phy: phy@8 {
+ reg = <0x8>;
+
+ interrupts-extended = <&tlmm 127 IRQ_TYPE_EDGE_FALLING>;
+
+ reset-gpios = <&pmm8540c_gpios 1 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <11000>;
+ reset-deassert-us = <70000>;
+
+ device_type = "ethernet-phy";
+
+ /* Set to RGMII_SGMII mode and soft reset. Turn off auto-negotiation
+ * from userspace to talk to the switch on the SGMII side of things
+ */
+ marvell,reg-init =
+ /* Set MODE[2:0] to RGMII_SGMII */
+ <0x12 0x14 0xfff8 0x4>,
+ /* Soft reset required after changing MODE[2:0] */
+ <0x12 0x14 0x7fff 0x8000>;
+ };
+ };
+
+ ethernet0_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ snps,route-up;
+ snps,priority = <0x1>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ snps,route-ptp;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ snps,route-avcp;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ snps,priority = <0xc>;
+ };
+ };
+
+ ethernet0_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ snps,tx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,send_slope = <0x1000>;
+ snps,idle_slope = <0x1000>;
+ snps,high_credit = <0x3e800>;
+ snps,low_credit = <0xffc18000>;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,send_slope = <0x1000>;
+ snps,idle_slope = <0x1000>;
+ snps,high_credit = <0x3e800>;
+ snps,low_credit = <0xffc18000>;
+ };
+ };
+};
+
+ðernet1 {
+ snps,mtl-rx-config = <ðernet1_mtl_rx_setup>;
+ snps,mtl-tx-config = <ðernet1_mtl_tx_setup>;
+
+ max-speed = <1000>;
+ phy-mode = "rgmii-txid";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <ðernet1_default>;
+
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+
+ ethernet1_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ snps,rx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x0>;
+ snps,route-up;
+ snps,priority = <0x1>;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ snps,map-to-dma-channel = <0x1>;
+ snps,route-ptp;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x2>;
+ snps,route-avcp;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,map-to-dma-channel = <0x3>;
+ snps,priority = <0xc>;
+ };
+ };
+
+ ethernet1_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ snps,tx-sched-sp;
+
+ queue0 {
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,dcb-algorithm;
+ };
+
+ queue2 {
+ snps,avb-algorithm;
+ snps,send_slope = <0x1000>;
+ snps,idle_slope = <0x1000>;
+ snps,high_credit = <0x3e800>;
+ snps,low_credit = <0xffc18000>;
+ };
+
+ queue3 {
+ snps,avb-algorithm;
+ snps,send_slope = <0x1000>;
+ snps,idle_slope = <0x1000>;
+ snps,high_credit = <0x3e800>;
+ snps,low_credit = <0xffc18000>;
+ };
+ };
+};
+
&i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_default>;
@@ -316,6 +494,66 @@ &xo_board_clk {
/* PINCTRL */
&tlmm {
+ ethernet0_default: ethernet0-default-state {
+ mdc-pins {
+ pins = "gpio175";
+ function = "rgmii_0";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ mdio-pins {
+ pins = "gpio176";
+ function = "rgmii_0";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ rgmii-tx-pins {
+ pins = "gpio183", "gpio184", "gpio185", "gpio186", "gpio187", "gpio188";
+ function = "rgmii_0";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ rgmii-rx-pins {
+ pins = "gpio177", "gpio178", "gpio179", "gpio180", "gpio181", "gpio182";
+ function = "rgmii_0";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
+ ethernet1_default: ethernet1-default-state {
+ mdc-pins {
+ pins = "gpio97";
+ function = "rgmii_1";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ mdio-pins {
+ pins = "gpio98";
+ function = "rgmii_1";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ rgmii-tx-pins {
+ pins = "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110";
+ function = "rgmii_1";
+ drive-strength = <16>;
+ bias-pull-up;
+ };
+
+ rgmii-rx-pins {
+ pins = "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104";
+ function = "rgmii_1";
+ drive-strength = <16>;
+ bias-disable;
+ };
+ };
+
i2c0_default: i2c0-default-state {
/* To USB7002T-I/KDXVA0 USB hub (SIP1 only) */
pins = "gpio135", "gpio136";
--
2.40.0
On Mon, May 01, 2023 at 03:51:03PM -0500, Andrew Halaney wrote:
> This is a forward port / upstream refactor of code delivered
> downstream by Qualcomm over at [0] to enable the DWMAC5 based
> implementation called EMAC3 on the sa8540p-ride dev board.
>
> >From what I can tell with the board schematic in hand,
> as well as the code delivered, the main changes needed are:
>
> 1. A new address space layout for dwmac5/EMAC3 MTL/DMA regs
> 2. A new programming sequence required for the EMAC3 base platforms
>
> This series addresses the devicetree changes to support this
> hardware bringup.
>
> As requested[1], it has been split up by compile deps / maintainer tree.
> The associated v4 of the netdev specific changes can be found at [2],
> and is merged.
>
> The clock patch from this series was picked up from v5, leaving just the
> devicetree bits here.
>
> Together, they result in the ethernet controller working for
> both controllers on this platform.
Reviewed-by: Brian Masney <[email protected]>
On Mon, 1 May 2023 15:51:03 -0500, Andrew Halaney wrote:
> This is a forward port / upstream refactor of code delivered
> downstream by Qualcomm over at [0] to enable the DWMAC5 based
> implementation called EMAC3 on the sa8540p-ride dev board.
>
> From what I can tell with the board schematic in hand,
> as well as the code delivered, the main changes needed are:
>
> [...]
Applied, thanks!
[1/2] arm64: dts: qcom: sc8280xp: Add ethernet nodes
commit: b405d8d500e59e1edc51d934a766ea6127e1e69d
[2/2] arm64: dts: qcom: sa8540p-ride: Add ethernet nodes
commit: 57827e87be5447559cc3495567349ff002a6b33a
Best regards,
--
Bjorn Andersson <[email protected]>