In Tegra264 the carveouts (GSCs) used to communicate between BPMP and
CPU-NS may reside in DRAM. The location will be signalled using reserved
memory node in DT. Additionally some minor updates to the HSP driver are
done to support the new chip.
Peter De Schrijver (4):
dt-bindings: mailbox: tegra: Document Tegra264 HSP
dt-bindings: Add bindings to support DRAM MRQ GSCs
dt-bindings: memory-region property for tegra186-bpmp
firmware: tegra: bpmp: Add support for DRAM MRQ GSCs
Stefan Kristiansson (2):
mailbox: tegra: add support for Tegra264
soc: tegra: fuse: add support for Tegra264
.../firmware/nvidia,tegra186-bpmp.yaml | 37 ++-
.../bindings/mailbox/nvidia,tegra186-hsp.yaml | 1 +
.../nvidia,tegra264-bpmp-shmem.yaml | 45 ++++
drivers/firmware/tegra/bpmp-tegra186.c | 214 ++++++++++++------
drivers/firmware/tegra/bpmp.c | 4 +-
drivers/mailbox/tegra-hsp.c | 16 +-
drivers/soc/tegra/fuse/tegra-apbmisc.c | 3 +-
include/soc/tegra/fuse.h | 3 +-
8 files changed, 251 insertions(+), 72 deletions(-)
create mode 100644 Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml
--
2.34.1
Add the compatible string for the HSP block found on the Tegra264 SoC.
The HSP block in Tegra264 is not register compatible with the one in
Tegra194 or Tegra234 hence there is no fallback compatibility string.
Signed-off-by: Peter De Schrijver <[email protected]>
---
.../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
index a3e87516d637..2d14fc948999 100644
--- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
+++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml
@@ -66,6 +66,7 @@ properties:
oneOf:
- const: nvidia,tegra186-hsp
- const: nvidia,tegra194-hsp
+ - const: nvidia,tegra264-hsp
- items:
- const: nvidia,tegra234-hsp
- const: nvidia,tegra194-hsp
--
2.34.1
On Wed, May 10, 2023 at 02:31:24PM +0300, Peter De Schrijver wrote:
> In Tegra264 the carveouts (GSCs) used to communicate between BPMP and
> CPU-NS may reside in DRAM. The location will be signalled using reserved
> memory node in DT. Additionally some minor updates to the HSP driver are
> done to support the new chip.
>
> Peter De Schrijver (4):
> dt-bindings: mailbox: tegra: Document Tegra264 HSP
> dt-bindings: Add bindings to support DRAM MRQ GSCs
> dt-bindings: memory-region property for tegra186-bpmp
> firmware: tegra: bpmp: Add support for DRAM MRQ GSCs
>
> Stefan Kristiansson (2):
> mailbox: tegra: add support for Tegra264
> soc: tegra: fuse: add support for Tegra264
Changes in v2:
- Added signoff messages
- Updated bindings to support DRAM MRQ GSCs
- Split out memory-region property for tegra186-bpmp
- Addressed sparse errors in bpmp-tegra186.c
On Wed, May 10, 2023 at 02:31:26PM +0300, Peter De Schrijver wrote:
> Add the compatible string for the HSP block found on the Tegra264 SoC.
> The HSP block in Tegra264 is not register compatible with the one in
> Tegra194 or Tegra234 hence there is no fallback compatibility string.
>
> Signed-off-by: Peter De Schrijver <[email protected]>
> ---
> .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Thierry Reding <[email protected]>