Add driver for the StarFive JH7110 Video-Output clock controller.
And these clock controllers should power on and enable the clocks from
SYSCRG first before registering.
Signed-off-by: Xingyu Wu <[email protected]>
---
drivers/clk/starfive/Kconfig | 11 +
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jh7110-vout.c | 239 ++++++++++++++++++
3 files changed, 251 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-vout.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 0a63a47e4b97..c506de9346c5 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -61,3 +61,14 @@ config CLK_STARFIVE_JH7110_ISP
help
Say yes here to support the Image-Signal-Process clock controller
on the StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JH7110_VOUT
+ tristate "StarFive JH7110 Video-Output clock support"
+ depends on CLK_STARFIVE_JH7110_SYS && JH71XX_PMU
+ select AUXILIARY_BUS
+ select CLK_STARFIVE_JH71X0
+ select RESET_STARFIVE_JH7110
+ default m if ARCH_STARFIVE
+ help
+ Say yes here to support the Video-Output clock controller
+ on the StarFive JH7110 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 76fb9f8d628b..841377e45bb6 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_STG) += clk-starfive-jh7110-stg.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_ISP) += clk-starfive-jh7110-isp.o
+obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
new file mode 100644
index 000000000000..e5ef0c8c0494
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
@@ -0,0 +1,239 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 Video-Output Clock Driver
+ *
+ * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+#include "clk-starfive-jh7110.h"
+
+/* external clocks */
+#define JH7110_VOUTCLK_VOUT_SRC (JH7110_VOUTCLK_END + 0)
+#define JH7110_VOUTCLK_VOUT_TOP_AHB (JH7110_VOUTCLK_END + 1)
+#define JH7110_VOUTCLK_VOUT_TOP_AXI (JH7110_VOUTCLK_END + 2)
+#define JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK (JH7110_VOUTCLK_END + 3)
+#define JH7110_VOUTCLK_I2STX0_BCLK (JH7110_VOUTCLK_END + 4)
+#define JH7110_VOUTCLK_HDMITX0_PIXELCLK (JH7110_VOUTCLK_END + 5)
+#define JH7110_VOUTCLK_EXT_END (JH7110_VOUTCLK_END + 6)
+
+static struct clk_bulk_data jh7110_vout_top_clks[] = {
+ { .id = "vout_src" },
+ { .id = "vout_top_ahb" }
+};
+
+static const struct jh71x0_clk_data jh7110_voutclk_data[] = {
+ /* divider */
+ JH71X0__DIV(JH7110_VOUTCLK_APB, "apb", 8, JH7110_VOUTCLK_VOUT_TOP_AHB),
+ JH71X0__DIV(JH7110_VOUTCLK_DC8200_PIX, "dc8200_pix", 63, JH7110_VOUTCLK_VOUT_SRC),
+ JH71X0__DIV(JH7110_VOUTCLK_DSI_SYS, "dsi_sys", 31, JH7110_VOUTCLK_VOUT_SRC),
+ JH71X0__DIV(JH7110_VOUTCLK_TX_ESC, "tx_esc", 31, JH7110_VOUTCLK_VOUT_TOP_AHB),
+ /* dc8200 */
+ JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
+ JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI),
+ JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB),
+ JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX,
+ JH7110_VOUTCLK_HDMITX0_PIXELCLK),
+ JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX,
+ JH7110_VOUTCLK_HDMITX0_PIXELCLK),
+ /* LCD */
+ JH71X0_GMUX(JH7110_VOUTCLK_DOM_VOUT_TOP_LCD, "dom_vout_top_lcd", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX0,
+ JH7110_VOUTCLK_DC8200_PIX1),
+ /* dsiTx */
+ JH71X0_GATE(JH7110_VOUTCLK_DSITX_APB, "dsiTx_apb", 0, JH7110_VOUTCLK_DSI_SYS),
+ JH71X0_GATE(JH7110_VOUTCLK_DSITX_SYS, "dsiTx_sys", 0, JH7110_VOUTCLK_DSI_SYS),
+ JH71X0_GMUX(JH7110_VOUTCLK_DSITX_DPI, "dsiTx_dpi", 0, 2,
+ JH7110_VOUTCLK_DC8200_PIX,
+ JH7110_VOUTCLK_HDMITX0_PIXELCLK),
+ JH71X0_GATE(JH7110_VOUTCLK_DSITX_TXESC, "dsiTx_txesc", 0, JH7110_VOUTCLK_TX_ESC),
+ /* mipitx DPHY */
+ JH71X0_GATE(JH7110_VOUTCLK_MIPITX_DPHY_TXESC, "mipitx_dphy_txesc", 0,
+ JH7110_VOUTCLK_TX_ESC),
+ /* hdmi */
+ JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_MCLK, "hdmi_tx_mclk", 0,
+ JH7110_VOUTCLK_VOUT_TOP_HDMITX0_MCLK),
+ JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_BCLK, "hdmi_tx_bclk", 0,
+ JH7110_VOUTCLK_I2STX0_BCLK),
+ JH71X0_GATE(JH7110_VOUTCLK_HDMI_TX_SYS, "hdmi_tx_sys", 0, JH7110_VOUTCLK_APB),
+};
+
+static int jh7110_vout_top_rst_init(struct jh71x0_clk_priv *priv)
+{
+ struct reset_control *top_rst;
+
+ /* The reset should be shared and other Vout modules will use its. */
+ top_rst = devm_reset_control_get_shared(priv->dev, NULL);
+ if (IS_ERR(top_rst))
+ return dev_err_probe(priv->dev, PTR_ERR(top_rst), "failed to get top reset\n");
+
+ return reset_control_deassert(top_rst);
+}
+
+static struct clk_hw *jh7110_voutclk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct jh71x0_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < JH7110_VOUTCLK_END)
+ return &priv->reg[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+#ifdef CONFIG_PM
+static int jh7110_voutcrg_suspend(struct device *dev)
+{
+ struct top_sysclk *top = dev_get_drvdata(dev);
+
+ clk_bulk_disable_unprepare(top->top_clks_num, top->top_clks);
+
+ return 0;
+}
+
+static int jh7110_voutcrg_resume(struct device *dev)
+{
+ struct top_sysclk *top = dev_get_drvdata(dev);
+
+ return clk_bulk_prepare_enable(top->top_clks_num, top->top_clks);
+}
+#endif
+
+static const struct dev_pm_ops jh7110_voutcrg_pm_ops = {
+ SET_RUNTIME_PM_OPS(jh7110_voutcrg_suspend, jh7110_voutcrg_resume, NULL)
+};
+
+static int jh7110_voutcrg_probe(struct platform_device *pdev)
+{
+ struct jh71x0_clk_priv *priv;
+ struct top_sysclk *top;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JH7110_VOUTCLK_END),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ top = devm_kzalloc(&pdev->dev, sizeof(*top), GFP_KERNEL);
+ if (!top)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ top->top_clks = jh7110_vout_top_clks;
+ top->top_clks_num = ARRAY_SIZE(jh7110_vout_top_clks);
+ ret = devm_clk_bulk_get(priv->dev, top->top_clks_num, top->top_clks);
+ if (ret)
+ return dev_err_probe(priv->dev, ret, "failed to get top clocks\n");
+ dev_set_drvdata(priv->dev, top);
+
+ /* enable power domain and clocks */
+ pm_runtime_enable(priv->dev);
+ ret = pm_runtime_get_sync(priv->dev);
+ if (ret < 0)
+ return dev_err_probe(priv->dev, ret, "failed to turn on power\n");
+
+ ret = jh7110_vout_top_rst_init(priv);
+ if (ret)
+ goto err_exit;
+
+ for (idx = 0; idx < JH7110_VOUTCLK_END; idx++) {
+ u32 max = jh7110_voutclk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh7110_voutclk_data[idx].name,
+ .ops = starfive_jh71x0_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ .flags = jh7110_voutclk_data[idx].flags,
+ };
+ struct jh71x0_clk *clk = &priv->reg[idx];
+ unsigned int i;
+ const char *fw_name[JH7110_VOUTCLK_EXT_END - JH7110_VOUTCLK_END] = {
+ "vout_src",
+ "vout_top_ahb",
+ "vout_top_axi",
+ "vout_top_hdmitx0_mclk",
+ "i2stx0_bclk",
+ "hdmitx0_pixelclk"
+ };
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7110_voutclk_data[idx].parents[i];
+
+ if (pidx < JH7110_VOUTCLK_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx < JH7110_VOUTCLK_EXT_END)
+ parents[i].fw_name = fw_name[pidx - JH7110_VOUTCLK_END];
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & JH71X0_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ goto err_exit;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_voutclk_get, priv);
+ if (ret)
+ goto err_exit;
+
+ ret = jh7110_reset_controller_register(priv, "rst-vout", 4);
+ if (ret)
+ goto err_exit;
+
+ return 0;
+
+err_exit:
+ pm_runtime_put_sync(priv->dev);
+ pm_runtime_disable(priv->dev);
+ return ret;
+}
+
+static int jh7110_voutcrg_remove(struct platform_device *pdev)
+{
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id jh7110_voutcrg_match[] = {
+ { .compatible = "starfive,jh7110-voutcrg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7110_voutcrg_match);
+
+static struct platform_driver jh7110_voutcrg_driver = {
+ .probe = jh7110_voutcrg_probe,
+ .remove = jh7110_voutcrg_remove,
+ .driver = {
+ .name = "clk-starfive-jh7110-vout",
+ .of_match_table = jh7110_voutcrg_match,
+ .pm = &jh7110_voutcrg_pm_ops,
+ },
+};
+module_platform_driver(jh7110_voutcrg_driver);
+
+MODULE_AUTHOR("Xingyu Wu <[email protected]>");
+MODULE_DESCRIPTION("StarFive JH7110 Video-Output clock driver");
+MODULE_LICENSE("GPL");
--
2.25.1
On 2023-04-24 21:54, Xingyu Wu wrote:
> Add driver for the StarFive JH7110 Video-Output clock controller.
> And these clock controllers should power on and enable the clocks from
> SYSCRG first before registering.
>
> Signed-off-by: Xingyu Wu <[email protected]>
There seems to be something wrong with this patch. Building the kernel
with the whole series applied and with CONFIG_FORTIFY_SOURCE=y triggers
the following kernel bug:
[ 75.705103] detected buffer overflow in __fortify_strlen
[ 75.710497] ------------[ cut here ]------------
[ 75.715117] kernel BUG at lib/string_helpers.c:1027!
[ 75.720083] Kernel BUG [#1]
[ 75.722879] Modules linked in: clk_starfive_jh7110_vout(+) nvme_fabrics binfmt_misc starfive_wdt jh7110_trng watchdog sfctemp rng_core drm loop fuse drm_panel_orientation_quirks configfs ip_tables x_tables autofs4 ext4 crc32c_generic crc16 mbcache jbd2 dm_mod nvme nvme_core t10_pi crc64_rocksoft crc64 crc_t10dif crct10dif_generic crct10dif_common xhci_pci xhci_hcd mmc_block dwmac_starfive stmmac_platform stmmac usbcore pcs_xpcs of_mdio fixed_phy fwnode_mdio phylink libphy usb_common dw_mmc_starfive dw_mmc_pltfm clk_starfive_jh7110_isp dw_mmc clk_starfive_jh7110_aon ptp phy_starfive_dphy_rx mmc_core pps_core phy_jh7110_pcie i2c_designware_platform clk_starfive_jh7110_stg phy_jh7110_usb i2c_designware_core
[ 75.785411] CPU: 1 PID: 419 Comm: insmod Not tainted 6.3.1+ #1
[ 75.791241] Hardware name: StarFive VisionFive 2 v1.2A (DT)
[ 75.796809] epc : fortify_panic+0x1a/0x1c
[ 75.800828] ra : fortify_panic+0x1a/0x1c
[ 75.804838] epc : ffffffff80874242 ra : ffffffff80874242 sp : ffffffc80454b6a0
[ 75.812054] gp : ffffffff8157f008 tp : ffffffd8c1214f80 t0 : 6465746365746564
[ 75.819269] t1 : 0000000000000064 t2 : 2064657463657465 s0 : ffffffc80454b6b0
[ 75.826483] s1 : 0000000000000020 a0 : 000000000000002c a1 : ffffffd8fdd63688
[ 75.833697] a2 : ffffffd8fdd6f8e8 a3 : 0000000000000000 a4 : 0000000000000000
[ 75.840912] a5 : 0000000000000000 a6 : ffffffff81426a38 a7 : 0000000000000000
[ 75.848126] s2 : ffffffff80ec4e00 s3 : ffffffd8d9e28008 s4 : 000000000000001f
[ 75.855340] s5 : 0000000000000000 s6 : ffffffff81580798 s7 : 0000000000ffffff
[ 75.862555] s8 : ffffffd8d9e29ab0 s9 : 0000000000000011 s10: ffffffff017312a0
[ 75.869770] s11: ffffffff01731450 t3 : ffffffff81592df7 t4 : ffffffff81592df7
[ 75.876984] t5 : ffffffff81592df8 t6 : ffffffc80454b4a8
[ 75.882290] status: 0000000200000120 badaddr: 0000000000000000 cause: 0000000000000003
[ 75.890199] [<ffffffff80874242>] fortify_panic+0x1a/0x1c
[ 75.895513] [<ffffffff805c7e20>] auxiliary_match_id+0x70/0xcc
[ 75.901262] [<ffffffff805c7f22>] auxiliary_match+0x1e/0x2a
[ 75.906749] [<ffffffff805bd6b0>] __device_attach_driver+0x2c/0xe4
[ 75.912841] [<ffffffff805bb04e>] bus_for_each_drv+0x70/0xc4
[ 75.918418] [<ffffffff805bdb0a>] __device_attach+0x94/0x198
[ 75.923989] [<ffffffff805bde68>] device_initial_probe+0x1a/0x22
[ 75.929908] [<ffffffff805bc146>] bus_probe_device+0x96/0x98
[ 75.935482] [<ffffffff805b971e>] device_add+0x56a/0x722
[ 75.940710] [<ffffffff805c7fc4>] __auxiliary_device_add+0x40/0x92
[ 75.946803] [<ffffffff80556ff4>] jh7110_reset_controller_register+0x92/0xca
[ 75.953765] [<ffffffff0173034c>] jh7110_voutcrg_probe+0x236/0x2fa [clk_starfive_jh7110_vout]
[ 75.962228] [<ffffffff805bfb40>] platform_probe+0x5e/0xa6
[ 75.967629] [<ffffffff805bd1e6>] really_probe+0xa0/0x342
[ 75.972940] [<ffffffff805bd508>] __driver_probe_device+0x80/0x138
[ 75.979031] [<ffffffff805bd5f8>] driver_probe_device+0x38/0xc4
[ 75.984863] [<ffffffff805bd83a>] __driver_attach+0xd2/0x1a8
[ 75.990436] [<ffffffff805baf92>] bus_for_each_dev+0x6c/0xb8
[ 75.996011] [<ffffffff805bcab6>] driver_attach+0x26/0x2e
[ 76.001325] [<ffffffff805bc384>] bus_add_driver+0x10c/0x1ee
[ 76.006900] [<ffffffff805be5e2>] driver_register+0x52/0xf4
[ 76.012386] [<ffffffff805bf78e>] __platform_driver_register+0x28/0x30
[ 76.018827] [<ffffffff01b72028>] jh7110_voutcrg_driver_init+0x28/0x1000 [clk_starfive_jh7110_vout]
[ 76.027802] [<ffffffff8000281a>] do_one_initcall+0x5c/0x1c8
[ 76.033377] [<ffffffff800a7612>] do_init_module+0x4c/0x1f6
[ 76.038867] [<ffffffff800a9396>] load_module+0x1a6c/0x1ebe
[ 76.044356] [<ffffffff800a99ea>] __do_sys_finit_module+0x9c/0xf8
[ 76.050365] [<ffffffff800a9a82>] sys_finit_module+0x1c/0x24
[ 76.055936] [<ffffffff80003df8>] ret_from_syscall+0x0/0x2
[ 76.061343] Code: 0800 85aa 3517 007a 0513 7ee5 a097 ffff 80e7 fc20 (9002) 7179
[ 76.068735] ---[ end trace 0000000000000000 ]---
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
[email protected] http://aurel32.net
On 2023/5/15 5:46, Aurelien Jarno wrote:
> On 2023-04-24 21:54, Xingyu Wu wrote:
>> Add driver for the StarFive JH7110 Video-Output clock controller.
>> And these clock controllers should power on and enable the clocks from
>> SYSCRG first before registering.
>>
>> Signed-off-by: Xingyu Wu <[email protected]>
>
> There seems to be something wrong with this patch. Building the kernel
> with the whole series applied and with CONFIG_FORTIFY_SOURCE=y triggers
> the following kernel bug:
>
> [ 75.705103] detected buffer overflow in __fortify_strlen
> [ 75.710497] ------------[ cut here ]------------
> [ 75.715117] kernel BUG at lib/string_helpers.c:1027!
> [ 75.720083] Kernel BUG [#1]
> [ 75.722879] Modules linked in: clk_starfive_jh7110_vout(+) nvme_fabrics binfmt_misc starfive_wdt jh7110_trng watchdog sfctemp rng_core drm loop fuse drm_panel_orientation_quirks configfs ip_tables x_tables autofs4 ext4 crc32c_generic crc16 mbcache jbd2 dm_mod nvme nvme_core t10_pi crc64_rocksoft crc64 crc_t10dif crct10dif_generic crct10dif_common xhci_pci xhci_hcd mmc_block dwmac_starfive stmmac_platform stmmac usbcore pcs_xpcs of_mdio fixed_phy fwnode_mdio phylink libphy usb_common dw_mmc_starfive dw_mmc_pltfm clk_starfive_jh7110_isp dw_mmc clk_starfive_jh7110_aon ptp phy_starfive_dphy_rx mmc_core pps_core phy_jh7110_pcie i2c_designware_platform clk_starfive_jh7110_stg phy_jh7110_usb i2c_designware_core
> [ 75.785411] CPU: 1 PID: 419 Comm: insmod Not tainted 6.3.1+ #1
> [ 75.791241] Hardware name: StarFive VisionFive 2 v1.2A (DT)
> [ 75.796809] epc : fortify_panic+0x1a/0x1c
> [ 75.800828] ra : fortify_panic+0x1a/0x1c
> [ 75.804838] epc : ffffffff80874242 ra : ffffffff80874242 sp : ffffffc80454b6a0
> [ 75.812054] gp : ffffffff8157f008 tp : ffffffd8c1214f80 t0 : 6465746365746564
> [ 75.819269] t1 : 0000000000000064 t2 : 2064657463657465 s0 : ffffffc80454b6b0
> [ 75.826483] s1 : 0000000000000020 a0 : 000000000000002c a1 : ffffffd8fdd63688
> [ 75.833697] a2 : ffffffd8fdd6f8e8 a3 : 0000000000000000 a4 : 0000000000000000
> [ 75.840912] a5 : 0000000000000000 a6 : ffffffff81426a38 a7 : 0000000000000000
> [ 75.848126] s2 : ffffffff80ec4e00 s3 : ffffffd8d9e28008 s4 : 000000000000001f
> [ 75.855340] s5 : 0000000000000000 s6 : ffffffff81580798 s7 : 0000000000ffffff
> [ 75.862555] s8 : ffffffd8d9e29ab0 s9 : 0000000000000011 s10: ffffffff017312a0
> [ 75.869770] s11: ffffffff01731450 t3 : ffffffff81592df7 t4 : ffffffff81592df7
> [ 75.876984] t5 : ffffffff81592df8 t6 : ffffffc80454b4a8
> [ 75.882290] status: 0000000200000120 badaddr: 0000000000000000 cause: 0000000000000003
> [ 75.890199] [<ffffffff80874242>] fortify_panic+0x1a/0x1c
> [ 75.895513] [<ffffffff805c7e20>] auxiliary_match_id+0x70/0xcc
> [ 75.901262] [<ffffffff805c7f22>] auxiliary_match+0x1e/0x2a
> [ 75.906749] [<ffffffff805bd6b0>] __device_attach_driver+0x2c/0xe4
> [ 75.912841] [<ffffffff805bb04e>] bus_for_each_drv+0x70/0xc4
> [ 75.918418] [<ffffffff805bdb0a>] __device_attach+0x94/0x198
> [ 75.923989] [<ffffffff805bde68>] device_initial_probe+0x1a/0x22
> [ 75.929908] [<ffffffff805bc146>] bus_probe_device+0x96/0x98
> [ 75.935482] [<ffffffff805b971e>] device_add+0x56a/0x722
> [ 75.940710] [<ffffffff805c7fc4>] __auxiliary_device_add+0x40/0x92
> [ 75.946803] [<ffffffff80556ff4>] jh7110_reset_controller_register+0x92/0xca
> [ 75.953765] [<ffffffff0173034c>] jh7110_voutcrg_probe+0x236/0x2fa [clk_starfive_jh7110_vout]
> [ 75.962228] [<ffffffff805bfb40>] platform_probe+0x5e/0xa6
> [ 75.967629] [<ffffffff805bd1e6>] really_probe+0xa0/0x342
> [ 75.972940] [<ffffffff805bd508>] __driver_probe_device+0x80/0x138
> [ 75.979031] [<ffffffff805bd5f8>] driver_probe_device+0x38/0xc4
> [ 75.984863] [<ffffffff805bd83a>] __driver_attach+0xd2/0x1a8
> [ 75.990436] [<ffffffff805baf92>] bus_for_each_dev+0x6c/0xb8
> [ 75.996011] [<ffffffff805bcab6>] driver_attach+0x26/0x2e
> [ 76.001325] [<ffffffff805bc384>] bus_add_driver+0x10c/0x1ee
> [ 76.006900] [<ffffffff805be5e2>] driver_register+0x52/0xf4
> [ 76.012386] [<ffffffff805bf78e>] __platform_driver_register+0x28/0x30
> [ 76.018827] [<ffffffff01b72028>] jh7110_voutcrg_driver_init+0x28/0x1000 [clk_starfive_jh7110_vout]
> [ 76.027802] [<ffffffff8000281a>] do_one_initcall+0x5c/0x1c8
> [ 76.033377] [<ffffffff800a7612>] do_init_module+0x4c/0x1f6
> [ 76.038867] [<ffffffff800a9396>] load_module+0x1a6c/0x1ebe
> [ 76.044356] [<ffffffff800a99ea>] __do_sys_finit_module+0x9c/0xf8
> [ 76.050365] [<ffffffff800a9a82>] sys_finit_module+0x1c/0x24
> [ 76.055936] [<ffffffff80003df8>] ret_from_syscall+0x0/0x2
> [ 76.061343] Code: 0800 85aa 3517 007a 0513 7ee5 a097 ffff 80e7 fc20 (9002) 7179
> [ 76.068735] ---[ end trace 0000000000000000 ]---
>
I got the recurrence of this with CONFIG_FORTIFY_SOURCE=y.
And I found the problem that the reset name of auxiliary_device_id in VOUTCRG
is exactly 32 characters. I rename the reset of auxiliary_device_id in VOUTCRG
to a shorter name and fix the problem. And I will fix it in next patch.
Best regards,
Xingyu Wu