2023-05-22 06:42:14

by Wyes Karny

[permalink] [raw]
Subject: [PATCH 0/2] amd-pstate: amd_pstate related fixes

This 2 patch series has the following 2 fixes for amd_pstate:
- Currently, amd_pstate sets CPPC enable MSR for a single CPU. But ACPI
specification recommends driver to set CPPC enable register per-core.
Align amd_pstate driver with the spec.

- Remove some extra checks for active mode which are not required.

Wyes Karny (2):
cpufreq/amd-pstate: Write CPPC enable bit for each core
cpufreq/amd-pstate: Remove unnecessary active state checks

drivers/cpufreq/amd-pstate.c | 64 ++++++++++++++++--------------------
1 file changed, 28 insertions(+), 36 deletions(-)

--
2.34.1



2023-05-22 06:48:28

by Wyes Karny

[permalink] [raw]
Subject: [PATCH 1/2] cpufreq/amd-pstate: Write CPPC enable bit for each core

ACPI specification [1] says: "CPPC Enable Register: If supported by the
platform, OSPM writes a one to this register to enable CPPC on this
processor."

Make amd_pstate align with the specification.

To do so, move amd_pstate_enable function to per-policy/per-core
callbacks.

Also remove per-cpu loop from cppc_enable, because it's called from
per-policy/per-core callbacks and it was causing duplicate MSR writes.
This will improve driver-load, suspend-resume and offline-online on
shared memory system.

[1]: https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/08_Processor_Configuration_and_Control/declaring-processors.html#cppc-enable-register

Fixes: e059c184da47 ("cpufreq: amd-pstate: Introduce the support for the processors with shared memory solution")
Signed-off-by: Wyes Karny <[email protected]>
---
drivers/cpufreq/amd-pstate.c | 53 ++++++++++++++++++------------------
1 file changed, 26 insertions(+), 27 deletions(-)

diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 5a3d4aa0f45a..8c72f95ac315 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -226,29 +226,27 @@ static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata,
return ret;
}

-static inline int pstate_enable(bool enable)
+static inline int pstate_enable(int cpu, bool enable)
{
- return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable);
+ return wrmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_ENABLE, enable);
}

-static int cppc_enable(bool enable)
+static int cppc_enable(int cpu, bool enable)
{
- int cpu, ret = 0;
+ int ret = 0;
struct cppc_perf_ctrls perf_ctrls;

- for_each_present_cpu(cpu) {
- ret = cppc_set_enable(cpu, enable);
+ ret = cppc_set_enable(cpu, enable);
+ if (ret)
+ return ret;
+
+ /* Enable autonomous mode for EPP */
+ if (cppc_state == AMD_PSTATE_ACTIVE) {
+ /* Set desired perf as zero to allow EPP firmware control */
+ perf_ctrls.desired_perf = 0;
+ ret = cppc_set_perf(cpu, &perf_ctrls);
if (ret)
return ret;
-
- /* Enable autonomous mode for EPP */
- if (cppc_state == AMD_PSTATE_ACTIVE) {
- /* Set desired perf as zero to allow EPP firmware control */
- perf_ctrls.desired_perf = 0;
- ret = cppc_set_perf(cpu, &perf_ctrls);
- if (ret)
- return ret;
- }
}

return ret;
@@ -256,9 +254,9 @@ static int cppc_enable(bool enable)

DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable);

-static inline int amd_pstate_enable(bool enable)
+static inline int amd_pstate_enable(int cpu, bool enable)
{
- return static_call(amd_pstate_enable)(enable);
+ return static_call(amd_pstate_enable)(cpu, enable);
}

static int pstate_init_perf(struct amd_cpudata *cpudata)
@@ -643,6 +641,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy)

cpudata->cpu = policy->cpu;

+ ret = amd_pstate_enable(policy->cpu, true);
+
ret = amd_pstate_init_perf(cpudata);
if (ret)
goto free_cpudata1;
@@ -724,7 +724,7 @@ static int amd_pstate_cpu_resume(struct cpufreq_policy *policy)
{
int ret;

- ret = amd_pstate_enable(true);
+ ret = amd_pstate_enable(policy->cpu, true);
if (ret)
pr_err("failed to enable amd-pstate during resume, return %d\n", ret);

@@ -735,7 +735,7 @@ static int amd_pstate_cpu_suspend(struct cpufreq_policy *policy)
{
int ret;

- ret = amd_pstate_enable(false);
+ ret = amd_pstate_enable(policy->cpu, false);
if (ret)
pr_err("failed to disable amd-pstate during suspend, return %d\n", ret);

@@ -841,7 +841,6 @@ static ssize_t show_energy_performance_preference(

static void amd_pstate_driver_cleanup(void)
{
- amd_pstate_enable(false);
cppc_state = AMD_PSTATE_DISABLE;
current_pstate_driver = NULL;
}
@@ -1039,6 +1038,8 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
cpudata->cpu = policy->cpu;
cpudata->epp_policy = 0;

+ ret = amd_pstate_enable(policy->cpu, true);
+
ret = amd_pstate_init_perf(cpudata);
if (ret)
goto free_cpudata1;
@@ -1180,13 +1181,13 @@ static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy)
return 0;
}

-static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata)
+static void amd_pstate_epp_reenable(int cpu, struct amd_cpudata *cpudata)
{
struct cppc_perf_ctrls perf_ctrls;
u64 value, max_perf;
int ret;

- ret = amd_pstate_enable(true);
+ ret = amd_pstate_enable(cpu, true);
if (ret)
pr_err("failed to enable amd pstate during resume, return %d\n", ret);

@@ -1209,7 +1210,7 @@ static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy)
pr_debug("AMD CPU Core %d going online\n", cpudata->cpu);

if (cppc_state == AMD_PSTATE_ACTIVE) {
- amd_pstate_epp_reenable(cpudata);
+ amd_pstate_epp_reenable(policy->cpu, cpudata);
cpudata->suspended = false;
}

@@ -1280,7 +1281,7 @@ static int amd_pstate_epp_suspend(struct cpufreq_policy *policy)
cpudata->suspended = true;

/* disable CPPC in lowlevel firmware */
- ret = amd_pstate_enable(false);
+ ret = amd_pstate_enable(policy->cpu, false);
if (ret)
pr_err("failed to suspend, return %d\n", ret);

@@ -1295,7 +1296,7 @@ static int amd_pstate_epp_resume(struct cpufreq_policy *policy)
mutex_lock(&amd_pstate_limits_lock);

/* enable amd pstate from suspend state*/
- amd_pstate_epp_reenable(cpudata);
+ amd_pstate_epp_reenable(policy->cpu, cpudata);

mutex_unlock(&amd_pstate_limits_lock);

@@ -1370,8 +1371,6 @@ static int __init amd_pstate_init(void)
static_call_update(amd_pstate_update_perf, cppc_update_perf);
}

- /* enable amd pstate feature */
- ret = amd_pstate_enable(true);
if (ret) {
pr_err("failed to enable with return %d\n", ret);
return ret;
--
2.34.1


2023-05-22 06:58:09

by Wyes Karny

[permalink] [raw]
Subject: [PATCH 2/2] cpufreq/amd-pstate: Remove unnecessary active state checks

Some functions are only specific to amd_pstate active mode driver. This
functions cannot be called from passive/guided mode paths, therefore
remove these unnecessary checks.

Fixes: d4da12f8033a ("cpufreq: amd-pstate: implement amd pstate cpu online and offline callback")
Fixes: 50ddd2f78269 ("cpufreq: amd-pstate: implement suspend and resume callbacks")

Signed-off-by: Wyes Karny <[email protected]>
---
drivers/cpufreq/amd-pstate.c | 13 +++----------
1 file changed, 3 insertions(+), 10 deletions(-)

diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index 8c72f95ac315..fda66a206d26 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -1209,10 +1209,8 @@ static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy)

pr_debug("AMD CPU Core %d going online\n", cpudata->cpu);

- if (cppc_state == AMD_PSTATE_ACTIVE) {
- amd_pstate_epp_reenable(policy->cpu, cpudata);
- cpudata->suspended = false;
- }
+ amd_pstate_epp_reenable(policy->cpu, cpudata);
+ cpudata->suspended = false;

return 0;
}
@@ -1255,8 +1253,7 @@ static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy)
if (cpudata->suspended)
return 0;

- if (cppc_state == AMD_PSTATE_ACTIVE)
- amd_pstate_epp_offline(policy);
+ amd_pstate_epp_offline(policy);

return 0;
}
@@ -1273,10 +1270,6 @@ static int amd_pstate_epp_suspend(struct cpufreq_policy *policy)
struct amd_cpudata *cpudata = policy->driver_data;
int ret;

- /* avoid suspending when EPP is not enabled */
- if (cppc_state != AMD_PSTATE_ACTIVE)
- return 0;
-
/* set this flag to avoid setting core offline*/
cpudata->suspended = true;

--
2.34.1


2023-05-22 07:43:49

by Yuan, Perry

[permalink] [raw]
Subject: RE: [PATCH 2/2] cpufreq/amd-pstate: Remove unnecessary active state checks

[AMD Official Use Only - General]

Hi Wyse.

> -----Original Message-----
> From: Karny, Wyes <[email protected]>
> Sent: Monday, May 22, 2023 2:33 PM
> To: Huang, Ray <[email protected]>; [email protected];
> [email protected]
> Cc: Limonciello, Mario <[email protected]>; [email protected];
> Yuan, Perry <[email protected]>; [email protected]; linux-
> [email protected]; Karny, Wyes <[email protected]>
> Subject: [PATCH 2/2] cpufreq/amd-pstate: Remove unnecessary active state
> checks
>
> Some functions are only specific to amd_pstate active mode driver. This
> functions cannot be called from passive/guided mode paths, therefore remove
> these unnecessary checks.
>
> Fixes: d4da12f8033a ("cpufreq: amd-pstate: implement amd pstate cpu online
> and offline callback")
> Fixes: 50ddd2f78269 ("cpufreq: amd-pstate: implement suspend and resume
> callbacks")
>
> Signed-off-by: Wyes Karny <[email protected]>
> ---
> drivers/cpufreq/amd-pstate.c | 13 +++----------
> 1 file changed, 3 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index
> 8c72f95ac315..fda66a206d26 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -1209,10 +1209,8 @@ static int amd_pstate_epp_cpu_online(struct
> cpufreq_policy *policy)
>
> pr_debug("AMD CPU Core %d going online\n", cpudata->cpu);
>
> - if (cppc_state == AMD_PSTATE_ACTIVE) {
> - amd_pstate_epp_reenable(policy->cpu, cpudata);
> - cpudata->suspended = false;
> - }
> + amd_pstate_epp_reenable(policy->cpu, cpudata);
> + cpudata->suspended = false;
>

Thanks for your patch to improve the pstate driver.
Have you tested the online and offline callback can work for non-epp modes ?
If the callback works well, glad to add the review by for the patch.

Perry.

> return 0;
> }
> @@ -1255,8 +1253,7 @@ static int amd_pstate_epp_cpu_offline(struct
> cpufreq_policy *policy)
> if (cpudata->suspended)
> return 0;
>
> - if (cppc_state == AMD_PSTATE_ACTIVE)
> - amd_pstate_epp_offline(policy);
> + amd_pstate_epp_offline(policy);
>
> return 0;
> }
> @@ -1273,10 +1270,6 @@ static int amd_pstate_epp_suspend(struct
> cpufreq_policy *policy)
> struct amd_cpudata *cpudata = policy->driver_data;
> int ret;
>
> - /* avoid suspending when EPP is not enabled */
> - if (cppc_state != AMD_PSTATE_ACTIVE)
> - return 0;
> -
> /* set this flag to avoid setting core offline*/
> cpudata->suspended = true;
>
> --
> 2.34.1


2023-05-22 08:24:46

by Huang Rui

[permalink] [raw]
Subject: Re: [PATCH 1/2] cpufreq/amd-pstate: Write CPPC enable bit for each core

On Mon, May 22, 2023 at 02:33:24PM +0800, Karny, Wyes wrote:
> ACPI specification [1] says: "CPPC Enable Register: If supported by the
> platform, OSPM writes a one to this register to enable CPPC on this
> processor."
>
> Make amd_pstate align with the specification.
>
> To do so, move amd_pstate_enable function to per-policy/per-core
> callbacks.
>
> Also remove per-cpu loop from cppc_enable, because it's called from
> per-policy/per-core callbacks and it was causing duplicate MSR writes.
> This will improve driver-load, suspend-resume and offline-online on
> shared memory system.
>
> [1]: https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/08_Processor_Configuration_and_Control/declaring-processors.html#cppc-enable-register
>
> Fixes: e059c184da47 ("cpufreq: amd-pstate: Introduce the support for the processors with shared memory solution")
> Signed-off-by: Wyes Karny <[email protected]>
> ---
> drivers/cpufreq/amd-pstate.c | 53 ++++++++++++++++++------------------
> 1 file changed, 26 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 5a3d4aa0f45a..8c72f95ac315 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -226,29 +226,27 @@ static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata,
> return ret;
> }
>
> -static inline int pstate_enable(bool enable)
> +static inline int pstate_enable(int cpu, bool enable)
> {
> - return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable);
> + return wrmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_ENABLE, enable);

In the full MSR processors, the CPPCEnableRegister is per package, not per
thread. In share memory processors, it should be per thread.

Thanks,
Ray

> }
>
> -static int cppc_enable(bool enable)
> +static int cppc_enable(int cpu, bool enable)
> {
> - int cpu, ret = 0;
> + int ret = 0;
> struct cppc_perf_ctrls perf_ctrls;
>
> - for_each_present_cpu(cpu) {
> - ret = cppc_set_enable(cpu, enable);
> + ret = cppc_set_enable(cpu, enable);
> + if (ret)
> + return ret;
> +
> + /* Enable autonomous mode for EPP */
> + if (cppc_state == AMD_PSTATE_ACTIVE) {
> + /* Set desired perf as zero to allow EPP firmware control */
> + perf_ctrls.desired_perf = 0;
> + ret = cppc_set_perf(cpu, &perf_ctrls);
> if (ret)
> return ret;
> -
> - /* Enable autonomous mode for EPP */
> - if (cppc_state == AMD_PSTATE_ACTIVE) {
> - /* Set desired perf as zero to allow EPP firmware control */
> - perf_ctrls.desired_perf = 0;
> - ret = cppc_set_perf(cpu, &perf_ctrls);
> - if (ret)
> - return ret;
> - }
> }
>
> return ret;
> @@ -256,9 +254,9 @@ static int cppc_enable(bool enable)
>
> DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable);
>
> -static inline int amd_pstate_enable(bool enable)
> +static inline int amd_pstate_enable(int cpu, bool enable)
> {
> - return static_call(amd_pstate_enable)(enable);
> + return static_call(amd_pstate_enable)(cpu, enable);
> }
>
> static int pstate_init_perf(struct amd_cpudata *cpudata)
> @@ -643,6 +641,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
>
> cpudata->cpu = policy->cpu;
>
> + ret = amd_pstate_enable(policy->cpu, true);
> +
> ret = amd_pstate_init_perf(cpudata);
> if (ret)
> goto free_cpudata1;
> @@ -724,7 +724,7 @@ static int amd_pstate_cpu_resume(struct cpufreq_policy *policy)
> {
> int ret;
>
> - ret = amd_pstate_enable(true);
> + ret = amd_pstate_enable(policy->cpu, true);
> if (ret)
> pr_err("failed to enable amd-pstate during resume, return %d\n", ret);
>
> @@ -735,7 +735,7 @@ static int amd_pstate_cpu_suspend(struct cpufreq_policy *policy)
> {
> int ret;
>
> - ret = amd_pstate_enable(false);
> + ret = amd_pstate_enable(policy->cpu, false);
> if (ret)
> pr_err("failed to disable amd-pstate during suspend, return %d\n", ret);
>
> @@ -841,7 +841,6 @@ static ssize_t show_energy_performance_preference(
>
> static void amd_pstate_driver_cleanup(void)
> {
> - amd_pstate_enable(false);
> cppc_state = AMD_PSTATE_DISABLE;
> current_pstate_driver = NULL;
> }
> @@ -1039,6 +1038,8 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy)
> cpudata->cpu = policy->cpu;
> cpudata->epp_policy = 0;
>
> + ret = amd_pstate_enable(policy->cpu, true);
> +
> ret = amd_pstate_init_perf(cpudata);
> if (ret)
> goto free_cpudata1;
> @@ -1180,13 +1181,13 @@ static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy)
> return 0;
> }
>
> -static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata)
> +static void amd_pstate_epp_reenable(int cpu, struct amd_cpudata *cpudata)
> {
> struct cppc_perf_ctrls perf_ctrls;
> u64 value, max_perf;
> int ret;
>
> - ret = amd_pstate_enable(true);
> + ret = amd_pstate_enable(cpu, true);
> if (ret)
> pr_err("failed to enable amd pstate during resume, return %d\n", ret);
>
> @@ -1209,7 +1210,7 @@ static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy)
> pr_debug("AMD CPU Core %d going online\n", cpudata->cpu);
>
> if (cppc_state == AMD_PSTATE_ACTIVE) {
> - amd_pstate_epp_reenable(cpudata);
> + amd_pstate_epp_reenable(policy->cpu, cpudata);
> cpudata->suspended = false;
> }
>
> @@ -1280,7 +1281,7 @@ static int amd_pstate_epp_suspend(struct cpufreq_policy *policy)
> cpudata->suspended = true;
>
> /* disable CPPC in lowlevel firmware */
> - ret = amd_pstate_enable(false);
> + ret = amd_pstate_enable(policy->cpu, false);
> if (ret)
> pr_err("failed to suspend, return %d\n", ret);
>
> @@ -1295,7 +1296,7 @@ static int amd_pstate_epp_resume(struct cpufreq_policy *policy)
> mutex_lock(&amd_pstate_limits_lock);
>
> /* enable amd pstate from suspend state*/
> - amd_pstate_epp_reenable(cpudata);
> + amd_pstate_epp_reenable(policy->cpu, cpudata);
>
> mutex_unlock(&amd_pstate_limits_lock);
>
> @@ -1370,8 +1371,6 @@ static int __init amd_pstate_init(void)
> static_call_update(amd_pstate_update_perf, cppc_update_perf);
> }
>
> - /* enable amd pstate feature */
> - ret = amd_pstate_enable(true);
> if (ret) {
> pr_err("failed to enable with return %d\n", ret);
> return ret;
> --
> 2.34.1
>

2023-05-26 04:11:22

by kernel test robot

[permalink] [raw]
Subject: Re: [PATCH 1/2] cpufreq/amd-pstate: Write CPPC enable bit for each core

Hi Wyes,

kernel test robot noticed the following build warnings:

[auto build test WARNING on rafael-pm/linux-next]
[also build test WARNING on linus/master v6.4-rc3 next-20230525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url: https://github.com/intel-lab-lkp/linux/commits/Wyes-Karny/cpufreq-amd-pstate-Write-CPPC-enable-bit-for-each-core/20230522-143855
base: https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git linux-next
patch link: https://lore.kernel.org/r/20230522063325.80193-2-wyes.karny%40amd.com
patch subject: [PATCH 1/2] cpufreq/amd-pstate: Write CPPC enable bit for each core
config: x86_64-buildonly-randconfig-r001-20230525
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
mkdir -p ~/bin
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/6b2af0570adf6fe7c91fa9e839dc11387041c9b4
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Wyes-Karny/cpufreq-amd-pstate-Write-CPPC-enable-bit-for-each-core/20230522-143855
git checkout 6b2af0570adf6fe7c91fa9e839dc11387041c9b4
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang ~/bin/make.cross W=1 O=build_dir ARCH=x86_64 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang ~/bin/make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash drivers/cpufreq/ kernel/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/

All warnings (new ones prefixed by >>):

>> drivers/cpufreq/amd-pstate.c:1374:6: warning: variable 'ret' is uninitialized when used here [-Wuninitialized]
if (ret) {
^~~
drivers/cpufreq/amd-pstate.c:1339:9: note: initialize the variable 'ret' to silence this warning
int ret;
^
= 0
1 warning generated.


vim +/ret +1374 drivers/cpufreq/amd-pstate.c

ffa5096a7c3386 Perry Yuan 2023-01-31 1335
ec437d71db77a1 Huang Rui 2021-12-24 1336 static int __init amd_pstate_init(void)
ec437d71db77a1 Huang Rui 2021-12-24 1337 {
3666062b87ec8b Greg Kroah-Hartman 2023-03-13 1338 struct device *dev_root;
ec437d71db77a1 Huang Rui 2021-12-24 1339 int ret;
ec437d71db77a1 Huang Rui 2021-12-24 1340
ec437d71db77a1 Huang Rui 2021-12-24 1341 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
ec437d71db77a1 Huang Rui 2021-12-24 1342 return -ENODEV;
202e683df37cdf Perry Yuan 2022-11-17 1343 /*
202e683df37cdf Perry Yuan 2022-11-17 1344 * by default the pstate driver is disabled to load
202e683df37cdf Perry Yuan 2022-11-17 1345 * enable the amd_pstate passive mode driver explicitly
36c5014e546096 Wyes Karny 2023-01-31 1346 * with amd_pstate=passive or other modes in kernel command line
202e683df37cdf Perry Yuan 2022-11-17 1347 */
36c5014e546096 Wyes Karny 2023-01-31 1348 if (cppc_state == AMD_PSTATE_DISABLE) {
7af78020e28a53 Kai-Heng Feng 2023-02-23 1349 pr_info("driver load is disabled, boot with specific mode to enable this\n");
202e683df37cdf Perry Yuan 2022-11-17 1350 return -ENODEV;
202e683df37cdf Perry Yuan 2022-11-17 1351 }
ec437d71db77a1 Huang Rui 2021-12-24 1352
ec437d71db77a1 Huang Rui 2021-12-24 1353 if (!acpi_cpc_valid()) {
a2a9d1850060e5 Perry Yuan 2022-08-15 1354 pr_warn_once("the _CPC object is not present in SBIOS or ACPI disabled\n");
ec437d71db77a1 Huang Rui 2021-12-24 1355 return -ENODEV;
ec437d71db77a1 Huang Rui 2021-12-24 1356 }
ec437d71db77a1 Huang Rui 2021-12-24 1357
ec437d71db77a1 Huang Rui 2021-12-24 1358 /* don't keep reloading if cpufreq_driver exists */
ec437d71db77a1 Huang Rui 2021-12-24 1359 if (cpufreq_get_current_driver())
ec437d71db77a1 Huang Rui 2021-12-24 1360 return -EEXIST;
ec437d71db77a1 Huang Rui 2021-12-24 1361
ec437d71db77a1 Huang Rui 2021-12-24 1362 /* capability check */
e059c184da47e9 Huang Rui 2021-12-24 1363 if (boot_cpu_has(X86_FEATURE_CPPC)) {
e059c184da47e9 Huang Rui 2021-12-24 1364 pr_debug("AMD CPPC MSR based functionality is supported\n");
2dd6d0ebf74049 Wyes Karny 2023-03-07 1365 if (cppc_state != AMD_PSTATE_ACTIVE)
ffa5096a7c3386 Perry Yuan 2023-01-31 1366 current_pstate_driver->adjust_perf = amd_pstate_adjust_perf;
202e683df37cdf Perry Yuan 2022-11-17 1367 } else {
202e683df37cdf Perry Yuan 2022-11-17 1368 pr_debug("AMD CPPC shared memory based functionality is supported\n");
e059c184da47e9 Huang Rui 2021-12-24 1369 static_call_update(amd_pstate_enable, cppc_enable);
e059c184da47e9 Huang Rui 2021-12-24 1370 static_call_update(amd_pstate_init_perf, cppc_init_perf);
e059c184da47e9 Huang Rui 2021-12-24 1371 static_call_update(amd_pstate_update_perf, cppc_update_perf);
ec437d71db77a1 Huang Rui 2021-12-24 1372 }
ec437d71db77a1 Huang Rui 2021-12-24 1373
ec437d71db77a1 Huang Rui 2021-12-24 @1374 if (ret) {
ffa5096a7c3386 Perry Yuan 2023-01-31 1375 pr_err("failed to enable with return %d\n", ret);
ec437d71db77a1 Huang Rui 2021-12-24 1376 return ret;
ec437d71db77a1 Huang Rui 2021-12-24 1377 }
ec437d71db77a1 Huang Rui 2021-12-24 1378
ffa5096a7c3386 Perry Yuan 2023-01-31 1379 ret = cpufreq_register_driver(current_pstate_driver);
ec437d71db77a1 Huang Rui 2021-12-24 1380 if (ret)
ffa5096a7c3386 Perry Yuan 2023-01-31 1381 pr_err("failed to register with return %d\n", ret);
ec437d71db77a1 Huang Rui 2021-12-24 1382
3666062b87ec8b Greg Kroah-Hartman 2023-03-13 1383 dev_root = bus_get_dev_root(&cpu_subsys);
3666062b87ec8b Greg Kroah-Hartman 2023-03-13 1384 if (dev_root) {
3666062b87ec8b Greg Kroah-Hartman 2023-03-13 1385 ret = sysfs_create_group(&dev_root->kobj, &amd_pstate_global_attr_group);
3666062b87ec8b Greg Kroah-Hartman 2023-03-13 1386 put_device(dev_root);
abd61c08ef349a Perry Yuan 2023-01-31 1387 if (ret) {
abd61c08ef349a Perry Yuan 2023-01-31 1388 pr_err("sysfs attribute export failed with error %d.\n", ret);
abd61c08ef349a Perry Yuan 2023-01-31 1389 goto global_attr_free;
abd61c08ef349a Perry Yuan 2023-01-31 1390 }
3666062b87ec8b Greg Kroah-Hartman 2023-03-13 1391 }
abd61c08ef349a Perry Yuan 2023-01-31 1392
abd61c08ef349a Perry Yuan 2023-01-31 1393 return ret;
abd61c08ef349a Perry Yuan 2023-01-31 1394
abd61c08ef349a Perry Yuan 2023-01-31 1395 global_attr_free:
abd61c08ef349a Perry Yuan 2023-01-31 1396 cpufreq_unregister_driver(current_pstate_driver);
ec437d71db77a1 Huang Rui 2021-12-24 1397 return ret;
ec437d71db77a1 Huang Rui 2021-12-24 1398 }
456ca88d8a5258 Perry Yuan 2022-11-17 1399 device_initcall(amd_pstate_init);
ec437d71db77a1 Huang Rui 2021-12-24 1400

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki


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