Hello,
This series adds initial support for the Marvell PXA1908 SoC and
"samsung,coreprimevelte", a smartphone using the SoC.
USB works and the phone can boot a rootfs from an SD card, but there are
some warnings in the dmesg:
During SMP initialization:
[ 0.006519] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU1: 0x00000000000000
[ 0.006542] CPU features: Unsupported CPU feature variation detected.
[ 0.006589] CPU1: Booted secondary processor 0x0000000001 [0x410fd032]
[ 0.010710] Detected VIPT I-cache on CPU2
[ 0.010716] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU2: 0x00000000000000
[ 0.010758] CPU2: Booted secondary processor 0x0000000002 [0x410fd032]
[ 0.014849] Detected VIPT I-cache on CPU3
[ 0.014855] CPU features: SANITY CHECK: Unexpected variation in SYS_CNTFRQ_EL0. Boot CPU: 0x000000018cba80, CPU3: 0x00000000000000
[ 0.014895] CPU3: Booted secondary processor 0x0000000003 [0x410fd032]
SMMU probing fails:
[ 0.101798] arm-smmu c0010000.iommu: probing hardware configuration...
[ 0.101809] arm-smmu c0010000.iommu: SMMUv1 with:
[ 0.101816] arm-smmu c0010000.iommu: no translation support!
On Samsung's PXA1908 phones, the bootloader does not start the ARM
system timer, and my temporary solution (which isn't present in this
series) was to put the code for starting the timer in the clock driver.
Would this hack be accepted upstream in the form of a platform or
clocksource driver such as drivers/clocksource/timer-mediatek-cpux.c?
A 3.14 based Marvell tree is available on GitHub
acorn-marvell/brillo_pxa_kernel, and a Samsung one on GitHub
CoderCharmander/g361f-kernel.
Andreas Färber attempted to upstream support for this SoC in 2017:
https://lore.kernel.org/lkml/[email protected]/
Duje Mihanović (10):
tty: serial: 8250: Define earlycon for mrvl,mmp-uart
gpio: pxa: use dynamic allocation of base
gpio: pxa: make pxa_gpio_has_pinctrl return false for MMP_GPIO
clk: mmp: Add Marvell PXA1908 clock driver
dt-bindings: clock: Add Marvell PXA1908 clock bindings
dt-bindings: clock: Add documentation for Marvell PXA1908
arm64: Kconfig.platforms: Add config for Marvell PXA1908 platform
arm64: dts: Add DTS for Marvell PXA1908 and samsung,coreprimevelte
dt-bindings: marvell: Document PXA1908 SoC
MAINTAINERS: add myself as Marvell PXA1908 maintainer
.../bindings/arm/marvell/marvell,pxa1908.yaml | 33 ++
.../bindings/clock/marvell,pxa1908.yaml | 53 +++
MAINTAINERS | 10 +
arch/arm64/Kconfig.platforms | 11 +
arch/arm64/boot/dts/marvell/Makefile | 1 +
.../pxa1908-samsung-coreprimevelte.dts | 321 ++++++++++++++++++
arch/arm64/boot/dts/marvell/pxa1908.dtsi | 298 ++++++++++++++++
drivers/clk/mmp/Makefile | 2 +-
drivers/clk/mmp/clk-of-pxa1908.c | 282 +++++++++++++++
drivers/gpio/gpio-pxa.c | 2 +
drivers/tty/serial/8250/8250_pxa.c | 1 +
include/dt-bindings/clock/marvell,pxa1908.h | 93 +++++
12 files changed, 1106 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
create mode 100644 Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
create mode 100644 arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
create mode 100644 arch/arm64/boot/dts/marvell/pxa1908.dtsi
create mode 100644 drivers/clk/mmp/clk-of-pxa1908.c
create mode 100644 include/dt-bindings/clock/marvell,pxa1908.h
--
2.41.0
Fixes the incorrect assumption that mmp-gpio needs a pinctrl handle,
causing devices consuming GPIO to be indefinitely deferred.
Signed-off-by: Duje Mihanović <[email protected]>
---
drivers/gpio/gpio-pxa.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 076ee6dff4d5..b48d142b736d 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -238,6 +238,7 @@ static bool pxa_gpio_has_pinctrl(void)
switch (gpio_type) {
case PXA3XX_GPIO:
case MMP2_GPIO:
+ case MMP_GPIO:
return false;
default:
--
2.41.0
Add dt bindings and documentation for Marvell PXA1908 SoC.
Signed-off-by: Duje Mihanović <[email protected]>
---
.../bindings/arm/marvell/marvell,pxa1908.yaml | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
new file mode 100644
index 000000000000..085d238129ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/marvell/pxa1908.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell PXA1908 Platforms
+
+maintainers:
+ - Duje Mihanović <[email protected]>
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - samsung,coreprimevelte
+ - const: marvell,pxa1908
+
+ pxa,rev-id:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ oneOf:
+ - items:
+ - description: Board ID
+ - description: Board revision
+ description: |
+ Some bootloaders use this property to determine whether the provided dt
+ blob is compatible with a specific device. For example, Samsung's S-Boot
+ is known to require this property.
+
+additionalProperties: false
--
2.41.0
Fixes the warning in dmesg that static allocation of the base is
deprecated.
Signed-off-by: Duje Mihanović <[email protected]>
---
drivers/gpio/gpio-pxa.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index a1630ed4b741..076ee6dff4d5 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -350,6 +350,7 @@ static int pxa_init_gpio_chip(struct pxa_gpio_chip *pchip, int ngpio, void __iom
pchip->chip.parent = pchip->dev;
pchip->chip.label = "gpio-pxa";
+ pchip->chip.base = -1;
pchip->chip.direction_input = pxa_gpio_direction_input;
pchip->chip.direction_output = pxa_gpio_direction_output;
pchip->chip.get = pxa_gpio_get;
--
2.41.0
Add driver for Marvell PXA1908 clock controller blocks. The SoC has
numerous clock controller blocks, currently supporting APBC, APBCP, MPMU
and APMU.
Signed-off-by: Duje Mihanović <[email protected]>
---
drivers/clk/mmp/Makefile | 2 +-
drivers/clk/mmp/clk-of-pxa1908.c | 282 +++++++++++++++++++++++++++++++
2 files changed, 283 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/mmp/clk-of-pxa1908.c
diff --git a/drivers/clk/mmp/Makefile b/drivers/clk/mmp/Makefile
index cbcc2f8430a2..feacddb28fc4 100644
--- a/drivers/clk/mmp/Makefile
+++ b/drivers/clk/mmp/Makefile
@@ -15,4 +15,4 @@ obj-$(CONFIG_CPU_PXA168) += clk-pxa168.o
obj-$(CONFIG_CPU_PXA910) += clk-pxa910.o
obj-$(CONFIG_CPU_MMP2) += clk-mmp2.o
-obj-y += clk-of-pxa1928.o
+obj-$(CONFIG_ARCH_MMP) += clk-of-pxa1928.o clk-of-pxa1908.o
diff --git a/drivers/clk/mmp/clk-of-pxa1908.c b/drivers/clk/mmp/clk-of-pxa1908.c
new file mode 100644
index 000000000000..58b3beca7b02
--- /dev/null
+++ b/drivers/clk/mmp/clk-of-pxa1908.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <linux/kernel.h>
+#include <linux/of_address.h>
+
+#include <dt-bindings/clock/marvell,pxa1908.h>
+
+#include "clk.h"
+
+#define APBC_INDEX_TO_OFFSET(n) ((n - 1) * 4)
+
+#define APMU_CLK_GATE_CTRL 0x40
+#define MPMU_UART_PLL 0x14
+
+struct pxa1908_clk_unit {
+ struct mmp_clk_unit unit;
+ void __iomem *mpmu_base;
+ void __iomem *apmu_base;
+ void __iomem *apbc_base;
+ void __iomem *apbcp_base;
+ void __iomem *apbs_base;
+ void __iomem *ciu_base;
+};
+
+static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
+ {PXA1908_CLK_CLK32, "clk32", NULL, 0, 32768},
+ {PXA1908_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
+ {PXA1908_CLK_PLL1_624, "pll1_624", NULL, 0, 624000000},
+ {PXA1908_CLK_PLL1_416, "pll1_416", NULL, 0, 416000000},
+ {PXA1908_CLK_PLL1_499, "pll1_499", NULL, 0, 499000000},
+ {PXA1908_CLK_PLL1_832, "pll1_832", NULL, 0, 832000000},
+ {PXA1908_CLK_PLL1_1248, "pll1_1248", NULL, 0, 1248000000},
+};
+
+static struct mmp_param_fixed_factor_clk fixed_factor_clks[] = {
+ {PXA1908_CLK_PLL1_D2, "pll1_d2", "pll1_624", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D4, "pll1_d4", "pll1_d2", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D6, "pll1_d6", "pll1_d2", 1, 3, 0},
+ {PXA1908_CLK_PLL1_D8, "pll1_d8", "pll1_d4", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D12, "pll1_d12", "pll1_d6", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D13, "pll1_d13", "pll1_624", 1, 13, 0},
+ {PXA1908_CLK_PLL1_D16, "pll1_d16", "pll1_d8", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D24, "pll1_d24", "pll1_d12", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D48, "pll1_d48", "pll1_d24", 1, 2, 0},
+ {PXA1908_CLK_PLL1_D96, "pll1_d96", "pll1_d48", 1, 2, 0},
+ {PXA1908_CLK_PLL1_32, "pll1_32", "pll1_d13", 2, 3, 0},
+ {PXA1908_CLK_PLL1_208, "pll1_208", "pll1_d2", 2, 3, 0},
+ {PXA1908_CLK_PLL1_117, "pll1_117", "pll1_624", 3, 16, 0},
+};
+
+static struct mmp_clk_factor_masks uart_factor_masks = {
+ .factor = 2,
+ .num_mask = 0x1fff,
+ .den_mask = 0x1fff,
+ .num_shift = 16,
+ .den_shift = 0,
+};
+
+static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
+ {.num = 8125, .den = 1536}, /* 14.745MHz */
+};
+
+static DEFINE_SPINLOCK(pll1_lock);
+static struct mmp_param_general_gate_clk pll1_gate_clks[] = {
+ {PXA1908_CLK_PLL1_D2_GATE, "pll1_d2_gate", "pll1_d2", 0, APMU_CLK_GATE_CTRL, 29, 0, &pll1_lock},
+ {PXA1908_CLK_PLL1_416_GATE, "pll1_416_gate", "pll1_416", 0, APMU_CLK_GATE_CTRL, 27, 0, &pll1_lock},
+ {PXA1908_CLK_PLL1_624_GATE, "pll1_624_gate", "pll1_624", 0, APMU_CLK_GATE_CTRL, 26, 0, &pll1_lock},
+ {PXA1908_CLK_PLL1_832_GATE, "pll1_832_gate", "pll1_832", 0, APMU_CLK_GATE_CTRL, 30, 0, &pll1_lock},
+ {PXA1908_CLK_PLL1_1248_GATE, "pll1_1248_gate", "pll1_1248", 0, APMU_CLK_GATE_CTRL, 28, 0, &pll1_lock},
+};
+
+static void pxa1908_pll_init(struct pxa1908_clk_unit *pxa_unit)
+{
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+ mmp_register_fixed_rate_clks(unit, fixed_rate_clks,
+ ARRAY_SIZE(fixed_rate_clks));
+
+ mmp_register_fixed_factor_clks(unit, fixed_factor_clks,
+ ARRAY_SIZE(fixed_factor_clks));
+
+ mmp_clk_register_factor("uart_pll", "pll1_d4",
+ CLK_SET_RATE_PARENT,
+ pxa_unit->mpmu_base + MPMU_UART_PLL,
+ &uart_factor_masks, uart_factor_tbl,
+ ARRAY_SIZE(uart_factor_tbl), NULL);
+
+}
+
+static DEFINE_SPINLOCK(pwm0_lock);
+static DEFINE_SPINLOCK(pwm2_lock);
+
+static DEFINE_SPINLOCK(uart0_lock);
+static DEFINE_SPINLOCK(uart1_lock);
+static DEFINE_SPINLOCK(uart2_lock);
+
+static const char * const uart_parent_names[] = {"pll1_117", "uart_pll"};
+static const char * const ssp_parent_names[] = {"pll1_d16", "pll1_d48", "pll1_d24", "pll1_d12"};
+
+static struct mmp_param_gate_clk apbc_gate_clks[] = {
+ {PXA1908_CLK_TWSI0, "twsi0_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_TWSI0), 0x7, 3, 0, 0, NULL},
+ {PXA1908_CLK_TWSI1, "twsi1_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_TWSI1), 0x7, 3, 0, 0, NULL},
+ {PXA1908_CLK_TWSI3, "twsi3_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_TWSI3), 0x7, 3, 0, 0, NULL},
+ {PXA1908_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_GPIO), 0x7, 3, 0, 0, NULL},
+ {PXA1908_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_KPC), 0x7, 3, 0, MMP_CLK_GATE_NEED_DELAY, NULL},
+ {PXA1908_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_RTC), 0x87, 0x83, 0, MMP_CLK_GATE_NEED_DELAY, NULL},
+ {PXA1908_CLK_PWM0, "pwm0_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_PWM0), 0x2, 2, 0, 0, &pwm0_lock},
+ {PXA1908_CLK_PWM1, "pwm1_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_PWM1), 0x6, 2, 0, 0, NULL},
+ {PXA1908_CLK_PWM2, "pwm2_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_PWM2), 0x2, 2, 0, 0, NULL},
+ {PXA1908_CLK_PWM3, "pwm3_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_PWM3), 0x6, 2, 0, 0, NULL},
+ {PXA1908_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_UART0), 0x7, 3, 0, 0, &uart0_lock},
+ {PXA1908_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_UART1), 0x7, 3, 0, 0, &uart1_lock},
+};
+
+static struct mmp_param_mux_clk apbc_mux_clks[] = {
+ {0, "uart0_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_UART0), 4, 3, 0, &uart0_lock},
+ {0, "uart1_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, APBC_INDEX_TO_OFFSET(PXA1908_CLK_UART1), 4, 3, 0, &uart1_lock},
+ {0, "ssp0_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), 0, APBC_INDEX_TO_OFFSET(PXA1908_CLK_SSP0), 4, 3, 0, NULL},
+ {0, "ssp2_mux", ssp_parent_names, ARRAY_SIZE(ssp_parent_names), 0, APBC_INDEX_TO_OFFSET(PXA1908_CLK_SSP2), 4, 3, 0, NULL},
+};
+
+static void pxa1908_apb_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
+{
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+ mmp_clk_register_gate(NULL, "pwm01_apb_share", "pll1_d48",
+ CLK_SET_RATE_PARENT,
+ pxa_unit->apbc_base + PXA1908_CLK_PWM0 * 4,
+ 0x5, 1, 0, 0, &pwm0_lock);
+ mmp_clk_register_gate(NULL, "pwm23_apb_share", "pll1_d48",
+ CLK_SET_RATE_PARENT,
+ pxa_unit->apbc_base + PXA1908_CLK_PWM2 * 4,
+ 0x5, 1, 0, 0, &pwm2_lock);
+ mmp_register_mux_clks(unit, apbc_mux_clks, pxa_unit->apbc_base,
+ ARRAY_SIZE(apbc_mux_clks));
+ mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->apbc_base,
+ ARRAY_SIZE(apbc_gate_clks));
+}
+
+static struct mmp_param_gate_clk apbcp_gate_clks[] = {
+ {PXA1908_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, PXA1908_CLK_UART2 * 4, 0x7, 0x3, 0x0, 0, &uart2_lock},
+ {PXA1908_CLK_TWSI2, "twsi2_clk", "pll1_32", CLK_SET_RATE_PARENT, PXA1908_CLK_TWSI2 * 4, 0x7, 0x3, 0x0, 0, NULL},
+ {PXA1908_CLK_AICER, "ripc_clk", NULL, 0, PXA1908_CLK_AICER * 4, 0x7, 0x2, 0x0, 0, NULL},
+};
+
+static struct mmp_param_mux_clk apbcp_mux_clks[] = {
+ {0, "uart2_mux", uart_parent_names, ARRAY_SIZE(uart_parent_names), CLK_SET_RATE_PARENT, PXA1908_CLK_UART2 * 4, 4, 3, 0, &uart2_lock},
+};
+
+static void pxa1908_apb_p_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
+{
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+ mmp_register_mux_clks(unit, apbcp_mux_clks, pxa_unit->apbcp_base,
+ ARRAY_SIZE(apbcp_mux_clks));
+ mmp_register_gate_clks(unit, apbcp_gate_clks, pxa_unit->apbcp_base,
+ ARRAY_SIZE(apbcp_gate_clks));
+}
+
+static DEFINE_SPINLOCK(sdh0_lock);
+static DEFINE_SPINLOCK(sdh1_lock);
+static DEFINE_SPINLOCK(sdh2_lock);
+
+static const char * const sdh_parent_names[] = {"pll1_416", "pll1_624"};
+
+static struct mmp_clk_mix_config sdh_mix_config = {
+ .reg_info = DEFINE_MIX_REG_INFO(3, 8, 2, 6, 11),
+};
+
+static struct mmp_param_gate_clk apmu_gate_clks[] = {
+ {PXA1908_CLK_USB, "usb_clk", NULL, 0, PXA1908_CLK_USB * 4, 0x9, 0x9, 0x1, 0, NULL},
+ {PXA1908_CLK_SDH0, "sdh0_clk", "sdh0_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, PXA1908_CLK_SDH0 * 4, 0x12, 0x12, 0x0, 0, &sdh0_lock},
+ {PXA1908_CLK_SDH1, "sdh1_clk", "sdh1_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, PXA1908_CLK_SDH1 * 4, 0x12, 0x12, 0x0, 0, &sdh1_lock},
+ {PXA1908_CLK_SDH2, "sdh2_clk", "sdh2_mix_clk", CLK_SET_RATE_PARENT | CLK_SET_RATE_UNGATE, PXA1908_CLK_SDH2 * 4, 0x12, 0x12, 0x0, 0, &sdh2_lock}
+};
+
+static void pxa1908_axi_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
+{
+ struct mmp_clk_unit *unit = &pxa_unit->unit;
+
+ mmp_register_general_gate_clks(unit, pll1_gate_clks,
+ pxa_unit->apmu_base, ARRAY_SIZE(pll1_gate_clks));
+
+ sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + PXA1908_CLK_SDH0 * 4;
+ mmp_clk_register_mix(NULL, "sdh0_mix_clk", sdh_parent_names,
+ ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
+ &sdh_mix_config, &sdh0_lock);
+ sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + PXA1908_CLK_SDH1 * 4;
+ mmp_clk_register_mix(NULL, "sdh1_mix_clk", sdh_parent_names,
+ ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
+ &sdh_mix_config, &sdh1_lock);
+ sdh_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + PXA1908_CLK_SDH2 * 4;
+ mmp_clk_register_mix(NULL, "sdh2_mix_clk", sdh_parent_names,
+ ARRAY_SIZE(sdh_parent_names), CLK_SET_RATE_PARENT,
+ &sdh_mix_config, &sdh2_lock);
+
+ mmp_register_gate_clks(unit, apmu_gate_clks, pxa_unit->apmu_base,
+ ARRAY_SIZE(apmu_gate_clks));
+}
+
+static void __init pxa1908_apbc_clk_init(struct device_node *np)
+{
+ struct pxa1908_clk_unit *pxa_unit;
+
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+ if (!pxa_unit)
+ return;
+
+ pxa_unit->apbc_base = of_iomap(np, 0);
+ if (!pxa_unit->apbc_base) {
+ pr_err("failed to map apbc registers\n");
+ kfree(pxa_unit);
+ return;
+ }
+
+ mmp_clk_init(np, &pxa_unit->unit, PXA1908_APBC_NR_CLKS);
+
+ pxa1908_apb_periph_clk_init(pxa_unit);
+}
+CLK_OF_DECLARE(pxa1908_apbc, "marvell,pxa1908-apbc", pxa1908_apbc_clk_init);
+
+static void __init pxa1908_apbcp_clk_init(struct device_node *np)
+{
+ struct pxa1908_clk_unit *pxa_unit;
+
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+ if (!pxa_unit)
+ return;
+
+ pxa_unit->apbcp_base = of_iomap(np, 0);
+ if (!pxa_unit->apbcp_base) {
+ pr_err("failed to map apbcp registers\n");
+ kfree(pxa_unit);
+ return;
+ }
+
+ mmp_clk_init(np, &pxa_unit->unit, PXA1908_APBCP_NR_CLKS);
+
+ pxa1908_apb_p_periph_clk_init(pxa_unit);
+}
+CLK_OF_DECLARE(pxa1908_apbcp, "marvell,pxa1908-apbcp", pxa1908_apbcp_clk_init);
+
+static void __init pxa1908_mpmu_clk_init(struct device_node *np)
+{
+ struct pxa1908_clk_unit *pxa_unit;
+
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+ if (!pxa_unit)
+ return;
+
+ pxa_unit->mpmu_base = of_iomap(np, 0);
+ if (!pxa_unit->mpmu_base) {
+ pr_err("failed to map mpmu registers\n");
+ kfree(pxa_unit);
+ return;
+ }
+
+ mmp_clk_init(np, &pxa_unit->unit, PXA1908_MPMU_NR_CLKS);
+
+ pxa1908_pll_init(pxa_unit);
+}
+CLK_OF_DECLARE(pxa1908_mpmu, "marvell,pxa1908-mpmu", pxa1908_mpmu_clk_init);
+
+static void __init pxa1908_apmu_clk_init(struct device_node *np)
+{
+ struct pxa1908_clk_unit *pxa_unit;
+
+ pxa_unit = kzalloc(sizeof(*pxa_unit), GFP_KERNEL);
+ if (!pxa_unit)
+ return;
+
+ pxa_unit->apmu_base = of_iomap(np, 0);
+ if (!pxa_unit->apmu_base) {
+ pr_err("failed to map apmu registers\n");
+ kfree(pxa_unit);
+ return;
+ }
+
+ mmp_clk_init(np, &pxa_unit->unit, PXA1908_APMU_NR_CLKS);
+
+ pxa1908_axi_periph_clk_init(pxa_unit);
+}
+CLK_OF_DECLARE(pxa1908_apmu, "marvell,pxa1908-apmu", pxa1908_apmu_clk_init);
--
2.41.0
mrvl,pxa-uart already supports earlycon and both compatible strings use
the same driver, so there's no reason for mmp-uart to not have earlycon
as well.
Signed-off-by: Duje Mihanović <[email protected]>
---
drivers/tty/serial/8250/8250_pxa.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/tty/serial/8250/8250_pxa.c b/drivers/tty/serial/8250/8250_pxa.c
index 28b341f602c6..a5b3ea27fc90 100644
--- a/drivers/tty/serial/8250/8250_pxa.c
+++ b/drivers/tty/serial/8250/8250_pxa.c
@@ -183,6 +183,7 @@ static int __init early_serial_pxa_setup(struct earlycon_device *device,
return early_serial8250_setup(device, NULL);
}
OF_EARLYCON_DECLARE(early_pxa, "mrvl,pxa-uart", early_serial_pxa_setup);
+OF_EARLYCON_DECLARE(mmp, "mrvl,mmp-uart", early_serial_pxa_setup);
#endif
MODULE_AUTHOR("Sergei Ianovich");
--
2.41.0
Add the dt bindings for Marvell PXA1908 clock controller.
Signed-off-by: Duje Mihanović <[email protected]>
---
include/dt-bindings/clock/marvell,pxa1908.h | 93 +++++++++++++++++++++
1 file changed, 93 insertions(+)
create mode 100644 include/dt-bindings/clock/marvell,pxa1908.h
diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindings/clock/marvell,pxa1908.h
new file mode 100644
index 000000000000..da9c5d499ae4
--- /dev/null
+++ b/include/dt-bindings/clock/marvell,pxa1908.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __DTS_MARVELL_PXA1908_CLOCK_H
+#define __DTS_MARVELL_PXA1908_CLOCK_H
+
+/* plls */
+#define PXA1908_CLK_CLK32 0x1
+#define PXA1908_CLK_VCTCXO 0x2
+#define PXA1908_CLK_PLL1_624 0x3
+#define PXA1908_CLK_PLL1_416 0x4
+#define PXA1908_CLK_PLL1_499 0x5
+#define PXA1908_CLK_PLL1_832 0x6
+#define PXA1908_CLK_PLL1_1248 0x7
+#define PXA1908_CLK_PLL1_D2 0x8
+#define PXA1908_CLK_PLL1_D4 0x9
+#define PXA1908_CLK_PLL1_D8 0xa
+#define PXA1908_CLK_PLL1_D16 0xb
+#define PXA1908_CLK_PLL1_D6 0xc
+#define PXA1908_CLK_PLL1_D12 0xd
+#define PXA1908_CLK_PLL1_D24 0xe
+#define PXA1908_CLK_PLL1_D48 0xf
+#define PXA1908_CLK_PLL1_D96 0x10
+#define PXA1908_CLK_PLL1_D13 0x11
+#define PXA1908_CLK_PLL1_32 0x12
+#define PXA1908_CLK_PLL1_208 0x13
+#define PXA1908_CLK_PLL1_117 0x14
+#define PXA1908_CLK_PLL1_416_GATE 0x15
+#define PXA1908_CLK_PLL1_624_GATE 0x16
+#define PXA1908_CLK_PLL1_832_GATE 0x17
+#define PXA1908_CLK_PLL1_1248_GATE 0x18
+#define PXA1908_CLK_PLL1_D2_GATE 0x19
+#define PXA1908_CLK_PLL1_499_EN 0x1a
+#define PXA1908_CLK_PLL2VCO 0x1b
+#define PXA1908_CLK_PLL2 0x1c
+#define PXA1908_CLK_PLL2P 0x1d
+#define PXA1908_CLK_PLL2VCODIV3 0x1e
+#define PXA1908_CLK_PLL3VCO 0x1f
+#define PXA1908_CLK_PLL3 0x20
+#define PXA1908_CLK_PLL3P 0x21
+#define PXA1908_CLK_PLL3VCODIV3 0x22
+#define PXA1908_CLK_PLL4VCO 0x23
+#define PXA1908_CLK_PLL4 0x24
+#define PXA1908_CLK_PLL4P 0x25
+#define PXA1908_CLK_PLL4VCODIV3 0x26
+#define PXA1908_MPMU_NR_CLKS 38
+
+/* apb (apbc) peripherals */
+#define PXA1908_CLK_UART0 0x1
+#define PXA1908_CLK_UART1 0x2
+#define PXA1908_CLK_GPIO 0x3
+#define PXA1908_CLK_PWM0 0x4
+#define PXA1908_CLK_PWM1 0x5
+#define PXA1908_CLK_PWM2 0x6
+#define PXA1908_CLK_PWM3 0x7
+#define PXA1908_CLK_SSP0 0x8
+#define PXA1908_CLK_SSP1 0x9
+#define PXA1908_CLK_IPC_RST 0xa
+#define PXA1908_CLK_RTC 0xb
+#define PXA1908_CLK_TWSI0 0xc
+#define PXA1908_CLK_KPC 0xd
+#define PXA1908_CLK_SWJTAG 0x11
+#define PXA1908_CLK_SSP2 0x14
+#define PXA1908_CLK_TWSI1 0x19
+#define PXA1908_CLK_THERMAL 0x1c
+#define PXA1908_CLK_TWSI3 0x1d
+#define PXA1908_APBC_NR_CLKS 0x30
+
+/* apb (apbcp) peripherals */
+#define PXA1908_CLK_UART2 0x7
+#define PXA1908_CLK_TWSI2 0xa
+#define PXA1908_CLK_AICER 0xe
+#define PXA1908_APBCP_NR_CLKS 0xe
+
+/* axi (apmu) peripherals */
+#define PXA1908_CLK_CCIC1 0x9
+#define PXA1908_CLK_ISP 0xe
+#define PXA1908_CLK_GATE_CTRL 0x10
+#define PXA1908_CLK_DSI1 0x11
+#define PXA1908_CLK_DISP1 0x13
+#define PXA1908_CLK_CCIC0 0x14
+#define PXA1908_CLK_SDH0 0x15
+#define PXA1908_CLK_SDH1 0x16
+#define PXA1908_CLK_SDH2 0x38
+#define PXA1908_CLK_USB 0x17
+#define PXA1908_CLK_NF 0x18
+#define PXA1908_CLK_CORE_DEBUG 0x24
+#define PXA1908_CLK_VPU 0x29
+#define PXA1908_CLK_GC 0x51
+#define PXA1908_CLK_GC2D 0x3d
+#define PXA1908_CLK_TRACE 0x42
+#define PXA1908_CLK_DVC_DFC_DEBUG 0x50
+#define PXA1908_APMU_NR_CLKS 0x60
+
+#endif
--
2.41.0
Add myself as the maintainer for Marvell PXA1908 SoC support.
Signed-off-by: Duje Mihanović <[email protected]>
---
MAINTAINERS | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index aee340630eca..263fd6db0f7b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2297,6 +2297,16 @@ F: drivers/irqchip/irq-mvebu-*
F: drivers/pinctrl/mvebu/
F: drivers/rtc/rtc-armada38x.c
+ARM/Marvell PXA1908 SOC support
+M: Duje Mihanović <[email protected]>
+L: [email protected] (moderated for non-subscribers)
+S: Maintained
+T: git https://gitlab.com/LegoLivesMatter/linux
+F: Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
+F: arch/arm64/boot/dts/marvell/pxa1908*
+F: drivers/clk/mmp/clk-of-pxa1908.c
+F: include/dt-bindings/clock/marvell,pxa1908.h
+
ARM/Mediatek RTC DRIVER
M: Eddie Huang <[email protected]>
M: Sean Wang <[email protected]>
--
2.41.0
Add DTS for Marvell PXA1908 SoC and Samsung Galaxy Core Prime Value
Edition LTE, a smartphone based on said SoC.
Signed-off-by: Duje Mihanović <[email protected]>
---
arch/arm64/boot/dts/marvell/Makefile | 1 +
.../pxa1908-samsung-coreprimevelte.dts | 321 ++++++++++++++++++
arch/arm64/boot/dts/marvell/pxa1908.dtsi | 298 ++++++++++++++++
3 files changed, 620 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
create mode 100644 arch/arm64/boot/dts/marvell/pxa1908.dtsi
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index 79ac09b58a89..0e277a0d368b 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -27,3 +27,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
+dtb-$(CONFIG_ARCH_MMP) += pxa1908-samsung-coreprimevelte.dtb
diff --git a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
new file mode 100644
index 000000000000..3e10a77a106e
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include "pxa1908.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+
+/ {
+ pxa,rev-id = <3928 2>;
+ model = "Samsung Galaxy Core Prime VE LTE";
+ compatible = "samsung,coreprimevelte", "marvell,pxa1908";
+
+ /* Bootloader fills this in */
+ memory {
+ device_type = "memory";
+ reg = <0 0 0 0>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer@17000000 {
+ reg = <0 0x17000000 0 0x1800000>;
+ no-map;
+ };
+
+ gpu@9000000 {
+ reg = <0 0x9000000 0 0x1000000>;
+ };
+
+ /* Communications processor, aka modem */
+ cp@3000000 {
+ reg = <0 0x3000000 0 0x5000000>;
+ };
+
+ cm3@a000000 {
+ reg = <0 0xa000000 0 0x80000>;
+ };
+
+ seclog@8000000 {
+ reg = <0 0x8000000 0 0x100000>;
+ };
+
+ ramoops@8100000 {
+ compatible = "ramoops";
+ reg = <0 0x8100000 0 0x40000>;
+ record-size = <0x8000>;
+ console-size = <0x20000>;
+ max-reason = <5>;
+ };
+ };
+
+ fb0: framebuffer@17177000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0x17177000 0 (480 * 800 * 4)>;
+ width = <480>;
+ height = <800>;
+ stride = <(480 * 4)>;
+ format = "a8r8g8b8";
+ };
+
+ muic-i2c {
+ compatible = "i2c-gpio";
+ sda-gpios = <&gpio 30 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&gpio 29 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <3>;
+ i2c-gpio,timeout-ms = <100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&muic_i2c_pins>;
+
+ muic: extcon@14 {
+ compatible = "siliconmitus,sm5504-muic";
+ reg = <0x14>;
+ interrupt-parent = <&gpio>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio_keys_pins>;
+ autorepeat;
+
+ key-home {
+ label = "Home";
+ linux,code = <KEY_HOME>;
+ gpios = <&gpio 50 GPIO_ACTIVE_LOW>;
+ };
+
+ key-volup {
+ label = "Volume Up";
+ linux,code = <KEY_VOLUMEUP>;
+ gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+ };
+
+ key-voldown {
+ label = "Volume Down";
+ linux,code = <KEY_VOLUMEDOWN>;
+ gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ chosen {};
+};
+
+&smmu {
+ status = "okay";
+};
+
+&pmx {
+ pinctrl-single,gpio-range = <&range 55 55 0>,
+ <&range 110 32 0>,
+ <&range 52 1 0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&board_pins_1 &board_pins_2 &board_pins_3>;
+
+ board_pins_1: pinmux_board_1 {
+ pinctrl-single,pins = <
+ 0x160 0
+ 0x164 0
+ 0x168 0
+ 0x16c 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0x8000 0x8000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0x8000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0x288 0x388>;
+ };
+
+ board_pins_2: pinmux_board_2 {
+ pinctrl-single,pins = <
+ 0x44 1
+ 0x48 1
+ 0x20 1
+ 0x18 1
+ 0x14 1
+ 0x10 1
+ 0xc 1
+ 0x8 1
+ 0x68 1
+ 0x58 0
+ 0x54 0
+ 0x7c 0
+ 0x6c 0
+ 0x70 0
+ 0x4c 1
+ 0x50 1
+ 0xac 0
+ 0x90 0
+ 0x8c 0
+ 0x88 0
+ 0x84 0
+ 0xc8 0
+ 0x128 0
+ 0x190 0
+ 0x194 0
+ 0x1a0 0
+ 0x114 0
+ 0x118 0
+ 0x1d8 0
+ 0x1e4 0
+ 0xe8 0
+ 0x100 0
+ 0x204 0
+ 0x210 0
+ 0x218 0
+ >;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xc000>;
+ pinctrl-single,low-power-mode = <0x288 0x388>;
+ };
+
+ board_pins_3: pinmux_board_3 {
+ pinctrl-single,pins = <
+ 0x260 0
+ 0x264 0
+ 0x268 0
+ 0x26c 0
+ 0x270 0
+ 0x274 0
+ 0x78 0
+ 0x74 0
+ 0xb0 1
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ uart0_pins: pinmux_uart0 {
+ pinctrl-single,pins = <
+ 0x198 6
+ 0x19c 6
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ gpio_keys_pins: pinmux_gpio_keys {
+ pinctrl-single,pins = <
+ 0x11c 0
+ 0x120 0
+ 0x1a4 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa0000 0x8000 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ muic_i2c_pins: pinmux_muic_i2c {
+ pinctrl-single,pins = <
+ 0x154 0
+ 0x150 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0x288 0x388>;
+ };
+
+ sdh0_pins_1: pinmux_sdh0_1 {
+ pinctrl-single,pins = <
+ 0x108 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ sdh0_pins_2: pinmux_sdh0_2 {
+ pinctrl-single,pins = <
+ 0x94 0
+ 0x98 0
+ 0x9c 0
+ 0xa0 0
+ 0xa4 0
+ >;
+ pinctrl-single,drive-strength = <0x800 0x1800>;
+ pinctrl-single,bias-pullup = <0xc000 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0x8000 0xa000 0x8000 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0 0x388>;
+ };
+
+ sdh0_pins_3: pinmux_sdh0_3 {
+ pinctrl-single,pins = <
+ 0xa8 0
+ >;
+ pinctrl-single,drive-strength = <0x1000 0x1800>;
+ pinctrl-single,bias-pullup = <0 0xc000 0 0xc000>;
+ pinctrl-single,bias-pulldown = <0 0xa000 0 0xa000>;
+ pinctrl-single,input-schmitt = <0 0x30>;
+ pinctrl-single,input-schmitt-enable = <0x40 0 0x40 0x40>;
+ pinctrl-single,low-power-mode = <0x208 0x388>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+};
+
+&twsi0 {
+ status = "okay";
+};
+
+&twsi1 {
+ status = "okay";
+};
+
+&twsi2 {
+ status = "okay";
+};
+
+&twsi3 {
+ status = "okay";
+};
+
+&usb {
+ extcon = <&muic>, <&muic>;
+};
+
+&sdh2 {
+ /* Disabled for now because initialization fails with -ETIMEDOUT. */
+ status = "disabled";
+ bus-width = <8>;
+ non-removable;
+ broken-cd;
+ mmc-ddr-1_8v;
+};
+
+&sdh0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdh0_pins_1 &sdh0_pins_2 &sdh0_pins_3>;
+ cd-gpios = <&gpio 11 0>;
+ cd-inverted;
+ bus-width = <4>;
+ wp-inverted;
+};
diff --git a/arch/arm64/boot/dts/marvell/pxa1908.dtsi b/arch/arm64/boot/dts/marvell/pxa1908.dtsi
new file mode 100644
index 000000000000..7131b2070b72
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/pxa1908.dtsi
@@ -0,0 +1,298 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/marvell,pxa1908.h>
+
+/ {
+ model = "Marvell Armada PXA1908";
+ compatible = "marvell,pxa1908";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 0>;
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 1>;
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 2>;
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0 3>;
+ enable-method = "psci";
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ smmu: iommu@c0010000 {
+ compatible = "arm,mmu-400";
+ reg = <0 0xc0010000 0 0x10000>;
+ #global-interrupts = <1>;
+ #iommu-cells = <1>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ gic: interrupt-controller@d1df9000 {
+ compatible = "arm,gic-400";
+ reg = <0 0xd1df9000 0 0x1000>,
+ <0 0xd1dfa000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+
+ apb@d4000000 {
+ compatible = "simple-bus";
+ reg = <0 0xd4000000 0 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xd4000000 0x200000>;
+
+ pdma: dma-controller@0 {
+ compatible = "marvell,pdma-1.0";
+ reg = <0 0x10000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <30>;
+ #dma-cells = <2>;
+ };
+
+ twsi1: i2c@10800 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10800 0x64>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_TWSI1>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ twsi0: i2c@11000 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x11000 0x64>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_TWSI0>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ twsi3: i2c@13800 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x13800 0x64>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbc PXA1908_CLK_TWSI3>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ apbc: clock-controller@15000 {
+ compatible = "marvell,pxa1908-apbc";
+ reg = <0x15000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@17000 {
+ compatible = "mrvl,mmp-uart";
+ reg = <0x17000 0x1000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma 21 1>,
+ <&pdma 22 1>;
+ dma-names = "rx", "tx";
+ clocks = <&apbc PXA1908_CLK_UART0>;
+ };
+
+ uart1: serial@18000 {
+ compatible = "mrvl,mmp-uart";
+ reg = <0x18000 0x1000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma 23 1>,
+ <&pdma 24 1>;
+ dma-names = "rx", "tx";
+ clocks = <&apbc PXA1908_CLK_UART1>;
+ };
+
+ gpio: gpio@19000 {
+ compatible = "marvell,mmp-gpio";
+ reg = <0x19000 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&apbc PXA1908_CLK_GPIO>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpio_mux";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ranges = <0 0x19000 0x800>;
+
+ gpio@0 {
+ reg = <0x0 0x4>;
+ };
+
+ gpio@4 {
+ reg = <0x4 0x4>;
+ };
+
+ gpio@8 {
+ reg = <0x8 0x4>;
+ };
+
+ gpio@100 {
+ reg = <0x100 0x4>;
+ };
+ };
+
+ pmx: pinmux@1e000 {
+ compatible = "pinconf-single";
+ reg = <0x1e000 0x330>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #gpio-range-cells = <3>;
+ ranges;
+
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <7>;
+
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+ };
+
+ uart2: serial@36000 {
+ compatible = "mrvl,mmp-uart";
+ reg = <0x36000 0x1000>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma 4 1>,
+ <&pdma 5 1>;
+ dma-names = "rx", "tx";
+ clocks = <&apbcp PXA1908_CLK_UART2>;
+ };
+
+ twsi2: i2c@37000 {
+ compatible = "mrvl,mmp-twsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x37000 0x64>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apbcp PXA1908_CLK_TWSI2>;
+ mrvl,i2c-fast-mode;
+ status = "disabled";
+ };
+
+ apbcp: clock-controller@3b000 {
+ compatible = "marvell,pxa1908-apbcp";
+ reg = <0x3b000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ mpmu: clock-controller@50000 {
+ compatible = "marvell,pxa1908-mpmu";
+ reg = <0x50000 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+
+ axi@d4200000 {
+ compatible = "simple-bus";
+ reg = <0 0xd4200000 0 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0xd4200000 0x200000>;
+
+ usbphy: phy@7000 {
+ compatible = "marvell,pxa1928-usb-phy";
+ reg = <0x7000 0x200>;
+ clocks = <&apmu PXA1908_CLK_USB>;
+ #phy-cells = <0>;
+ };
+
+ usb: usb@8000 {
+ compatible = "chipidea,usb2";
+ reg = <0x8000 0x200>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_USB>;
+ phys = <&usbphy>;
+ phy-names = "usb-phy";
+ };
+
+ sdh0: mmc@80000 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0x80000 0x120>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_SDH0>;
+ clock-names = "io";
+ mrvl,clk-delay-cycles = <31>;
+ };
+
+ sdh1: mmc@80800 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0x80800 0x120>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_SDH1>;
+ clock-names = "io";
+ mrvl,clk-delay-cycles = <31>;
+ };
+
+ sdh2: mmc@81000 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0x81000 0x120>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&apmu PXA1908_CLK_SDH2>;
+ clock-names = "io";
+ mrvl,clk-delay-cycles = <31>;
+ };
+
+ apmu: clock-controller@82800 {
+ compatible = "marvell,pxa1908-apmu";
+ reg = <0x82800 0x400>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+};
--
2.41.0
Add ARCH_MMP configuration option for Marvell PXA1908 SoC.
Signed-off-by: Duje Mihanović <[email protected]>
---
arch/arm64/Kconfig.platforms | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 6069120199bb..b417cae42c84 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -89,6 +89,17 @@ config ARCH_BERLIN
help
This enables support for Marvell Berlin SoC Family
+config ARCH_MMP
+ bool "Marvell MMP SoC Family"
+ select ARM_GIC
+ select ARM_ARCH_TIMER
+ select ARM_SMMU
+ select MMP_PDMA
+ select PINCTRL_SINGLE
+ help
+ This enables support for Marvell MMP SoC family, currently
+ supporting PXA1908 aka IAP140.
+
config ARCH_BITMAIN
bool "Bitmain SoC Platforms"
help
--
2.41.0
On Fri, 21 Jul 2023 22:37:51 +0200, Duje Mihanović wrote:
> Add dt bindings and documentation for Marvell PXA1908 SoC.
>
> Signed-off-by: Duje Mihanović <[email protected]>
> ---
> .../bindings/arm/marvell/marvell,pxa1908.yaml | 33 +++++++++++++++++++
> 1 file changed, 33 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml: $id: Cannot determine base path from $id, relative path/filename doesn't match actual path or filename
$id: http://devicetree.org/schemas/arm/marvell/pxa1908.yaml
file: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/[email protected]
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
On 21/07/2023 22:37, Duje Mihanović wrote:
> Add the dt bindings for Marvell PXA1908 clock controller.
>
Squash the patch with bindings change. It has little sense on its own,
> Signed-off-by: Duje Mihanović <[email protected]>
> ---
> include/dt-bindings/clock/marvell,pxa1908.h | 93 +++++++++++++++++++++
> 1 file changed, 93 insertions(+)
> create mode 100644 include/dt-bindings/clock/marvell,pxa1908.h
>
> diff --git a/include/dt-bindings/clock/marvell,pxa1908.h b/include/dt-bindings/clock/marvell,pxa1908.h
> new file mode 100644
> index 000000000000..da9c5d499ae4
> --- /dev/null
> +++ b/include/dt-bindings/clock/marvell,pxa1908.h
> @@ -0,0 +1,93 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
Dual license. Didn't checkpatch complain?
> +#ifndef __DTS_MARVELL_PXA1908_CLOCK_H
> +#define __DTS_MARVELL_PXA1908_CLOCK_H
> +
> +/* plls */
> +#define PXA1908_CLK_CLK32 0x1
> +#define PXA1908_CLK_VCTCXO 0x2
> +#define PXA1908_CLK_PLL1_624 0x3
IDs are decimal numbers.
> +#define PXA1908_CLK_PLL1_416 0x4
> +#define PXA1908_CLK_PLL1_499 0x5
> +#define PXA1908_CLK_PLL1_832 0x6
> +#define PXA1908_CLK_PLL1_1248 0x7
> +#define PXA1908_CLK_PLL1_D2 0x8
Best regards,
Krzysztof
On 21/07/2023 22:37, Duje Mihanović wrote:
> Add DTS for Marvell PXA1908 SoC and Samsung Galaxy Core Prime Value
> Edition LTE, a smartphone based on said SoC.
>
> Signed-off-by: Duje Mihanović <[email protected]>
> ---
> arch/arm64/boot/dts/marvell/Makefile | 1 +
> .../pxa1908-samsung-coreprimevelte.dts | 321 ++++++++++++++++++
> arch/arm64/boot/dts/marvell/pxa1908.dtsi | 298 ++++++++++++++++
> 3 files changed, 620 insertions(+)
> create mode 100644 arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
> create mode 100644 arch/arm64/boot/dts/marvell/pxa1908.dtsi
>
> diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
> index 79ac09b58a89..0e277a0d368b 100644
> --- a/arch/arm64/boot/dts/marvell/Makefile
> +++ b/arch/arm64/boot/dts/marvell/Makefile
> @@ -27,3 +27,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
> +dtb-$(CONFIG_ARCH_MMP) += pxa1908-samsung-coreprimevelte.dtb
> diff --git a/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
> new file mode 100644
> index 000000000000..3e10a77a106e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/marvell/pxa1908-samsung-coreprimevelte.dts
> @@ -0,0 +1,321 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +#include "pxa1908.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/linux-event-codes.h>
> +
> +/ {
> + pxa,rev-id = <3928 2>;
Drop. This is not documented.
It does not look like you tested the DTS against bindings. Please run
`make dtbs_check` (see
Documentation/devicetree/bindings/writing-schema.rst or
https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/
for instructions).
> + model = "Samsung Galaxy Core Prime VE LTE";
> + compatible = "samsung,coreprimevelte", "marvell,pxa1908";
Missing bindings.
> +
> + /* Bootloader fills this in */
> + memory {
> + device_type = "memory";
> + reg = <0 0 0 0>;
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + framebuffer@17000000 {
> + reg = <0 0x17000000 0 0x1800000>;
> + no-map;
> + };
> +
> + gpu@9000000 {
> + reg = <0 0x9000000 0 0x1000000>;
> + };
> +
> + /* Communications processor, aka modem */
> + cp@3000000 {
> + reg = <0 0x3000000 0 0x5000000>;
> + };
> +
> + cm3@a000000 {
> + reg = <0 0xa000000 0 0x80000>;
> + };
> +
> + seclog@8000000 {
> + reg = <0 0x8000000 0 0x100000>;
> + };
> +
> + ramoops@8100000 {
> + compatible = "ramoops";
> + reg = <0 0x8100000 0 0x40000>;
> + record-size = <0x8000>;
> + console-size = <0x20000>;
> + max-reason = <5>;
> + };
> + };
> +
> + fb0: framebuffer@17177000 {
> + compatible = "simple-framebuffer";
> + reg = <0 0x17177000 0 (480 * 800 * 4)>;
> + width = <480>;
> + height = <800>;
> + stride = <(480 * 4)>;
> + format = "a8r8g8b8";
> + };
> +
> + muic-i2c {
> + compatible = "i2c-gpio";
> + sda-gpios = <&gpio 30 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
> + scl-gpios = <&gpio 29 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
> + i2c-gpio,delay-us = <3>;
> + i2c-gpio,timeout-ms = <100>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&muic_i2c_pins>;
> +
> + muic: extcon@14 {
> + compatible = "siliconmitus,sm5504-muic";
> + reg = <0x14>;
> + interrupt-parent = <&gpio>;
> + interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
> + };
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&gpio_keys_pins>;
> + autorepeat;
> +
> + key-home {
> + label = "Home";
> + linux,code = <KEY_HOME>;
> + gpios = <&gpio 50 GPIO_ACTIVE_LOW>;
> + };
> +
> + key-volup {
> + label = "Volume Up";
> + linux,code = <KEY_VOLUMEUP>;
> + gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
> + };
> +
> + key-voldown {
> + label = "Volume Down";
> + linux,code = <KEY_VOLUMEDOWN>;
> + gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
> + };
> + };
> +
> + chosen {};
chosen is usually at the top (as alphabetical order suggests)
> +};
> +
> +&smmu {
> + status = "okay";
> +};
> +
> +&pmx {
> + pinctrl-single,gpio-range = <&range 55 55 0>,
> + <&range 110 32 0>,
> + <&range 52 1 0>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&board_pins_1 &board_pins_2 &board_pins_3>;
> +
> + board_pins_1: pinmux_board_1 {
No underscores in node names.
...
> diff --git a/arch/arm64/boot/dts/marvell/pxa1908.dtsi b/arch/arm64/boot/dts/marvell/pxa1908.dtsi
> new file mode 100644
> index 000000000000..7131b2070b72
> --- /dev/null
> +++ b/arch/arm64/boot/dts/marvell/pxa1908.dtsi
> @@ -0,0 +1,298 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/marvell,pxa1908.h>
> +
> +/ {
> + model = "Marvell Armada PXA1908";
> + compatible = "marvell,pxa1908";
Undocumented compatible.
Please run scripts/checkpatch.pl and fix reported warnings. Some
warnings can be ignored, but the code here looks like it needs a fix.
Feel free to get in touch if the warning is not clear.
Best regards,
Krzysztof
On 21/07/2023 22:37, Duje Mihanović wrote:
> Add dt bindings and documentation for Marvell PXA1908 SoC.
>
> Signed-off-by: Duje Mihanović <[email protected]>
> ---
> .../bindings/arm/marvell/marvell,pxa1908.yaml | 33 +++++++++++++++++++
> 1 file changed, 33 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
> new file mode 100644
> index 000000000000..085d238129ad
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
I suggest having one bindings file for all pxa platforms, not per one SoC.
> @@ -0,0 +1,33 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/marvell/pxa1908.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Marvell PXA1908 Platforms
> +
> +maintainers:
> + - Duje Mihanović <[email protected]>
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - samsung,coreprimevelte
> + - const: marvell,pxa1908
> +
> + pxa,rev-id:
Incorrect vendor prefix
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + oneOf:
That's not oneOf, so just items:
> + - items:
> + - description: Board ID
> + - description: Board revision
> + description: |
Best regards,
Krzysztof
Hi Krzysztof,
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
>
> I suggest having one bindings file for all pxa platforms, not per one SoC.
I would need to coordinate this with Lubomir.
> > + pxa,rev-id:
> Incorrect vendor prefix
Unfortunately, the non-free bootloader used by the coreprimevelte expects the
rev-id property to be named exactly like that and will refuse to boot the
kernel image at all otherwise. This restriction can be bypassed by
chainloading U-Boot, which I wish to do eventually.
Best regards,
Duje
On Fri, Jul 21, 2023 at 10:37:44PM +0200, Duje Mihanović wrote:
> Fixes the warning in dmesg that static allocation of the base is
> deprecated.
Have you checked if this might regress on the older platforms where maybe
drivers that are looking for the specific GPIO number?
Please, elaborate the answer to the above in the commit message (in case you
have done the research, otherwise do that first).
The background of this request is the OMAP breakage in the previous cycle
due to the very similar change. We don't want to repeat our mistakes.
--
With Best Regards,
Andy Shevchenko
On Fri, Jul 21, 2023 at 10:37:45PM +0200, Duje Mihanović wrote:
> Fixes the incorrect assumption that mmp-gpio needs a pinctrl handle,
> causing devices consuming GPIO to be indefinitely deferred.
If this is a fix, add the Fixes tag and locate it closer to the beginning of
the series, so it may be backported with an ease.
--
With Best Regards,
Andy Shevchenko
On Fri, Jul 21, 2023 at 10:37:46PM +0200, Duje Mihanović wrote:
> Add driver for Marvell PXA1908 clock controller blocks. The SoC has
> numerous clock controller blocks, currently supporting APBC, APBCP, MPMU
> and APMU.
...
> +#include <linux/kernel.h>
Try to avoid using this header without real need.
You have missing a ton of the header inclusions, btw.
> +#include <linux/of_address.h>
> +#define APBC_INDEX_TO_OFFSET(n) ((n - 1) * 4)
> +
> +#define APMU_CLK_GATE_CTRL 0x40
> +#define MPMU_UART_PLL 0x14
...
> +static struct mmp_param_fixed_rate_clk fixed_rate_clks[] = {
> + {PXA1908_CLK_CLK32, "clk32", NULL, 0, 32768},
> + {PXA1908_CLK_VCTCXO, "vctcxo", NULL, 0, 26000000},
HZ_PER_MHZ (from units.h) here and elsewhere?
> + {PXA1908_CLK_PLL1_624, "pll1_624", NULL, 0, 624000000},
> + {PXA1908_CLK_PLL1_416, "pll1_416", NULL, 0, 416000000},
> + {PXA1908_CLK_PLL1_499, "pll1_499", NULL, 0, 499000000},
> + {PXA1908_CLK_PLL1_832, "pll1_832", NULL, 0, 832000000},
> + {PXA1908_CLK_PLL1_1248, "pll1_1248", NULL, 0, 1248000000},
> +};
...
> +static struct mmp_clk_factor_masks uart_factor_masks = {
> + .factor = 2,
> + .num_mask = 0x1fff,
> + .den_mask = 0x1fff,
GENMASK() (provided in bits.h).
> + .num_shift = 16,
> + .den_shift = 0,
> +};
...
> +static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
> + {.num = 8125, .den = 1536}, /* 14.745MHz */
> +};
Can this struct be dropped in favour of struct u32_fract (from math.h)?
...
> + pxa_unit->apbc_base = of_iomap(np, 0);
> + if (!pxa_unit->apbc_base) {
> + pr_err("failed to map apbc registers\n");
Haven't noticed if you are using pr_fmt().
> + kfree(pxa_unit);
> + return;
> + }
--
With Best Regards,
Andy Shevchenko
On Sat, Jul 22, 2023 at 11:27:21AM +0200, Krzysztof Kozlowski wrote:
> On 21/07/2023 22:37, Duje Mihanović wrote:
> > Add dt bindings and documentation for Marvell PXA1908 SoC.
> >
> > Signed-off-by: Duje Mihanović <[email protected]>
> > ---
> > .../bindings/arm/marvell/marvell,pxa1908.yaml | 33 +++++++++++++++++++
> > 1 file changed, 33 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
> > new file mode 100644
> > index 000000000000..085d238129ad
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
>
> I suggest having one bindings file for all pxa platforms, not per one SoC.
Or perhaps mirroring the new dts directory structure. PXA is really
multiple families. This one is more aligned with MMP than the
PXA2xx/3xx.
Rob
On July 24, 2023 4:14:35 PM GMT+02:00, Rob Herring <[email protected]> wrote:
>On Sat, Jul 22, 2023 at 11:27:21AM +0200, Krzysztof Kozlowski wrote:
>> On 21/07/2023 22:37, Duje Mihanović wrote:
>> > Add dt bindings and documentation for Marvell PXA1908 SoC.
>> >
>> > Signed-off-by: Duje Mihanović <[email protected]>
>> > ---
>> > .../bindings/arm/marvell/marvell,pxa1908.yaml | 33 +++++++++++++++++++
>> > 1 file changed, 33 insertions(+)
>> > create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
>> >
>> > diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
>> > new file mode 100644
>> > index 000000000000..085d238129ad
>> > --- /dev/null
>> > +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,pxa1908.yaml
>>
>> I suggest having one bindings file for all pxa platforms, not per one SoC.
>
>Or perhaps mirroring the new dts directory structure. PXA is really
>multiple families. This one is more aligned with MMP than the
>PXA2xx/3xx.
>
>Rob
>