This patchset is a collection and resend of the lingering GPIO patches
for the regmap migration of the ACCES and WinSystems drivers.[^1][^2]
Previously, these patches were postponed due to pending dependency
patches that have since been merged into mainline. Now that those
dependencies are present in the GPIO tree, this patchset can be merged
without incident. An IRQ handling fix for the ws16c48 driver is also
included at the end.[^3]
[^1] https://lore.kernel.org/all/[email protected]/
[^2] https://lore.kernel.org/all/[email protected]/
[^3] https://lore.kernel.org/all/[email protected]/
William Breathitt Gray (7):
gpio: idio-16: Migrate to the regmap API
gpio: 104-idio-16: Migrate to the regmap API
gpio: pci-idio-16: Migrate to the regmap API
gpio: idio-16: Remove unused legacy interface
gpio: pcie-idio-24: Migrate to the regmap API
gpio: ws16c48: Migrate to the regmap API
gpio: ws16c48: Fix off-by-one error in WS16C48 resource region extent
drivers/gpio/Kconfig | 13 +-
drivers/gpio/gpio-104-idio-16.c | 286 +++----------
drivers/gpio/gpio-idio-16.c | 254 ++++++------
drivers/gpio/gpio-idio-16.h | 79 +---
drivers/gpio/gpio-pci-idio-16.c | 294 +++-----------
drivers/gpio/gpio-pcie-idio-24.c | 677 +++++++++++--------------------
drivers/gpio/gpio-ws16c48.c | 554 +++++++++----------------
7 files changed, 728 insertions(+), 1429 deletions(-)
base-commit: 87d0688483f56c748b37a5298bdc382df5cf8f74
--
2.41.0
The regmap API supports IO port accessors so we can take advantage of
regmap abstractions rather than handling access to the device registers
directly in the driver. Migrate the pci-idio-16 module to the new
idio-16 library interface leveraging the gpio-regmap API.
Suggested-by: Andy Shevchenko <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/5ba5405c64aca984d5cf3bdbdffa04c325e5a147.1680618405.git.william.gray@linaro.org/
Signed-off-by: William Breathitt Gray <[email protected]>
---
drivers/gpio/Kconfig | 2 +-
drivers/gpio/gpio-pci-idio-16.c | 294 +++++++-------------------------
2 files changed, 62 insertions(+), 234 deletions(-)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 8bc60a6ce3a9..864b221252b2 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -1655,7 +1655,7 @@ config GPIO_PCH
config GPIO_PCI_IDIO_16
tristate "ACCES PCI-IDIO-16 GPIO support"
- select GPIOLIB_IRQCHIP
+ select REGMAP_MMIO
select GPIO_IDIO_16
help
Enables GPIO support for the ACCES PCI-IDIO-16. An interrupt is
diff --git a/drivers/gpio/gpio-pci-idio-16.c b/drivers/gpio/gpio-pci-idio-16.c
index 6726c32e31e6..44c0a21b1d1d 100644
--- a/drivers/gpio/gpio-pci-idio-16.c
+++ b/drivers/gpio/gpio-pci-idio-16.c
@@ -5,214 +5,75 @@
*/
#include <linux/bits.h>
#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/gpio/driver.h>
-#include <linux/interrupt.h>
-#include <linux/irqdesc.h>
+#include <linux/err.h>
+#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
-#include <linux/spinlock.h>
+#include <linux/regmap.h>
#include <linux/types.h>
#include "gpio-idio-16.h"
-/**
- * struct idio_16_gpio - GPIO device private data structure
- * @chip: instance of the gpio_chip
- * @lock: synchronization lock to prevent I/O race conditions
- * @reg: I/O address offset for the GPIO device registers
- * @state: ACCES IDIO-16 device state
- * @irq_mask: I/O bits affected by interrupts
- */
-struct idio_16_gpio {
- struct gpio_chip chip;
- raw_spinlock_t lock;
- struct idio_16 __iomem *reg;
- struct idio_16_state state;
- unsigned long irq_mask;
+static const struct regmap_range idio_16_wr_ranges[] = {
+ regmap_reg_range(0x0, 0x2), regmap_reg_range(0x3, 0x4),
};
-
-static int idio_16_gpio_get_direction(struct gpio_chip *chip,
- unsigned int offset)
-{
- if (idio_16_get_direction(offset))
- return GPIO_LINE_DIRECTION_IN;
-
- return GPIO_LINE_DIRECTION_OUT;
-}
-
-static int idio_16_gpio_direction_input(struct gpio_chip *chip,
- unsigned int offset)
-{
- return 0;
-}
-
-static int idio_16_gpio_direction_output(struct gpio_chip *chip,
- unsigned int offset, int value)
-{
- chip->set(chip, offset, value);
- return 0;
-}
-
-static int idio_16_gpio_get(struct gpio_chip *chip, unsigned int offset)
-{
- struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
-
- return idio_16_get(idio16gpio->reg, &idio16gpio->state, offset);
-}
-
-static int idio_16_gpio_get_multiple(struct gpio_chip *chip,
- unsigned long *mask, unsigned long *bits)
-{
- struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
-
- idio_16_get_multiple(idio16gpio->reg, &idio16gpio->state, mask, bits);
- return 0;
-}
-
-static void idio_16_gpio_set(struct gpio_chip *chip, unsigned int offset,
- int value)
-{
- struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
-
- idio_16_set(idio16gpio->reg, &idio16gpio->state, offset, value);
-}
-
-static void idio_16_gpio_set_multiple(struct gpio_chip *chip,
- unsigned long *mask, unsigned long *bits)
-{
- struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
-
- idio_16_set_multiple(idio16gpio->reg, &idio16gpio->state, mask, bits);
-}
-
-static void idio_16_irq_ack(struct irq_data *data)
-{
-}
-
-static void idio_16_irq_mask(struct irq_data *data)
-{
- struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
- struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
- const unsigned long mask = BIT(irqd_to_hwirq(data));
- unsigned long flags;
-
- idio16gpio->irq_mask &= ~mask;
-
- if (!idio16gpio->irq_mask) {
- raw_spin_lock_irqsave(&idio16gpio->lock, flags);
-
- iowrite8(0, &idio16gpio->reg->irq_ctl);
-
- raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
- }
-
- gpiochip_disable_irq(chip, irqd_to_hwirq(data));
-}
-
-static void idio_16_irq_unmask(struct irq_data *data)
-{
- struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
- struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
- const unsigned long mask = BIT(irqd_to_hwirq(data));
- const unsigned long prev_irq_mask = idio16gpio->irq_mask;
- unsigned long flags;
-
- gpiochip_enable_irq(chip, irqd_to_hwirq(data));
-
- idio16gpio->irq_mask |= mask;
-
- if (!prev_irq_mask) {
- raw_spin_lock_irqsave(&idio16gpio->lock, flags);
-
- ioread8(&idio16gpio->reg->irq_ctl);
-
- raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
- }
-}
-
-static int idio_16_irq_set_type(struct irq_data *data, unsigned int flow_type)
-{
- /* The only valid irq types are none and both-edges */
- if (flow_type != IRQ_TYPE_NONE &&
- (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
- return -EINVAL;
-
- return 0;
-}
-
-static const struct irq_chip idio_16_irqchip = {
- .name = "pci-idio-16",
- .irq_ack = idio_16_irq_ack,
- .irq_mask = idio_16_irq_mask,
- .irq_unmask = idio_16_irq_unmask,
- .irq_set_type = idio_16_irq_set_type,
- .flags = IRQCHIP_IMMUTABLE,
- GPIOCHIP_IRQ_RESOURCE_HELPERS,
+static const struct regmap_range idio_16_rd_ranges[] = {
+ regmap_reg_range(0x1, 0x2), regmap_reg_range(0x5, 0x6),
};
-
-static irqreturn_t idio_16_irq_handler(int irq, void *dev_id)
-{
- struct idio_16_gpio *const idio16gpio = dev_id;
- unsigned int irq_status;
- struct gpio_chip *const chip = &idio16gpio->chip;
- int gpio;
-
- raw_spin_lock(&idio16gpio->lock);
-
- irq_status = ioread8(&idio16gpio->reg->irq_status);
-
- raw_spin_unlock(&idio16gpio->lock);
-
- /* Make sure our device generated IRQ */
- if (!(irq_status & 0x3) || !(irq_status & 0x4))
- return IRQ_NONE;
-
- for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
- generic_handle_domain_irq(chip->irq.domain, gpio);
-
- raw_spin_lock(&idio16gpio->lock);
-
- /* Clear interrupt */
- iowrite8(0, &idio16gpio->reg->in0_7);
-
- raw_spin_unlock(&idio16gpio->lock);
-
- return IRQ_HANDLED;
-}
-
-#define IDIO_16_NGPIO 32
-static const char *idio_16_names[IDIO_16_NGPIO] = {
- "OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7",
- "OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15",
- "IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7",
- "IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15"
+static const struct regmap_range idio_16_precious_ranges[] = {
+ regmap_reg_range(0x2, 0x2),
+};
+static const struct regmap_access_table idio_16_wr_table = {
+ .yes_ranges = idio_16_wr_ranges,
+ .n_yes_ranges = ARRAY_SIZE(idio_16_wr_ranges),
+};
+static const struct regmap_access_table idio_16_rd_table = {
+ .yes_ranges = idio_16_rd_ranges,
+ .n_yes_ranges = ARRAY_SIZE(idio_16_rd_ranges),
+};
+static const struct regmap_access_table idio_16_precious_table = {
+ .yes_ranges = idio_16_precious_ranges,
+ .n_yes_ranges = ARRAY_SIZE(idio_16_precious_ranges),
+};
+static const struct regmap_config idio_16_regmap_config = {
+ .reg_bits = 8,
+ .reg_stride = 1,
+ .val_bits = 8,
+ .io_port = true,
+ .wr_table = &idio_16_wr_table,
+ .rd_table = &idio_16_rd_table,
+ .volatile_table = &idio_16_rd_table,
+ .precious_table = &idio_16_precious_table,
+ .cache_type = REGCACHE_FLAT,
+ .use_raw_spinlock = true,
};
-static int idio_16_irq_init_hw(struct gpio_chip *gc)
-{
- struct idio_16_gpio *const idio16gpio = gpiochip_get_data(gc);
-
- /* Disable IRQ by default and clear any pending interrupt */
- iowrite8(0, &idio16gpio->reg->irq_ctl);
- iowrite8(0, &idio16gpio->reg->in0_7);
+/* Only input lines (GPIO 16-31) support interrupts */
+#define IDIO_16_REGMAP_IRQ(_id) \
+ [16 + _id] = { \
+ .mask = BIT(2), \
+ .type = { .types_supported = IRQ_TYPE_EDGE_BOTH }, \
+ }
- return 0;
-}
+static const struct regmap_irq idio_16_regmap_irqs[] = {
+ IDIO_16_REGMAP_IRQ(0), IDIO_16_REGMAP_IRQ(1), IDIO_16_REGMAP_IRQ(2), /* 0-2 */
+ IDIO_16_REGMAP_IRQ(3), IDIO_16_REGMAP_IRQ(4), IDIO_16_REGMAP_IRQ(5), /* 3-5 */
+ IDIO_16_REGMAP_IRQ(6), IDIO_16_REGMAP_IRQ(7), IDIO_16_REGMAP_IRQ(8), /* 6-8 */
+ IDIO_16_REGMAP_IRQ(9), IDIO_16_REGMAP_IRQ(10), IDIO_16_REGMAP_IRQ(11), /* 9-11 */
+ IDIO_16_REGMAP_IRQ(12), IDIO_16_REGMAP_IRQ(13), IDIO_16_REGMAP_IRQ(14), /* 12-14 */
+ IDIO_16_REGMAP_IRQ(15), /* 15 */
+};
static int idio_16_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
struct device *const dev = &pdev->dev;
- struct idio_16_gpio *idio16gpio;
int err;
const size_t pci_bar_index = 2;
const char *const name = pci_name(pdev);
- struct gpio_irq_chip *girq;
-
- idio16gpio = devm_kzalloc(dev, sizeof(*idio16gpio), GFP_KERNEL);
- if (!idio16gpio)
- return -ENOMEM;
+ struct idio_16_regmap_config config = {};
+ void __iomem *regs;
+ struct regmap *map;
err = pcim_enable_device(pdev);
if (err) {
@@ -226,53 +87,20 @@ static int idio_16_probe(struct pci_dev *pdev, const struct pci_device_id *id)
return err;
}
- idio16gpio->reg = pcim_iomap_table(pdev)[pci_bar_index];
+ regs = pcim_iomap_table(pdev)[pci_bar_index];
- /* Deactivate input filters */
- iowrite8(0, &idio16gpio->reg->filter_ctl);
+ map = devm_regmap_init_mmio(dev, regs, &idio_16_regmap_config);
+ if (IS_ERR(map))
+ return dev_err_probe(dev, PTR_ERR(map), "Unable to initialize register map\n");
- idio16gpio->chip.label = name;
- idio16gpio->chip.parent = dev;
- idio16gpio->chip.owner = THIS_MODULE;
- idio16gpio->chip.base = -1;
- idio16gpio->chip.ngpio = IDIO_16_NGPIO;
- idio16gpio->chip.names = idio_16_names;
- idio16gpio->chip.get_direction = idio_16_gpio_get_direction;
- idio16gpio->chip.direction_input = idio_16_gpio_direction_input;
- idio16gpio->chip.direction_output = idio_16_gpio_direction_output;
- idio16gpio->chip.get = idio_16_gpio_get;
- idio16gpio->chip.get_multiple = idio_16_gpio_get_multiple;
- idio16gpio->chip.set = idio_16_gpio_set;
- idio16gpio->chip.set_multiple = idio_16_gpio_set_multiple;
-
- idio_16_state_init(&idio16gpio->state);
-
- girq = &idio16gpio->chip.irq;
- gpio_irq_chip_set_chip(girq, &idio_16_irqchip);
- /* This will let us handle the parent IRQ in the driver */
- girq->parent_handler = NULL;
- girq->num_parents = 0;
- girq->parents = NULL;
- girq->default_type = IRQ_TYPE_NONE;
- girq->handler = handle_edge_irq;
- girq->init_hw = idio_16_irq_init_hw;
-
- raw_spin_lock_init(&idio16gpio->lock);
-
- err = devm_gpiochip_add_data(dev, &idio16gpio->chip, idio16gpio);
- if (err) {
- dev_err(dev, "GPIO registering failed (%d)\n", err);
- return err;
- }
-
- err = devm_request_irq(dev, pdev->irq, idio_16_irq_handler, IRQF_SHARED,
- name, idio16gpio);
- if (err) {
- dev_err(dev, "IRQ handler registering failed (%d)\n", err);
- return err;
- }
+ config.parent = dev;
+ config.map = map;
+ config.regmap_irqs = idio_16_regmap_irqs;
+ config.num_regmap_irqs = ARRAY_SIZE(idio_16_regmap_irqs);
+ config.irq = pdev->irq;
+ config.filters = true;
- return 0;
+ return devm_idio_16_regmap_register(dev, &config);
}
static const struct pci_device_id idio_16_pci_dev_id[] = {
--
2.41.0
The regmap API supports IO port accessors so we can take advantage of
regmap abstractions rather than handling access to the device registers
directly in the driver.
The WinSystems WS16C48 provides the following registers:
Offset 0x0-0x5: Port 0-5 I/O
Offset 0x6: Int_Pending
Offset 0x7: Page/Lock
Offset 0x8-0xA (Page 1): Pol_0-Pol_2
Offset 0x8-0xA (Page 2): Enab_0-Enab_2
Offset 0x8-0xA (Page 3): Int_ID0-Int_ID2
Port 0-5 I/O provides access to 48 lines of digital I/O across six
registers, each bit position corresponding to the respective line.
Writing a 1 to a respective bit position causes that output pin to sink
current, while writing a 0 to the same bit position causes that output
pin to go to a high-impedance state and allows it to be used an input.
Reads on a port report the inverted state (0 = high, 1 = low) of an I/O
pin when used in input mode. Interrupts are supported on Port 0-2.
Int_Pending is a read-only register that reports the combined state of
the INT_ID0 through INT_ID2 registers; an interrupt pending is indicated
when any of the low three bits are set.
The Page/Lock register provides the following bits:
Bit 0-5: Port 0-5 I/O Lock
Bit 6-7: Page 0-3 Selection
For Bits 0-5, writing a 1 to a respective bit position locks the output
state of the corresponding I/O port. Writing the page number to Bits 6-7
selects that respective register page for use.
Pol_0-Pol_2 are accessible when Page 1 is selected. Writing a 1 to a
respective bit position selects the rising edge detection interrupts for
that input line, while writing a 0 to the same bit position selects the
falling edge detection interrupts.
Enab_0-Enab_2 are accessible when Page 2 is selected. Writing a 1 to a
respective bit position enables interrupts for that input line, while
writing a 0 to that same bit position clears and disables interrupts for
that input line.
Int_ID0-Int_ID2 are accessible when Page 3 is selected. A respective bit
when read as a 1 indicates that an edge of the polarity set in the
corresponding polarity register was detected for the corresponding input
line. Writing any value to this register clears all pending interrupts
for the register.
Suggested-by: Andy Shevchenko <[email protected]>
Reviewed-by: Michael Walle <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Link: https://lore.kernel.org/r/f59de81e80f7198bcfa9a15615c459c38b5d0e08.1680708357.git.william.gray@linaro.org/
Signed-off-by: William Breathitt Gray <[email protected]>
---
drivers/gpio/Kconfig | 3 +
drivers/gpio/gpio-ws16c48.c | 552 ++++++++++++------------------------
2 files changed, 188 insertions(+), 367 deletions(-)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 3cccc6cc315f..673bafb8be58 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -998,7 +998,10 @@ config GPIO_WINBOND
config GPIO_WS16C48
tristate "WinSystems WS16C48 GPIO support"
select ISA_BUS_API
+ select REGMAP_IRQ
+ select REGMAP_MMIO
select GPIOLIB_IRQCHIP
+ select GPIO_REGMAP
help
Enables GPIO support for the WinSystems WS16C48. The base port
addresses for the devices may be configured via the base module
diff --git a/drivers/gpio/gpio-ws16c48.c b/drivers/gpio/gpio-ws16c48.c
index e73885a4dc32..701847508e94 100644
--- a/drivers/gpio/gpio-ws16c48.c
+++ b/drivers/gpio/gpio-ws16c48.c
@@ -3,19 +3,18 @@
* GPIO driver for the WinSystems WS16C48
* Copyright (C) 2016 William Breathitt Gray
*/
-#include <linux/bitmap.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/gpio/driver.h>
-#include <linux/io.h>
-#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/irqdesc.h>
+#include <linux/err.h>
+#include <linux/gpio/regmap.h>
+#include <linux/irq.h>
#include <linux/isa.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/spinlock.h>
+#include <linux/regmap.h>
#include <linux/types.h>
#define WS16C48_EXTENT 10
@@ -31,371 +30,178 @@ static unsigned int num_irq;
module_param_hw_array(irq, uint, irq, &num_irq, 0);
MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
-/**
- * struct ws16c48_reg - device register structure
- * @port: Port 0 through 5 I/O
- * @int_pending: Interrupt Pending
- * @page_lock: Register page (Bits 7-6) and I/O port lock (Bits 5-0)
- * @pol_enab_int_id: Interrupt polarity, enable, and ID
- */
-struct ws16c48_reg {
- u8 port[6];
- u8 int_pending;
- u8 page_lock;
- u8 pol_enab_int_id[3];
+#define WS16C48_DAT_BASE 0x0
+#define WS16C48_PAGE_LOCK 0x7
+#define WS16C48_PAGE_BASE 0x8
+#define WS16C48_POL WS16C48_PAGE_BASE
+#define WS16C48_ENAB WS16C48_PAGE_BASE
+#define WS16C48_INT_ID WS16C48_PAGE_BASE
+
+#define PAGE_LOCK_PAGE_FIELD GENMASK(7, 6)
+#define POL_PAGE u8_encode_bits(1, PAGE_LOCK_PAGE_FIELD)
+#define ENAB_PAGE u8_encode_bits(2, PAGE_LOCK_PAGE_FIELD)
+#define INT_ID_PAGE u8_encode_bits(3, PAGE_LOCK_PAGE_FIELD)
+
+static const struct regmap_range ws16c48_wr_ranges[] = {
+ regmap_reg_range(0x0, 0x5), regmap_reg_range(0x7, 0xA),
+};
+static const struct regmap_range ws16c48_rd_ranges[] = {
+ regmap_reg_range(0x0, 0xA),
+};
+static const struct regmap_range ws16c48_volatile_ranges[] = {
+ regmap_reg_range(0x0, 0x6), regmap_reg_range(0x8, 0xA),
+};
+static const struct regmap_access_table ws16c48_wr_table = {
+ .yes_ranges = ws16c48_wr_ranges,
+ .n_yes_ranges = ARRAY_SIZE(ws16c48_wr_ranges),
+};
+static const struct regmap_access_table ws16c48_rd_table = {
+ .yes_ranges = ws16c48_rd_ranges,
+ .n_yes_ranges = ARRAY_SIZE(ws16c48_rd_ranges),
+};
+static const struct regmap_access_table ws16c48_volatile_table = {
+ .yes_ranges = ws16c48_volatile_ranges,
+ .n_yes_ranges = ARRAY_SIZE(ws16c48_volatile_ranges),
+};
+static const struct regmap_config ws16c48_regmap_config = {
+ .reg_bits = 8,
+ .reg_stride = 1,
+ .val_bits = 8,
+ .io_port = true,
+ .wr_table = &ws16c48_wr_table,
+ .rd_table = &ws16c48_rd_table,
+ .volatile_table = &ws16c48_volatile_table,
+ .cache_type = REGCACHE_FLAT,
+ .use_raw_spinlock = true,
+};
+
+#define WS16C48_NGPIO_PER_REG 8
+#define WS16C48_REGMAP_IRQ(_id) \
+ [_id] = { \
+ .reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \
+ .mask = BIT((_id) % WS16C48_NGPIO_PER_REG), \
+ .type = { \
+ .type_reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \
+ .types_supported = IRQ_TYPE_EDGE_BOTH, \
+ }, \
+ }
+
+/* Only the first 24 lines (Port 0-2) support interrupts */
+#define WS16C48_NUM_IRQS 24
+static const struct regmap_irq ws16c48_regmap_irqs[WS16C48_NUM_IRQS] = {
+ WS16C48_REGMAP_IRQ(0), WS16C48_REGMAP_IRQ(1), WS16C48_REGMAP_IRQ(2), /* 0-2 */
+ WS16C48_REGMAP_IRQ(3), WS16C48_REGMAP_IRQ(4), WS16C48_REGMAP_IRQ(5), /* 3-5 */
+ WS16C48_REGMAP_IRQ(6), WS16C48_REGMAP_IRQ(7), WS16C48_REGMAP_IRQ(8), /* 6-8 */
+ WS16C48_REGMAP_IRQ(9), WS16C48_REGMAP_IRQ(10), WS16C48_REGMAP_IRQ(11), /* 9-11 */
+ WS16C48_REGMAP_IRQ(12), WS16C48_REGMAP_IRQ(13), WS16C48_REGMAP_IRQ(14), /* 12-14 */
+ WS16C48_REGMAP_IRQ(15), WS16C48_REGMAP_IRQ(16), WS16C48_REGMAP_IRQ(17), /* 15-17 */
+ WS16C48_REGMAP_IRQ(18), WS16C48_REGMAP_IRQ(19), WS16C48_REGMAP_IRQ(20), /* 18-20 */
+ WS16C48_REGMAP_IRQ(21), WS16C48_REGMAP_IRQ(22), WS16C48_REGMAP_IRQ(23), /* 21-23 */
};
/**
* struct ws16c48_gpio - GPIO device private data structure
- * @chip: instance of the gpio_chip
- * @io_state: bit I/O state (whether bit is set to input or output)
- * @out_state: output bits state
+ * @map: regmap for the device
* @lock: synchronization lock to prevent I/O race conditions
* @irq_mask: I/O bits affected by interrupts
- * @flow_mask: IRQ flow type mask for the respective I/O bits
- * @reg: I/O address offset for the device registers
*/
struct ws16c48_gpio {
- struct gpio_chip chip;
- unsigned char io_state[6];
- unsigned char out_state[6];
+ struct regmap *map;
raw_spinlock_t lock;
- unsigned long irq_mask;
- unsigned long flow_mask;
- struct ws16c48_reg __iomem *reg;
+ u8 irq_mask[WS16C48_NUM_IRQS / WS16C48_NGPIO_PER_REG];
};
-static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
+static int ws16c48_handle_pre_irq(void *const irq_drv_data) __acquires(&ws16c48gpio->lock)
{
- struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
- const unsigned port = offset / 8;
- const unsigned mask = BIT(offset % 8);
+ struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
- if (ws16c48gpio->io_state[port] & mask)
- return GPIO_LINE_DIRECTION_IN;
-
- return GPIO_LINE_DIRECTION_OUT;
-}
-
-static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
-{
- struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
- const unsigned port = offset / 8;
- const unsigned mask = BIT(offset % 8);
- unsigned long flags;
-
- raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
-
- ws16c48gpio->io_state[port] |= mask;
- ws16c48gpio->out_state[port] &= ~mask;
- iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
-
- raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
+ /* Lock to prevent Page/Lock register change while we handle IRQ */
+ raw_spin_lock(&ws16c48gpio->lock);
return 0;
}
-static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
- unsigned offset, int value)
+static int ws16c48_handle_post_irq(void *const irq_drv_data) __releases(&ws16c48gpio->lock)
{
- struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
- const unsigned port = offset / 8;
- const unsigned mask = BIT(offset % 8);
- unsigned long flags;
-
- raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
+ struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
- ws16c48gpio->io_state[port] &= ~mask;
- if (value)
- ws16c48gpio->out_state[port] |= mask;
- else
- ws16c48gpio->out_state[port] &= ~mask;
- iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
-
- raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
+ raw_spin_unlock(&ws16c48gpio->lock);
return 0;
}
-static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
- struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
- const unsigned port = offset / 8;
- const unsigned mask = BIT(offset % 8);
- unsigned long flags;
- unsigned port_state;
-
- raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
-
- /* ensure that GPIO is set for input */
- if (!(ws16c48gpio->io_state[port] & mask)) {
- raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
- return -EINVAL;
- }
-
- port_state = ioread8(ws16c48gpio->reg->port + port);
-
- raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
-
- return !!(port_state & mask);
-}
-
-static int ws16c48_gpio_get_multiple(struct gpio_chip *chip,
- unsigned long *mask, unsigned long *bits)
-{
- struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
- unsigned long offset;
- unsigned long gpio_mask;
- size_t index;
- u8 __iomem *port_addr;
- unsigned long port_state;
-
- /* clear bits array to a clean slate */
- bitmap_zero(bits, chip->ngpio);
-
- for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
- index = offset / 8;
- port_addr = ws16c48gpio->reg->port + index;
- port_state = ioread8(port_addr) & gpio_mask;
-
- bitmap_set_value8(bits, port_state, offset);
- }
-
- return 0;
-}
-
-static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
- struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
- const unsigned port = offset / 8;
- const unsigned mask = BIT(offset % 8);
- unsigned long flags;
-
- raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
-
- /* ensure that GPIO is set for output */
- if (ws16c48gpio->io_state[port] & mask) {
- raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
- return;
- }
-
- if (value)
- ws16c48gpio->out_state[port] |= mask;
- else
- ws16c48gpio->out_state[port] &= ~mask;
- iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
-
- raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
-}
-
-static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
- unsigned long *mask, unsigned long *bits)
-{
- struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
- unsigned long offset;
- unsigned long gpio_mask;
- size_t index;
- u8 __iomem *port_addr;
- unsigned long bitmask;
- unsigned long flags;
-
- for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
- index = offset / 8;
- port_addr = ws16c48gpio->reg->port + index;
-
- /* mask out GPIO configured for input */
- gpio_mask &= ~ws16c48gpio->io_state[index];
- bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
-
- raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
-
- /* update output state data and set device gpio register */
- ws16c48gpio->out_state[index] &= ~gpio_mask;
- ws16c48gpio->out_state[index] |= bitmask;
- iowrite8(ws16c48gpio->out_state[index], port_addr);
-
- raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
- }
-}
-
-static void ws16c48_irq_ack(struct irq_data *data)
+static int ws16c48_handle_mask_sync(const int index, const unsigned int mask_buf_def,
+ const unsigned int mask_buf, void *const irq_drv_data)
{
- struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
- struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
- const unsigned long offset = irqd_to_hwirq(data);
- const unsigned port = offset / 8;
- const unsigned mask = BIT(offset % 8);
+ struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
unsigned long flags;
- unsigned port_state;
-
- /* only the first 3 ports support interrupts */
- if (port > 2)
- return;
+ int ret = 0;
raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
- port_state = ws16c48gpio->irq_mask >> (8*port);
+ /* exit early if no change since the last mask sync */
+ if (mask_buf == ws16c48gpio->irq_mask[index])
+ goto exit_unlock;
+ ws16c48gpio->irq_mask[index] = mask_buf;
- /* Select Register Page 2; Unlock all I/O ports */
- iowrite8(0x80, &ws16c48gpio->reg->page_lock);
+ ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, ENAB_PAGE);
+ if (ret)
+ goto exit_unlock;
- /* Clear pending interrupt */
- iowrite8(port_state & ~mask, ws16c48gpio->reg->pol_enab_int_id + port);
- iowrite8(port_state | mask, ws16c48gpio->reg->pol_enab_int_id + port);
+ /* Update ENAB register (inverted mask) */
+ ret = regmap_write(ws16c48gpio->map, WS16C48_ENAB + index, ~mask_buf);
+ if (ret)
+ goto exit_unlock;
- /* Select Register Page 3; Unlock all I/O ports */
- iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
+ ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
+ if (ret)
+ goto exit_unlock;
+exit_unlock:
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
-}
-
-static void ws16c48_irq_mask(struct irq_data *data)
-{
- struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
- struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
- const unsigned long offset = irqd_to_hwirq(data);
- const unsigned long mask = BIT(offset);
- const unsigned port = offset / 8;
- unsigned long flags;
- unsigned long port_state;
-
- /* only the first 3 ports support interrupts */
- if (port > 2)
- return;
-
- raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
- ws16c48gpio->irq_mask &= ~mask;
- gpiochip_disable_irq(chip, offset);
- port_state = ws16c48gpio->irq_mask >> (8 * port);
-
- /* Select Register Page 2; Unlock all I/O ports */
- iowrite8(0x80, &ws16c48gpio->reg->page_lock);
-
- /* Disable interrupt */
- iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
-
- /* Select Register Page 3; Unlock all I/O ports */
- iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
-
- raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
+ return ret;
}
-static void ws16c48_irq_unmask(struct irq_data *data)
+static int ws16c48_set_type_config(unsigned int **const buf, const unsigned int type,
+ const struct regmap_irq *const irq_data, const int idx,
+ void *const irq_drv_data)
{
- struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
- struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
- const unsigned long offset = irqd_to_hwirq(data);
- const unsigned long mask = BIT(offset);
- const unsigned port = offset / 8;
+ struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
+ unsigned int polarity;
unsigned long flags;
- unsigned long port_state;
-
- /* only the first 3 ports support interrupts */
- if (port > 2)
- return;
-
- raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
-
- gpiochip_enable_irq(chip, offset);
- ws16c48gpio->irq_mask |= mask;
- port_state = ws16c48gpio->irq_mask >> (8 * port);
-
- /* Select Register Page 2; Unlock all I/O ports */
- iowrite8(0x80, &ws16c48gpio->reg->page_lock);
-
- /* Enable interrupt */
- iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
-
- /* Select Register Page 3; Unlock all I/O ports */
- iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
-
- raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
-}
+ int ret;
-static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
-{
- struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
- struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
- const unsigned long offset = irqd_to_hwirq(data);
- const unsigned long mask = BIT(offset);
- const unsigned port = offset / 8;
- unsigned long flags;
- unsigned long port_state;
-
- /* only the first 3 ports support interrupts */
- if (port > 2)
- return -EINVAL;
-
- raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
-
- switch (flow_type) {
- case IRQ_TYPE_NONE:
- break;
+ switch (type) {
case IRQ_TYPE_EDGE_RISING:
- ws16c48gpio->flow_mask |= mask;
+ polarity = irq_data->mask;
break;
case IRQ_TYPE_EDGE_FALLING:
- ws16c48gpio->flow_mask &= ~mask;
+ polarity = 0;
break;
default:
- raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
return -EINVAL;
}
- port_state = ws16c48gpio->flow_mask >> (8 * port);
+ raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
- /* Select Register Page 1; Unlock all I/O ports */
- iowrite8(0x40, &ws16c48gpio->reg->page_lock);
+ ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, POL_PAGE);
+ if (ret)
+ goto exit_unlock;
/* Set interrupt polarity */
- iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
+ ret = regmap_update_bits(ws16c48gpio->map, WS16C48_POL + idx, irq_data->mask, polarity);
+ if (ret)
+ goto exit_unlock;
- /* Select Register Page 3; Unlock all I/O ports */
- iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
+ ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
+ if (ret)
+ goto exit_unlock;
+exit_unlock:
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
- return 0;
-}
-
-static const struct irq_chip ws16c48_irqchip = {
- .name = "ws16c48",
- .irq_ack = ws16c48_irq_ack,
- .irq_mask = ws16c48_irq_mask,
- .irq_unmask = ws16c48_irq_unmask,
- .irq_set_type = ws16c48_irq_set_type,
- .flags = IRQCHIP_IMMUTABLE,
- GPIOCHIP_IRQ_RESOURCE_HELPERS,
-};
-
-static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
-{
- struct ws16c48_gpio *const ws16c48gpio = dev_id;
- struct gpio_chip *const chip = &ws16c48gpio->chip;
- struct ws16c48_reg __iomem *const reg = ws16c48gpio->reg;
- unsigned long int_pending;
- unsigned long port;
- unsigned long int_id;
- unsigned long gpio;
-
- int_pending = ioread8(®->int_pending) & 0x7;
- if (!int_pending)
- return IRQ_NONE;
-
- /* loop until all pending interrupts are handled */
- do {
- for_each_set_bit(port, &int_pending, 3) {
- int_id = ioread8(reg->pol_enab_int_id + port);
- for_each_set_bit(gpio, &int_id, 8)
- generic_handle_domain_irq(chip->irq.domain,
- gpio + 8*port);
- }
-
- int_pending = ioread8(®->int_pending) & 0x7;
- } while (int_pending);
-
- return IRQ_HANDLED;
+ return ret;
}
#define WS16C48_NGPIO 48
@@ -414,30 +220,37 @@ static const char *ws16c48_names[WS16C48_NGPIO] = {
"Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
};
-static int ws16c48_irq_init_hw(struct gpio_chip *gc)
+static int ws16c48_irq_init_hw(struct regmap *const map)
{
- struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc);
+ int err;
- /* Select Register Page 2; Unlock all I/O ports */
- iowrite8(0x80, &ws16c48gpio->reg->page_lock);
+ err = regmap_write(map, WS16C48_PAGE_LOCK, ENAB_PAGE);
+ if (err)
+ return err;
/* Disable interrupts for all lines */
- iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[0]);
- iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[1]);
- iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[2]);
-
- /* Select Register Page 3; Unlock all I/O ports */
- iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
+ err = regmap_write(map, WS16C48_ENAB + 0, 0x00);
+ if (err)
+ return err;
+ err = regmap_write(map, WS16C48_ENAB + 1, 0x00);
+ if (err)
+ return err;
+ err = regmap_write(map, WS16C48_ENAB + 2, 0x00);
+ if (err)
+ return err;
- return 0;
+ return regmap_write(map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
}
static int ws16c48_probe(struct device *dev, unsigned int id)
{
struct ws16c48_gpio *ws16c48gpio;
const char *const name = dev_name(dev);
- struct gpio_irq_chip *girq;
int err;
+ struct gpio_regmap_config gpio_config = {};
+ void __iomem *regs;
+ struct regmap_irq_chip *chip;
+ struct regmap_irq_chip_data *chip_data;
ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
if (!ws16c48gpio)
@@ -449,50 +262,55 @@ static int ws16c48_probe(struct device *dev, unsigned int id)
return -EBUSY;
}
- ws16c48gpio->reg = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
- if (!ws16c48gpio->reg)
+ regs = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
+ if (!regs)
return -ENOMEM;
- ws16c48gpio->chip.label = name;
- ws16c48gpio->chip.parent = dev;
- ws16c48gpio->chip.owner = THIS_MODULE;
- ws16c48gpio->chip.base = -1;
- ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
- ws16c48gpio->chip.names = ws16c48_names;
- ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
- ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
- ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
- ws16c48gpio->chip.get = ws16c48_gpio_get;
- ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
- ws16c48gpio->chip.set = ws16c48_gpio_set;
- ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
-
- girq = &ws16c48gpio->chip.irq;
- gpio_irq_chip_set_chip(girq, &ws16c48_irqchip);
- /* This will let us handle the parent IRQ in the driver */
- girq->parent_handler = NULL;
- girq->num_parents = 0;
- girq->parents = NULL;
- girq->default_type = IRQ_TYPE_NONE;
- girq->handler = handle_edge_irq;
- girq->init_hw = ws16c48_irq_init_hw;
+ ws16c48gpio->map = devm_regmap_init_mmio(dev, regs, &ws16c48_regmap_config);
+ if (IS_ERR(ws16c48gpio->map))
+ return dev_err_probe(dev, PTR_ERR(ws16c48gpio->map),
+ "Unable to initialize register map\n");
- raw_spin_lock_init(&ws16c48gpio->lock);
+ chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
- err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
- if (err) {
- dev_err(dev, "GPIO registering failed (%d)\n", err);
- return err;
- }
+ chip->name = name;
+ chip->status_base = WS16C48_INT_ID;
+ chip->mask_base = WS16C48_ENAB;
+ chip->ack_base = WS16C48_INT_ID;
+ chip->num_regs = 3;
+ chip->irqs = ws16c48_regmap_irqs;
+ chip->num_irqs = ARRAY_SIZE(ws16c48_regmap_irqs);
+ chip->handle_pre_irq = ws16c48_handle_pre_irq;
+ chip->handle_post_irq = ws16c48_handle_post_irq;
+ chip->handle_mask_sync = ws16c48_handle_mask_sync;
+ chip->set_type_config = ws16c48_set_type_config;
+ chip->irq_drv_data = ws16c48gpio;
- err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED,
- name, ws16c48gpio);
- if (err) {
- dev_err(dev, "IRQ handler registering failed (%d)\n", err);
+ raw_spin_lock_init(&ws16c48gpio->lock);
+
+ /* Initialize to prevent spurious interrupts before we're ready */
+ err = ws16c48_irq_init_hw(ws16c48gpio->map);
+ if (err)
return err;
- }
- return 0;
+ err = devm_regmap_add_irq_chip(dev, ws16c48gpio->map, irq[id], 0, 0, chip, &chip_data);
+ if (err)
+ return dev_err_probe(dev, err, "IRQ registration failed\n");
+
+ gpio_config.parent = dev;
+ gpio_config.regmap = ws16c48gpio->map;
+ gpio_config.ngpio = WS16C48_NGPIO;
+ gpio_config.names = ws16c48_names;
+ gpio_config.reg_dat_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
+ gpio_config.reg_set_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
+ /* Setting a GPIO to 0 allows it to be used as an input */
+ gpio_config.reg_dir_out_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
+ gpio_config.ngpio_per_reg = WS16C48_NGPIO_PER_REG;
+ gpio_config.irq_domain = regmap_irq_get_domain(chip_data);
+
+ return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config));
}
static struct isa_driver ws16c48_driver = {
--
2.41.0
The regmap API supports IO port accessors so we can take advantage of
regmap abstractions rather than handling access to the device registers
directly in the driver.
For the PCIe-IDIO-24 series of devices, the following BARs are
available:
BAR[0]: memory mapped PEX8311
BAR[1]: I/O mapped PEX8311
BAR[2]: I/O mapped card registers
There are 24 FET Output lines, 24 Isolated Input lines, and 8 TTL/CMOS
lines (which may be configured for either output or input). The GPIO
lines are exposed by the following card registers:
Base +0x0-0x2 (Read/Write): FET Outputs
Base +0xB (Read/Write): TTL/CMOS
Base +0x4-0x6 (Read): Isolated Inputs
Base +0x7 (Read): TTL/CMOS
In order for the device to support interrupts, the PLX PEX8311 internal
PCI wire interrupt and local interrupt input must first be enabled.
The following card registers for Change-Of-State may be used:
Base +0x8-0xA (Read): COS Status Inputs
Base +0x8-0xA (Write): COS Clear Inputs
Base +0xB (Read): COS Status TTL/CMOS
Base +0xB (Write): COS Clear TTL/CMOS
Base +0xE (Read/Write): COS Enable
The COS Enable register is used to enable/disable interrupts and
configure the interrupt levels; each bit maps to a group of eight inputs
as described below:
Bit 0: IRQ EN Rising Edge IN0-7
Bit 1: IRQ EN Rising Edge IN8-15
Bit 2: IRQ EN Rising Edge IN16-23
Bit 3: IRQ EN Rising Edge TTL0-7
Bit 4: IRQ EN Falling Edge IN0-7
Bit 5: IRQ EN Falling Edge IN8-15
Bit 6: IRQ EN Falling Edge IN16-23
Bit 7: IRQ EN Falling Edge TTL0-7
An interrupt is asserted when a change-of-state matching the interrupt
level configuration respective for a particular group of eight inputs
with enabled COS is detected.
The COS Status registers may be read to determine which inputs have
changed; if interrupts were enabled, an IRQ will be generated for the
set bits in these registers. Writing the value read from the COS Status
register back to the respective COS Clear register will clear just those
interrupts.
Reviewed-by: Michael Walle <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Link: https://lore.kernel.org/r/3091e387b1d2eac011a1d84e493663aa2acf982e.1680708357.git.william.gray@linaro.org/
Signed-off-by: William Breathitt Gray <[email protected]>
---
drivers/gpio/Kconfig | 3 +
drivers/gpio/gpio-pcie-idio-24.c | 677 +++++++++++--------------------
2 files changed, 250 insertions(+), 430 deletions(-)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 864b221252b2..3cccc6cc315f 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -1665,7 +1665,10 @@ config GPIO_PCI_IDIO_16
config GPIO_PCIE_IDIO_24
tristate "ACCES PCIe-IDIO-24 GPIO support"
+ select REGMAP_IRQ
+ select REGMAP_MMIO
select GPIOLIB_IRQCHIP
+ select GPIO_REGMAP
help
Enables GPIO support for the ACCES PCIe-IDIO-24 family (PCIe-IDIO-24,
PCIe-IDI-24, PCIe-IDO-24, PCIe-IDIO-12). An interrupt is generated
diff --git a/drivers/gpio/gpio-pcie-idio-24.c b/drivers/gpio/gpio-pcie-idio-24.c
index 463c0613abb9..2efd1b1a0805 100644
--- a/drivers/gpio/gpio-pcie-idio-24.c
+++ b/drivers/gpio/gpio-pcie-idio-24.c
@@ -6,16 +6,15 @@
* This driver supports the following ACCES devices: PCIe-IDIO-24,
* PCIe-IDI-24, PCIe-IDO-24, and PCIe-IDIO-12.
*/
-#include <linux/bitmap.h>
-#include <linux/bitops.h>
+#include <linux/bits.h>
#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/gpio/driver.h>
-#include <linux/interrupt.h>
-#include <linux/irqdesc.h>
+#include <linux/err.h>
+#include <linux/gpio/regmap.h>
+#include <linux/irq.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
+#include <linux/regmap.h>
#include <linux/spinlock.h>
#include <linux/types.h>
@@ -59,422 +58,224 @@
#define PLX_PEX8311_PCI_LCS_INTCSR 0x68
#define INTCSR_INTERNAL_PCI_WIRE BIT(8)
#define INTCSR_LOCAL_INPUT BIT(11)
+#define IDIO_24_ENABLE_IRQ (INTCSR_INTERNAL_PCI_WIRE | INTCSR_LOCAL_INPUT)
+
+#define IDIO_24_OUT_BASE 0x0
+#define IDIO_24_TTLCMOS_OUT_REG 0x3
+#define IDIO_24_IN_BASE 0x4
+#define IDIO_24_TTLCMOS_IN_REG 0x7
+#define IDIO_24_COS_STATUS_BASE 0x8
+#define IDIO_24_CONTROL_REG 0xC
+#define IDIO_24_COS_ENABLE 0xE
+#define IDIO_24_SOFT_RESET 0xF
+
+#define CONTROL_REG_OUT_MODE BIT(1)
+
+#define COS_ENABLE_RISING BIT(1)
+#define COS_ENABLE_FALLING BIT(4)
+#define COS_ENABLE_BOTH (COS_ENABLE_RISING | COS_ENABLE_FALLING)
+
+static const struct regmap_config pex8311_intcsr_regmap_config = {
+ .name = "pex8311_intcsr",
+ .reg_bits = 32,
+ .reg_stride = 1,
+ .reg_base = PLX_PEX8311_PCI_LCS_INTCSR,
+ .val_bits = 32,
+ .io_port = true,
+};
-/**
- * struct idio_24_gpio_reg - GPIO device registers structure
- * @out0_7: Read: FET Outputs 0-7
- * Write: FET Outputs 0-7
- * @out8_15: Read: FET Outputs 8-15
- * Write: FET Outputs 8-15
- * @out16_23: Read: FET Outputs 16-23
- * Write: FET Outputs 16-23
- * @ttl_out0_7: Read: TTL/CMOS Outputs 0-7
- * Write: TTL/CMOS Outputs 0-7
- * @in0_7: Read: Isolated Inputs 0-7
- * Write: Reserved
- * @in8_15: Read: Isolated Inputs 8-15
- * Write: Reserved
- * @in16_23: Read: Isolated Inputs 16-23
- * Write: Reserved
- * @ttl_in0_7: Read: TTL/CMOS Inputs 0-7
- * Write: Reserved
- * @cos0_7: Read: COS Status Inputs 0-7
- * Write: COS Clear Inputs 0-7
- * @cos8_15: Read: COS Status Inputs 8-15
- * Write: COS Clear Inputs 8-15
- * @cos16_23: Read: COS Status Inputs 16-23
- * Write: COS Clear Inputs 16-23
- * @cos_ttl0_7: Read: COS Status TTL/CMOS 0-7
- * Write: COS Clear TTL/CMOS 0-7
- * @ctl: Read: Control Register
- * Write: Control Register
- * @reserved: Read: Reserved
- * Write: Reserved
- * @cos_enable: Read: COS Enable
- * Write: COS Enable
- * @soft_reset: Read: IRQ Output Pin Status
- * Write: Software Board Reset
- */
-struct idio_24_gpio_reg {
- u8 out0_7;
- u8 out8_15;
- u8 out16_23;
- u8 ttl_out0_7;
- u8 in0_7;
- u8 in8_15;
- u8 in16_23;
- u8 ttl_in0_7;
- u8 cos0_7;
- u8 cos8_15;
- u8 cos16_23;
- u8 cos_ttl0_7;
- u8 ctl;
- u8 reserved;
- u8 cos_enable;
- u8 soft_reset;
+static const struct regmap_range idio_24_wr_ranges[] = {
+ regmap_reg_range(0x0, 0x3), regmap_reg_range(0x8, 0xC),
+ regmap_reg_range(0xE, 0xF),
+};
+static const struct regmap_range idio_24_rd_ranges[] = {
+ regmap_reg_range(0x0, 0xC), regmap_reg_range(0xE, 0xF),
+};
+static const struct regmap_range idio_24_volatile_ranges[] = {
+ regmap_reg_range(0x4, 0xB), regmap_reg_range(0xF, 0xF),
+};
+static const struct regmap_access_table idio_24_wr_table = {
+ .yes_ranges = idio_24_wr_ranges,
+ .n_yes_ranges = ARRAY_SIZE(idio_24_wr_ranges),
+};
+static const struct regmap_access_table idio_24_rd_table = {
+ .yes_ranges = idio_24_rd_ranges,
+ .n_yes_ranges = ARRAY_SIZE(idio_24_rd_ranges),
+};
+static const struct regmap_access_table idio_24_volatile_table = {
+ .yes_ranges = idio_24_volatile_ranges,
+ .n_yes_ranges = ARRAY_SIZE(idio_24_volatile_ranges),
+};
+
+static const struct regmap_config idio_24_regmap_config = {
+ .reg_bits = 8,
+ .reg_stride = 1,
+ .val_bits = 8,
+ .io_port = true,
+ .wr_table = &idio_24_wr_table,
+ .rd_table = &idio_24_rd_table,
+ .volatile_table = &idio_24_volatile_table,
+ .cache_type = REGCACHE_FLAT,
+ .use_raw_spinlock = true,
+};
+
+#define IDIO_24_NGPIO_PER_REG 8
+#define IDIO_24_REGMAP_IRQ(_id) \
+ [24 + _id] = { \
+ .reg_offset = (_id) / IDIO_24_NGPIO_PER_REG, \
+ .mask = BIT((_id) % IDIO_24_NGPIO_PER_REG), \
+ .type = { .types_supported = IRQ_TYPE_EDGE_BOTH }, \
+ }
+#define IDIO_24_IIN_IRQ(_id) IDIO_24_REGMAP_IRQ(_id)
+#define IDIO_24_TTL_IRQ(_id) IDIO_24_REGMAP_IRQ(24 + _id)
+
+static const struct regmap_irq idio_24_regmap_irqs[] = {
+ IDIO_24_IIN_IRQ(0), IDIO_24_IIN_IRQ(1), IDIO_24_IIN_IRQ(2), /* IIN 0-2 */
+ IDIO_24_IIN_IRQ(3), IDIO_24_IIN_IRQ(4), IDIO_24_IIN_IRQ(5), /* IIN 3-5 */
+ IDIO_24_IIN_IRQ(6), IDIO_24_IIN_IRQ(7), IDIO_24_IIN_IRQ(8), /* IIN 6-8 */
+ IDIO_24_IIN_IRQ(9), IDIO_24_IIN_IRQ(10), IDIO_24_IIN_IRQ(11), /* IIN 9-11 */
+ IDIO_24_IIN_IRQ(12), IDIO_24_IIN_IRQ(13), IDIO_24_IIN_IRQ(14), /* IIN 12-14 */
+ IDIO_24_IIN_IRQ(15), IDIO_24_IIN_IRQ(16), IDIO_24_IIN_IRQ(17), /* IIN 15-17 */
+ IDIO_24_IIN_IRQ(18), IDIO_24_IIN_IRQ(19), IDIO_24_IIN_IRQ(20), /* IIN 18-20 */
+ IDIO_24_IIN_IRQ(21), IDIO_24_IIN_IRQ(22), IDIO_24_IIN_IRQ(23), /* IIN 21-23 */
+ IDIO_24_TTL_IRQ(0), IDIO_24_TTL_IRQ(1), IDIO_24_TTL_IRQ(2), /* TTL 0-2 */
+ IDIO_24_TTL_IRQ(3), IDIO_24_TTL_IRQ(4), IDIO_24_TTL_IRQ(5), /* TTL 3-5 */
+ IDIO_24_TTL_IRQ(6), IDIO_24_TTL_IRQ(7), /* TTL 6-7 */
};
/**
* struct idio_24_gpio - GPIO device private data structure
- * @chip: instance of the gpio_chip
+ * @map: regmap for the device
* @lock: synchronization lock to prevent I/O race conditions
- * @reg: I/O address offset for the GPIO device registers
- * @irq_mask: I/O bits affected by interrupts
+ * @irq_type: type configuration for IRQs
*/
struct idio_24_gpio {
- struct gpio_chip chip;
+ struct regmap *map;
raw_spinlock_t lock;
- __u8 __iomem *plx;
- struct idio_24_gpio_reg __iomem *reg;
- unsigned long irq_mask;
+ u8 irq_type;
};
-static int idio_24_gpio_get_direction(struct gpio_chip *chip,
- unsigned int offset)
-{
- struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
- const unsigned long out_mode_mask = BIT(1);
-
- /* FET Outputs */
- if (offset < 24)
- return GPIO_LINE_DIRECTION_OUT;
-
- /* Isolated Inputs */
- if (offset < 48)
- return GPIO_LINE_DIRECTION_IN;
-
- /* TTL/CMOS I/O */
- /* OUT MODE = 1 when TTL/CMOS Output Mode is set */
- if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
- return GPIO_LINE_DIRECTION_OUT;
-
- return GPIO_LINE_DIRECTION_IN;
-}
-
-static int idio_24_gpio_direction_input(struct gpio_chip *chip,
- unsigned int offset)
-{
- struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
- unsigned long flags;
- unsigned int ctl_state;
- const unsigned long out_mode_mask = BIT(1);
-
- /* TTL/CMOS I/O */
- if (offset > 47) {
- raw_spin_lock_irqsave(&idio24gpio->lock, flags);
-
- /* Clear TTL/CMOS Output Mode */
- ctl_state = ioread8(&idio24gpio->reg->ctl) & ~out_mode_mask;
- iowrite8(ctl_state, &idio24gpio->reg->ctl);
-
- raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
- }
-
- return 0;
-}
-
-static int idio_24_gpio_direction_output(struct gpio_chip *chip,
- unsigned int offset, int value)
-{
- struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
- unsigned long flags;
- unsigned int ctl_state;
- const unsigned long out_mode_mask = BIT(1);
-
- /* TTL/CMOS I/O */
- if (offset > 47) {
- raw_spin_lock_irqsave(&idio24gpio->lock, flags);
-
- /* Set TTL/CMOS Output Mode */
- ctl_state = ioread8(&idio24gpio->reg->ctl) | out_mode_mask;
- iowrite8(ctl_state, &idio24gpio->reg->ctl);
-
- raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
- }
-
- chip->set(chip, offset, value);
- return 0;
-}
-
-static int idio_24_gpio_get(struct gpio_chip *chip, unsigned int offset)
+static int idio_24_handle_mask_sync(const int index, const unsigned int mask_buf_def,
+ const unsigned int mask_buf, void *const irq_drv_data)
{
- struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
- const unsigned long offset_mask = BIT(offset % 8);
- const unsigned long out_mode_mask = BIT(1);
-
- /* FET Outputs */
- if (offset < 8)
- return !!(ioread8(&idio24gpio->reg->out0_7) & offset_mask);
+ const unsigned int type_mask = COS_ENABLE_BOTH << index;
+ struct idio_24_gpio *const idio24gpio = irq_drv_data;
+ u8 type;
+ int ret;
- if (offset < 16)
- return !!(ioread8(&idio24gpio->reg->out8_15) & offset_mask);
-
- if (offset < 24)
- return !!(ioread8(&idio24gpio->reg->out16_23) & offset_mask);
-
- /* Isolated Inputs */
- if (offset < 32)
- return !!(ioread8(&idio24gpio->reg->in0_7) & offset_mask);
-
- if (offset < 40)
- return !!(ioread8(&idio24gpio->reg->in8_15) & offset_mask);
-
- if (offset < 48)
- return !!(ioread8(&idio24gpio->reg->in16_23) & offset_mask);
+ raw_spin_lock(&idio24gpio->lock);
- /* TTL/CMOS Outputs */
- if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
- return !!(ioread8(&idio24gpio->reg->ttl_out0_7) & offset_mask);
+ /* if all are masked, then disable interrupts, else set to type */
+ type = (mask_buf == mask_buf_def) ? ~type_mask : idio24gpio->irq_type;
- /* TTL/CMOS Inputs */
- return !!(ioread8(&idio24gpio->reg->ttl_in0_7) & offset_mask);
-}
+ ret = regmap_update_bits(idio24gpio->map, IDIO_24_COS_ENABLE, type_mask, type);
-static int idio_24_gpio_get_multiple(struct gpio_chip *chip,
- unsigned long *mask, unsigned long *bits)
-{
- struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
- unsigned long offset;
- unsigned long gpio_mask;
- void __iomem *ports[] = {
- &idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15,
- &idio24gpio->reg->out16_23, &idio24gpio->reg->in0_7,
- &idio24gpio->reg->in8_15, &idio24gpio->reg->in16_23,
- };
- size_t index;
- unsigned long port_state;
- const unsigned long out_mode_mask = BIT(1);
-
- /* clear bits array to a clean slate */
- bitmap_zero(bits, chip->ngpio);
-
- for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
- index = offset / 8;
-
- /* read bits from current gpio port (port 6 is TTL GPIO) */
- if (index < 6)
- port_state = ioread8(ports[index]);
- else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask)
- port_state = ioread8(&idio24gpio->reg->ttl_out0_7);
- else
- port_state = ioread8(&idio24gpio->reg->ttl_in0_7);
-
- port_state &= gpio_mask;
-
- bitmap_set_value8(bits, port_state, offset);
- }
+ raw_spin_unlock(&idio24gpio->lock);
- return 0;
+ return ret;
}
-static void idio_24_gpio_set(struct gpio_chip *chip, unsigned int offset,
- int value)
+static int idio_24_set_type_config(unsigned int **const buf, const unsigned int type,
+ const struct regmap_irq *const irq_data, const int idx,
+ void *const irq_drv_data)
{
- struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
- const unsigned long out_mode_mask = BIT(1);
- void __iomem *base;
- const unsigned int mask = BIT(offset % 8);
- unsigned long flags;
- unsigned int out_state;
-
- /* Isolated Inputs */
- if (offset > 23 && offset < 48)
- return;
-
- /* TTL/CMOS Inputs */
- if (offset > 47 && !(ioread8(&idio24gpio->reg->ctl) & out_mode_mask))
- return;
-
- /* TTL/CMOS Outputs */
- if (offset > 47)
- base = &idio24gpio->reg->ttl_out0_7;
- /* FET Outputs */
- else if (offset > 15)
- base = &idio24gpio->reg->out16_23;
- else if (offset > 7)
- base = &idio24gpio->reg->out8_15;
- else
- base = &idio24gpio->reg->out0_7;
-
- raw_spin_lock_irqsave(&idio24gpio->lock, flags);
-
- if (value)
- out_state = ioread8(base) | mask;
- else
- out_state = ioread8(base) & ~mask;
-
- iowrite8(out_state, base);
-
- raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
-}
-
-static void idio_24_gpio_set_multiple(struct gpio_chip *chip,
- unsigned long *mask, unsigned long *bits)
-{
- struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
- unsigned long offset;
- unsigned long gpio_mask;
- void __iomem *ports[] = {
- &idio24gpio->reg->out0_7, &idio24gpio->reg->out8_15,
- &idio24gpio->reg->out16_23
- };
- size_t index;
- unsigned long bitmask;
- unsigned long flags;
- unsigned long out_state;
- const unsigned long out_mode_mask = BIT(1);
-
- for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
- index = offset / 8;
-
- bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
-
- raw_spin_lock_irqsave(&idio24gpio->lock, flags);
-
- /* read bits from current gpio port (port 6 is TTL GPIO) */
- if (index < 6) {
- out_state = ioread8(ports[index]);
- } else if (ioread8(&idio24gpio->reg->ctl) & out_mode_mask) {
- out_state = ioread8(&idio24gpio->reg->ttl_out0_7);
- } else {
- /* skip TTL GPIO if set for input */
- raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
- continue;
- }
-
- /* set requested bit states */
- out_state &= ~gpio_mask;
- out_state |= bitmask;
-
- /* write bits for current gpio port (port 6 is TTL GPIO) */
- if (index < 6)
- iowrite8(out_state, ports[index]);
- else
- iowrite8(out_state, &idio24gpio->reg->ttl_out0_7);
-
- raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
+ const unsigned int offset = irq_data->reg_offset;
+ const unsigned int rising = COS_ENABLE_RISING << offset;
+ const unsigned int falling = COS_ENABLE_FALLING << offset;
+ const unsigned int mask = COS_ENABLE_BOTH << offset;
+ struct idio_24_gpio *const idio24gpio = irq_drv_data;
+ unsigned int new;
+ unsigned int cos_enable;
+ int ret;
+
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ new = rising;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ new = falling;
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ new = mask;
+ break;
+ default:
+ return -EINVAL;
}
-}
-
-static void idio_24_irq_ack(struct irq_data *data)
-{
-}
-static void idio_24_irq_mask(struct irq_data *data)
-{
- struct gpio_chip *const chip = irq_data_get_irq_chip_data(data);
- struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
- unsigned long flags;
- const unsigned long bit_offset = irqd_to_hwirq(data) - 24;
- unsigned char new_irq_mask;
- const unsigned long bank_offset = bit_offset / 8;
- unsigned char cos_enable_state;
-
- raw_spin_lock_irqsave(&idio24gpio->lock, flags);
-
- idio24gpio->irq_mask &= ~BIT(bit_offset);
- new_irq_mask = idio24gpio->irq_mask >> bank_offset * 8;
+ raw_spin_lock(&idio24gpio->lock);
- if (!new_irq_mask) {
- cos_enable_state = ioread8(&idio24gpio->reg->cos_enable);
+ /* replace old bitmap with new bitmap */
+ idio24gpio->irq_type = (idio24gpio->irq_type & ~mask) | (new & mask);
- /* Disable Rising Edge detection */
- cos_enable_state &= ~BIT(bank_offset);
- /* Disable Falling Edge detection */
- cos_enable_state &= ~BIT(bank_offset + 4);
+ ret = regmap_read(idio24gpio->map, IDIO_24_COS_ENABLE, &cos_enable);
+ if (ret)
+ goto exit_unlock;
- iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable);
+ /* if COS is currently enabled then update the edge type */
+ if (cos_enable & mask) {
+ ret = regmap_update_bits(idio24gpio->map, IDIO_24_COS_ENABLE, mask,
+ idio24gpio->irq_type);
+ if (ret)
+ goto exit_unlock;
}
- raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
+exit_unlock:
+ raw_spin_unlock(&idio24gpio->lock);
- gpiochip_disable_irq(chip, irqd_to_hwirq(data));
+ return ret;
}
-static void idio_24_irq_unmask(struct irq_data *data)
+static int idio_24_reg_mask_xlate(struct gpio_regmap *const gpio, const unsigned int base,
+ const unsigned int offset, unsigned int *const reg,
+ unsigned int *const mask)
{
- struct gpio_chip *const chip = irq_data_get_irq_chip_data(data);
- struct idio_24_gpio *const idio24gpio = gpiochip_get_data(chip);
- unsigned long flags;
- unsigned char prev_irq_mask;
- const unsigned long bit_offset = irqd_to_hwirq(data) - 24;
- const unsigned long bank_offset = bit_offset / 8;
- unsigned char cos_enable_state;
-
- gpiochip_enable_irq(chip, irqd_to_hwirq(data));
-
- raw_spin_lock_irqsave(&idio24gpio->lock, flags);
+ const unsigned int out_stride = offset / IDIO_24_NGPIO_PER_REG;
+ const unsigned int in_stride = (offset - 24) / IDIO_24_NGPIO_PER_REG;
+ struct regmap *const map = gpio_regmap_get_drvdata(gpio);
+ int err;
+ unsigned int ctrl_reg;
- prev_irq_mask = idio24gpio->irq_mask >> bank_offset * 8;
- idio24gpio->irq_mask |= BIT(bit_offset);
+ switch (base) {
+ case IDIO_24_OUT_BASE:
+ *mask = BIT(offset % IDIO_24_NGPIO_PER_REG);
- if (!prev_irq_mask) {
- cos_enable_state = ioread8(&idio24gpio->reg->cos_enable);
+ /* FET Outputs */
+ if (offset < 24) {
+ *reg = IDIO_24_OUT_BASE + out_stride;
+ return 0;
+ }
- /* Enable Rising Edge detection */
- cos_enable_state |= BIT(bank_offset);
- /* Enable Falling Edge detection */
- cos_enable_state |= BIT(bank_offset + 4);
+ /* Isolated Inputs */
+ if (offset < 48) {
+ *reg = IDIO_24_IN_BASE + in_stride;
+ return 0;
+ }
- iowrite8(cos_enable_state, &idio24gpio->reg->cos_enable);
- }
+ err = regmap_read(map, IDIO_24_CONTROL_REG, &ctrl_reg);
+ if (err)
+ return err;
- raw_spin_unlock_irqrestore(&idio24gpio->lock, flags);
-}
+ /* TTL/CMOS Outputs */
+ if (ctrl_reg & CONTROL_REG_OUT_MODE) {
+ *reg = IDIO_24_TTLCMOS_OUT_REG;
+ return 0;
+ }
-static int idio_24_irq_set_type(struct irq_data *data, unsigned int flow_type)
-{
- /* The only valid irq types are none and both-edges */
- if (flow_type != IRQ_TYPE_NONE &&
- (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
+ /* TTL/CMOS Inputs */
+ *reg = IDIO_24_TTLCMOS_IN_REG;
+ return 0;
+ case IDIO_24_CONTROL_REG:
+ /* We can only set direction for TTL/CMOS lines */
+ if (offset < 48)
+ return -EOPNOTSUPP;
+
+ *reg = IDIO_24_CONTROL_REG;
+ *mask = CONTROL_REG_OUT_MODE;
+ return 0;
+ default:
+ /* Should never reach this path */
return -EINVAL;
-
- return 0;
-}
-
-static const struct irq_chip idio_24_irqchip = {
- .name = "pcie-idio-24",
- .irq_ack = idio_24_irq_ack,
- .irq_mask = idio_24_irq_mask,
- .irq_unmask = idio_24_irq_unmask,
- .irq_set_type = idio_24_irq_set_type,
- .flags = IRQCHIP_IMMUTABLE,
- GPIOCHIP_IRQ_RESOURCE_HELPERS,
-};
-
-static irqreturn_t idio_24_irq_handler(int irq, void *dev_id)
-{
- struct idio_24_gpio *const idio24gpio = dev_id;
- unsigned long irq_status;
- struct gpio_chip *const chip = &idio24gpio->chip;
- unsigned long irq_mask;
- int gpio;
-
- raw_spin_lock(&idio24gpio->lock);
-
- /* Read Change-Of-State status */
- irq_status = ioread32(&idio24gpio->reg->cos0_7);
-
- raw_spin_unlock(&idio24gpio->lock);
-
- /* Make sure our device generated IRQ */
- if (!irq_status)
- return IRQ_NONE;
-
- /* Handle only unmasked IRQ */
- irq_mask = idio24gpio->irq_mask & irq_status;
-
- for_each_set_bit(gpio, &irq_mask, chip->ngpio - 24)
- generic_handle_domain_irq(chip->irq.domain, gpio + 24);
-
- raw_spin_lock(&idio24gpio->lock);
-
- /* Clear Change-Of-State status */
- iowrite32(irq_status, &idio24gpio->reg->cos0_7);
-
- raw_spin_unlock(&idio24gpio->lock);
-
- return IRQ_HANDLED;
+ }
}
#define IDIO_24_NGPIO 56
@@ -496,11 +297,12 @@ static int idio_24_probe(struct pci_dev *pdev, const struct pci_device_id *id)
const size_t pci_plx_bar_index = 1;
const size_t pci_bar_index = 2;
const char *const name = pci_name(pdev);
- struct gpio_irq_chip *girq;
-
- idio24gpio = devm_kzalloc(dev, sizeof(*idio24gpio), GFP_KERNEL);
- if (!idio24gpio)
- return -ENOMEM;
+ struct gpio_regmap_config gpio_config = {};
+ void __iomem *pex8311_regs;
+ void __iomem *idio_24_regs;
+ struct regmap *intcsr_map;
+ struct regmap_irq_chip *chip;
+ struct regmap_irq_chip_data *chip_data;
err = pcim_enable_device(pdev);
if (err) {
@@ -514,57 +316,72 @@ static int idio_24_probe(struct pci_dev *pdev, const struct pci_device_id *id)
return err;
}
- idio24gpio->plx = pcim_iomap_table(pdev)[pci_plx_bar_index];
- idio24gpio->reg = pcim_iomap_table(pdev)[pci_bar_index];
-
- idio24gpio->chip.label = name;
- idio24gpio->chip.parent = dev;
- idio24gpio->chip.owner = THIS_MODULE;
- idio24gpio->chip.base = -1;
- idio24gpio->chip.ngpio = IDIO_24_NGPIO;
- idio24gpio->chip.names = idio_24_names;
- idio24gpio->chip.get_direction = idio_24_gpio_get_direction;
- idio24gpio->chip.direction_input = idio_24_gpio_direction_input;
- idio24gpio->chip.direction_output = idio_24_gpio_direction_output;
- idio24gpio->chip.get = idio_24_gpio_get;
- idio24gpio->chip.get_multiple = idio_24_gpio_get_multiple;
- idio24gpio->chip.set = idio_24_gpio_set;
- idio24gpio->chip.set_multiple = idio_24_gpio_set_multiple;
-
- girq = &idio24gpio->chip.irq;
- gpio_irq_chip_set_chip(girq, &idio_24_irqchip);
- /* This will let us handle the parent IRQ in the driver */
- girq->parent_handler = NULL;
- girq->num_parents = 0;
- girq->parents = NULL;
- girq->default_type = IRQ_TYPE_NONE;
- girq->handler = handle_edge_irq;
+ pex8311_regs = pcim_iomap_table(pdev)[pci_plx_bar_index];
+ idio_24_regs = pcim_iomap_table(pdev)[pci_bar_index];
+
+ intcsr_map = devm_regmap_init_mmio(dev, pex8311_regs, &pex8311_intcsr_regmap_config);
+ if (IS_ERR(intcsr_map))
+ return dev_err_probe(dev, PTR_ERR(intcsr_map),
+ "Unable to initialize PEX8311 register map\n");
+
+ idio24gpio = devm_kzalloc(dev, sizeof(*idio24gpio), GFP_KERNEL);
+ if (!idio24gpio)
+ return -ENOMEM;
+
+ idio24gpio->map = devm_regmap_init_mmio(dev, idio_24_regs, &idio_24_regmap_config);
+ if (IS_ERR(idio24gpio->map))
+ return dev_err_probe(dev, PTR_ERR(idio24gpio->map),
+ "Unable to initialize register map\n");
raw_spin_lock_init(&idio24gpio->lock);
+ /* Initialize all IRQ type configuration to IRQ_TYPE_EDGE_BOTH */
+ idio24gpio->irq_type = GENMASK(7, 0);
+
+ chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ chip->name = name;
+ chip->status_base = IDIO_24_COS_STATUS_BASE;
+ chip->mask_base = IDIO_24_COS_ENABLE;
+ chip->ack_base = IDIO_24_COS_STATUS_BASE;
+ chip->num_regs = 4;
+ chip->irqs = idio_24_regmap_irqs;
+ chip->num_irqs = ARRAY_SIZE(idio_24_regmap_irqs);
+ chip->handle_mask_sync = idio_24_handle_mask_sync;
+ chip->set_type_config = idio_24_set_type_config;
+ chip->irq_drv_data = idio24gpio;
+
/* Software board reset */
- iowrite8(0, &idio24gpio->reg->soft_reset);
+ err = regmap_write(idio24gpio->map, IDIO_24_SOFT_RESET, 0);
+ if (err)
+ return err;
/*
* enable PLX PEX8311 internal PCI wire interrupt and local interrupt
* input
*/
- iowrite8((INTCSR_INTERNAL_PCI_WIRE | INTCSR_LOCAL_INPUT) >> 8,
- idio24gpio->plx + PLX_PEX8311_PCI_LCS_INTCSR + 1);
-
- err = devm_gpiochip_add_data(dev, &idio24gpio->chip, idio24gpio);
- if (err) {
- dev_err(dev, "GPIO registering failed (%d)\n", err);
+ err = regmap_update_bits(intcsr_map, 0x0, IDIO_24_ENABLE_IRQ, IDIO_24_ENABLE_IRQ);
+ if (err)
return err;
- }
-
- err = devm_request_irq(dev, pdev->irq, idio_24_irq_handler, IRQF_SHARED,
- name, idio24gpio);
- if (err) {
- dev_err(dev, "IRQ handler registering failed (%d)\n", err);
- return err;
- }
- return 0;
+ err = devm_regmap_add_irq_chip(dev, idio24gpio->map, pdev->irq, 0, 0, chip, &chip_data);
+ if (err)
+ return dev_err_probe(dev, err, "IRQ registration failed\n");
+
+ gpio_config.parent = dev;
+ gpio_config.regmap = idio24gpio->map;
+ gpio_config.ngpio = IDIO_24_NGPIO;
+ gpio_config.names = idio_24_names;
+ gpio_config.reg_dat_base = GPIO_REGMAP_ADDR(IDIO_24_OUT_BASE);
+ gpio_config.reg_set_base = GPIO_REGMAP_ADDR(IDIO_24_OUT_BASE);
+ gpio_config.reg_dir_out_base = GPIO_REGMAP_ADDR(IDIO_24_CONTROL_REG);
+ gpio_config.ngpio_per_reg = IDIO_24_NGPIO_PER_REG;
+ gpio_config.irq_domain = regmap_irq_get_domain(chip_data);
+ gpio_config.reg_mask_xlate = idio_24_reg_mask_xlate;
+ gpio_config.drvdata = idio24gpio->map;
+
+ return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config));
}
static const struct pci_device_id idio_24_pci_dev_id[] = {
--
2.41.0
The WinSystems WS16C48 I/O address region spans offsets 0x0 through 0xA,
which is a total of 11 bytes. Fix the WS16C48_EXTENT define to the
correct value of 11 so that access to necessary device registers is
properly requested in the ws16c48_probe() callback by the
devm_request_region() function call.
Fixes: 2c05a0f29f41 ("gpio: ws16c48: Implement and utilize register structures")
Cc: [email protected]
Cc: Paul Demetrotion <[email protected]>
Signed-off-by: William Breathitt Gray <[email protected]>
---
drivers/gpio/gpio-ws16c48.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/gpio-ws16c48.c b/drivers/gpio/gpio-ws16c48.c
index 701847508e94..6289b0510cf2 100644
--- a/drivers/gpio/gpio-ws16c48.c
+++ b/drivers/gpio/gpio-ws16c48.c
@@ -17,7 +17,7 @@
#include <linux/regmap.h>
#include <linux/types.h>
-#define WS16C48_EXTENT 10
+#define WS16C48_EXTENT 11
#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
static unsigned int base[MAX_NUM_WS16C48];
--
2.41.0
The regmap API supports IO port accessors so we can take advantage of
regmap abstractions rather than handling access to the device registers
directly in the driver. Migrate the 104-idio-16 module to the new
idio-16 library interface leveraging the gpio-regmap API.
Suggested-by: Andy Shevchenko <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/1f24a1f18c9a9daa4983713e0a5b53e838d624a8.1680618405.git.william.gray@linaro.org/
Signed-off-by: William Breathitt Gray <[email protected]>
---
drivers/gpio/Kconfig | 2 +-
drivers/gpio/gpio-104-idio-16.c | 286 +++++++-------------------------
2 files changed, 64 insertions(+), 224 deletions(-)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 7f5cc69fff23..8bc60a6ce3a9 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -872,7 +872,7 @@ config GPIO_104_IDIO_16
tristate "ACCES 104-IDIO-16 GPIO support"
depends on PC104
select ISA_BUS_API
- select GPIOLIB_IRQCHIP
+ select REGMAP_MMIO
select GPIO_IDIO_16
help
Enables GPIO support for the ACCES 104-IDIO-16 family (104-IDIO-16,
diff --git a/drivers/gpio/gpio-104-idio-16.c b/drivers/gpio/gpio-104-idio-16.c
index 098fbefdbe22..f03ccd0f534c 100644
--- a/drivers/gpio/gpio-104-idio-16.c
+++ b/drivers/gpio/gpio-104-idio-16.c
@@ -6,19 +6,16 @@
* This driver supports the following ACCES devices: 104-IDIO-16,
* 104-IDIO-16E, 104-IDO-16, 104-IDIO-8, 104-IDIO-8E, and 104-IDO-8.
*/
-#include <linux/bitmap.h>
+#include <linux/bits.h>
#include <linux/device.h>
-#include <linux/errno.h>
-#include <linux/gpio/driver.h>
-#include <linux/io.h>
+#include <linux/err.h>
#include <linux/ioport.h>
-#include <linux/interrupt.h>
-#include <linux/irqdesc.h>
+#include <linux/irq.h>
#include <linux/isa.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
-#include <linux/spinlock.h>
+#include <linux/regmap.h>
#include <linux/types.h>
#include "gpio-idio-16.h"
@@ -36,187 +33,62 @@ static unsigned int num_irq;
module_param_hw_array(irq, uint, irq, &num_irq, 0);
MODULE_PARM_DESC(irq, "ACCES 104-IDIO-16 interrupt line numbers");
-/**
- * struct idio_16_gpio - GPIO device private data structure
- * @chip: instance of the gpio_chip
- * @lock: synchronization lock to prevent I/O race conditions
- * @irq_mask: I/O bits affected by interrupts
- * @reg: I/O address offset for the device registers
- * @state: ACCES IDIO-16 device state
- */
-struct idio_16_gpio {
- struct gpio_chip chip;
- raw_spinlock_t lock;
- unsigned long irq_mask;
- struct idio_16 __iomem *reg;
- struct idio_16_state state;
+static const struct regmap_range idio_16_wr_ranges[] = {
+ regmap_reg_range(0x0, 0x2), regmap_reg_range(0x4, 0x4),
};
-
-static int idio_16_gpio_get_direction(struct gpio_chip *chip,
- unsigned int offset)
-{
- if (idio_16_get_direction(offset))
- return GPIO_LINE_DIRECTION_IN;
-
- return GPIO_LINE_DIRECTION_OUT;
-}
-
-static int idio_16_gpio_direction_input(struct gpio_chip *chip,
- unsigned int offset)
-{
- return 0;
-}
-
-static int idio_16_gpio_direction_output(struct gpio_chip *chip,
- unsigned int offset, int value)
-{
- chip->set(chip, offset, value);
- return 0;
-}
-
-static int idio_16_gpio_get(struct gpio_chip *chip, unsigned int offset)
-{
- struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
-
- return idio_16_get(idio16gpio->reg, &idio16gpio->state, offset);
-}
-
-static int idio_16_gpio_get_multiple(struct gpio_chip *chip,
- unsigned long *mask, unsigned long *bits)
-{
- struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
-
- idio_16_get_multiple(idio16gpio->reg, &idio16gpio->state, mask, bits);
-
- return 0;
-}
-
-static void idio_16_gpio_set(struct gpio_chip *chip, unsigned int offset,
- int value)
-{
- struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
-
- idio_16_set(idio16gpio->reg, &idio16gpio->state, offset, value);
-}
-
-static void idio_16_gpio_set_multiple(struct gpio_chip *chip,
- unsigned long *mask, unsigned long *bits)
-{
- struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
-
- idio_16_set_multiple(idio16gpio->reg, &idio16gpio->state, mask, bits);
-}
-
-static void idio_16_irq_ack(struct irq_data *data)
-{
-}
-
-static void idio_16_irq_mask(struct irq_data *data)
-{
- struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
- struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
- const unsigned long offset = irqd_to_hwirq(data);
- unsigned long flags;
-
- idio16gpio->irq_mask &= ~BIT(offset);
- gpiochip_disable_irq(chip, offset);
-
- if (!idio16gpio->irq_mask) {
- raw_spin_lock_irqsave(&idio16gpio->lock, flags);
-
- iowrite8(0, &idio16gpio->reg->irq_ctl);
-
- raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
- }
-}
-
-static void idio_16_irq_unmask(struct irq_data *data)
-{
- struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
- struct idio_16_gpio *const idio16gpio = gpiochip_get_data(chip);
- const unsigned long offset = irqd_to_hwirq(data);
- const unsigned long prev_irq_mask = idio16gpio->irq_mask;
- unsigned long flags;
-
- gpiochip_enable_irq(chip, offset);
- idio16gpio->irq_mask |= BIT(offset);
-
- if (!prev_irq_mask) {
- raw_spin_lock_irqsave(&idio16gpio->lock, flags);
-
- ioread8(&idio16gpio->reg->irq_ctl);
-
- raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
- }
-}
-
-static int idio_16_irq_set_type(struct irq_data *data, unsigned int flow_type)
-{
- /* The only valid irq types are none and both-edges */
- if (flow_type != IRQ_TYPE_NONE &&
- (flow_type & IRQ_TYPE_EDGE_BOTH) != IRQ_TYPE_EDGE_BOTH)
- return -EINVAL;
-
- return 0;
-}
-
-static const struct irq_chip idio_16_irqchip = {
- .name = "104-idio-16",
- .irq_ack = idio_16_irq_ack,
- .irq_mask = idio_16_irq_mask,
- .irq_unmask = idio_16_irq_unmask,
- .irq_set_type = idio_16_irq_set_type,
- .flags = IRQCHIP_IMMUTABLE,
- GPIOCHIP_IRQ_RESOURCE_HELPERS,
+static const struct regmap_range idio_16_rd_ranges[] = {
+ regmap_reg_range(0x1, 0x2), regmap_reg_range(0x5, 0x5),
};
-
-static irqreturn_t idio_16_irq_handler(int irq, void *dev_id)
-{
- struct idio_16_gpio *const idio16gpio = dev_id;
- struct gpio_chip *const chip = &idio16gpio->chip;
- int gpio;
-
- for_each_set_bit(gpio, &idio16gpio->irq_mask, chip->ngpio)
- generic_handle_domain_irq(chip->irq.domain, gpio);
-
- raw_spin_lock(&idio16gpio->lock);
-
- iowrite8(0, &idio16gpio->reg->in0_7);
-
- raw_spin_unlock(&idio16gpio->lock);
-
- return IRQ_HANDLED;
-}
-
-#define IDIO_16_NGPIO 32
-static const char *idio_16_names[IDIO_16_NGPIO] = {
- "OUT0", "OUT1", "OUT2", "OUT3", "OUT4", "OUT5", "OUT6", "OUT7",
- "OUT8", "OUT9", "OUT10", "OUT11", "OUT12", "OUT13", "OUT14", "OUT15",
- "IIN0", "IIN1", "IIN2", "IIN3", "IIN4", "IIN5", "IIN6", "IIN7",
- "IIN8", "IIN9", "IIN10", "IIN11", "IIN12", "IIN13", "IIN14", "IIN15"
+static const struct regmap_range idio_16_precious_ranges[] = {
+ regmap_reg_range(0x2, 0x2),
+};
+static const struct regmap_access_table idio_16_wr_table = {
+ .yes_ranges = idio_16_wr_ranges,
+ .n_yes_ranges = ARRAY_SIZE(idio_16_wr_ranges),
+};
+static const struct regmap_access_table idio_16_rd_table = {
+ .yes_ranges = idio_16_rd_ranges,
+ .n_yes_ranges = ARRAY_SIZE(idio_16_rd_ranges),
+};
+static const struct regmap_access_table idio_16_precious_table = {
+ .yes_ranges = idio_16_precious_ranges,
+ .n_yes_ranges = ARRAY_SIZE(idio_16_precious_ranges),
+};
+static const struct regmap_config idio_16_regmap_config = {
+ .reg_bits = 8,
+ .reg_stride = 1,
+ .val_bits = 8,
+ .io_port = true,
+ .wr_table = &idio_16_wr_table,
+ .rd_table = &idio_16_rd_table,
+ .volatile_table = &idio_16_rd_table,
+ .precious_table = &idio_16_precious_table,
+ .cache_type = REGCACHE_FLAT,
+ .use_raw_spinlock = true,
};
-static int idio_16_irq_init_hw(struct gpio_chip *gc)
-{
- struct idio_16_gpio *const idio16gpio = gpiochip_get_data(gc);
-
- /* Disable IRQ by default */
- iowrite8(0, &idio16gpio->reg->irq_ctl);
- iowrite8(0, &idio16gpio->reg->in0_7);
+/* Only input lines (GPIO 16-31) support interrupts */
+#define IDIO_16_REGMAP_IRQ(_id) \
+ [16 + _id] = { \
+ .mask = BIT(_id), \
+ .type = { .types_supported = IRQ_TYPE_EDGE_BOTH }, \
+ }
- return 0;
-}
+static const struct regmap_irq idio_16_regmap_irqs[] = {
+ IDIO_16_REGMAP_IRQ(0), IDIO_16_REGMAP_IRQ(1), IDIO_16_REGMAP_IRQ(2), /* 0-2 */
+ IDIO_16_REGMAP_IRQ(3), IDIO_16_REGMAP_IRQ(4), IDIO_16_REGMAP_IRQ(5), /* 3-5 */
+ IDIO_16_REGMAP_IRQ(6), IDIO_16_REGMAP_IRQ(7), IDIO_16_REGMAP_IRQ(8), /* 6-8 */
+ IDIO_16_REGMAP_IRQ(9), IDIO_16_REGMAP_IRQ(10), IDIO_16_REGMAP_IRQ(11), /* 9-11 */
+ IDIO_16_REGMAP_IRQ(12), IDIO_16_REGMAP_IRQ(13), IDIO_16_REGMAP_IRQ(14), /* 12-14 */
+ IDIO_16_REGMAP_IRQ(15), /* 15 */
+};
static int idio_16_probe(struct device *dev, unsigned int id)
{
- struct idio_16_gpio *idio16gpio;
const char *const name = dev_name(dev);
- struct gpio_irq_chip *girq;
- int err;
-
- idio16gpio = devm_kzalloc(dev, sizeof(*idio16gpio), GFP_KERNEL);
- if (!idio16gpio)
- return -ENOMEM;
+ struct idio_16_regmap_config config = {};
+ void __iomem *regs;
+ struct regmap *map;
if (!devm_request_region(dev, base[id], IDIO_16_EXTENT, name)) {
dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
@@ -224,54 +96,22 @@ static int idio_16_probe(struct device *dev, unsigned int id)
return -EBUSY;
}
- idio16gpio->reg = devm_ioport_map(dev, base[id], IDIO_16_EXTENT);
- if (!idio16gpio->reg)
+ regs = devm_ioport_map(dev, base[id], IDIO_16_EXTENT);
+ if (!regs)
return -ENOMEM;
- idio16gpio->chip.label = name;
- idio16gpio->chip.parent = dev;
- idio16gpio->chip.owner = THIS_MODULE;
- idio16gpio->chip.base = -1;
- idio16gpio->chip.ngpio = IDIO_16_NGPIO;
- idio16gpio->chip.names = idio_16_names;
- idio16gpio->chip.get_direction = idio_16_gpio_get_direction;
- idio16gpio->chip.direction_input = idio_16_gpio_direction_input;
- idio16gpio->chip.direction_output = idio_16_gpio_direction_output;
- idio16gpio->chip.get = idio_16_gpio_get;
- idio16gpio->chip.get_multiple = idio_16_gpio_get_multiple;
- idio16gpio->chip.set = idio_16_gpio_set;
- idio16gpio->chip.set_multiple = idio_16_gpio_set_multiple;
-
- idio_16_state_init(&idio16gpio->state);
- /* FET off states are represented by bit values of "1" */
- bitmap_fill(idio16gpio->state.out_state, IDIO_16_NOUT);
-
- girq = &idio16gpio->chip.irq;
- gpio_irq_chip_set_chip(girq, &idio_16_irqchip);
- /* This will let us handle the parent IRQ in the driver */
- girq->parent_handler = NULL;
- girq->num_parents = 0;
- girq->parents = NULL;
- girq->default_type = IRQ_TYPE_NONE;
- girq->handler = handle_edge_irq;
- girq->init_hw = idio_16_irq_init_hw;
+ map = devm_regmap_init_mmio(dev, regs, &idio_16_regmap_config);
+ if (IS_ERR(map))
+ return dev_err_probe(dev, PTR_ERR(map), "Unable to initialize register map\n");
- raw_spin_lock_init(&idio16gpio->lock);
-
- err = devm_gpiochip_add_data(dev, &idio16gpio->chip, idio16gpio);
- if (err) {
- dev_err(dev, "GPIO registering failed (%d)\n", err);
- return err;
- }
-
- err = devm_request_irq(dev, irq[id], idio_16_irq_handler, 0, name,
- idio16gpio);
- if (err) {
- dev_err(dev, "IRQ handler registering failed (%d)\n", err);
- return err;
- }
+ config.parent = dev;
+ config.map = map;
+ config.regmap_irqs = idio_16_regmap_irqs;
+ config.num_regmap_irqs = ARRAY_SIZE(idio_16_regmap_irqs);
+ config.irq = irq[id];
+ config.no_status = true;
- return 0;
+ return devm_idio_16_regmap_register(dev, &config);
}
static struct isa_driver idio_16_driver = {
--
2.41.0
On Thu, Aug 10, 2023 at 06:00:44PM -0400, William Breathitt Gray wrote:
> The WinSystems WS16C48 I/O address region spans offsets 0x0 through 0xA,
> which is a total of 11 bytes. Fix the WS16C48_EXTENT define to the
> correct value of 11 so that access to necessary device registers is
> properly requested in the ws16c48_probe() callback by the
> devm_request_region() function call.
>
> Fixes: 2c05a0f29f41 ("gpio: ws16c48: Implement and utilize register structures")
Fixes should go first in the series, but I see no conflict here, I hope Bart
can manage this when applying.
Reviewed-by: Andy Shevchenko <[email protected]>
--
With Best Regards,
Andy Shevchenko
On Fri, Aug 11, 2023 at 12:00 AM William Breathitt Gray
<[email protected]> wrote:
> This patchset is a collection and resend of the lingering GPIO patches
> for the regmap migration of the ACCES and WinSystems drivers.[^1][^2]
> Previously, these patches were postponed due to pending dependency
> patches that have since been merged into mainline. Now that those
> dependencies are present in the GPIO tree, this patchset can be merged
> without incident. An IRQ handling fix for the ws16c48 driver is also
> included at the end.[^3]
The series:
Reviewed-by: Linus Walleij <[email protected]>
The result is really nice!
Yours,
Linus Walleij
On Fri, Aug 11, 2023 at 12:19:54PM +0300, Andy Shevchenko wrote:
> On Thu, Aug 10, 2023 at 06:00:44PM -0400, William Breathitt Gray wrote:
> > The WinSystems WS16C48 I/O address region spans offsets 0x0 through 0xA,
> > which is a total of 11 bytes. Fix the WS16C48_EXTENT define to the
> > correct value of 11 so that access to necessary device registers is
> > properly requested in the ws16c48_probe() callback by the
> > devm_request_region() function call.
> >
> > Fixes: 2c05a0f29f41 ("gpio: ws16c48: Implement and utilize register structures")
>
> Fixes should go first in the series, but I see no conflict here, I hope Bart
> can manage this when applying.
>
> Reviewed-by: Andy Shevchenko <[email protected]>
>
> --
> With Best Regards,
> Andy Shevchenko
Bart, if you encounter any issues reordering this patch first before the
others, just let me know and I'll send a rebased version with the
appropriate context adjustments.
Thanks,
William Breathitt Gray
On Fri, Aug 11, 2023 at 12:01 AM William Breathitt Gray
<[email protected]> wrote:
>
> This patchset is a collection and resend of the lingering GPIO patches
> for the regmap migration of the ACCES and WinSystems drivers.[^1][^2]
> Previously, these patches were postponed due to pending dependency
> patches that have since been merged into mainline. Now that those
> dependencies are present in the GPIO tree, this patchset can be merged
> without incident. An IRQ handling fix for the ws16c48 driver is also
> included at the end.[^3]
>
> [^1] https://lore.kernel.org/all/[email protected]/
> [^2] https://lore.kernel.org/all/[email protected]/
> [^3] https://lore.kernel.org/all/[email protected]/
>
> William Breathitt Gray (7):
> gpio: idio-16: Migrate to the regmap API
> gpio: 104-idio-16: Migrate to the regmap API
> gpio: pci-idio-16: Migrate to the regmap API
> gpio: idio-16: Remove unused legacy interface
> gpio: pcie-idio-24: Migrate to the regmap API
> gpio: ws16c48: Migrate to the regmap API
> gpio: ws16c48: Fix off-by-one error in WS16C48 resource region extent
>
> drivers/gpio/Kconfig | 13 +-
> drivers/gpio/gpio-104-idio-16.c | 286 +++----------
> drivers/gpio/gpio-idio-16.c | 254 ++++++------
> drivers/gpio/gpio-idio-16.h | 79 +---
> drivers/gpio/gpio-pci-idio-16.c | 294 +++-----------
> drivers/gpio/gpio-pcie-idio-24.c | 677 +++++++++++--------------------
> drivers/gpio/gpio-ws16c48.c | 554 +++++++++----------------
> 7 files changed, 728 insertions(+), 1429 deletions(-)
>
>
> base-commit: 87d0688483f56c748b37a5298bdc382df5cf8f74
> --
> 2.41.0
>
Queued the last patch for fixes and the rest for v6.6.
Bart