Hi Jim,
Jim Quinlan <[email protected]> (2023-06-23):
> v6 -- No code has been changed.
> -- Changed commit subject and comment in "#PERST" commit (Bjorn, Cyril)
> -- Changed sign-off and author email address for all commits.
> This was due to a change in Broadcom's upstreaming policy.
I've just run some more tests to be on the safe side, and I can confirm
everything is still looking good with the updated series and the updated
base commit.
Test setup:
-----------
- using a $CM with the 20230111 EEPROM
- on the same CM4 IO Board
- with a $PCIE board (PCIe to multiple USB ports)
- and the same Samsung USB flash drive.
where $CM is one of:
- CM4 Lite Rev 1.0
- CM4 8/32 Rev 1.0
- CM4 4/32 Rev 1.1
and $PCIE is one of:
- SupaHub PCE6U1C-R02, VER 006
- SupaHub PCE6U1C-R02, VER 006S
Results:
--------
1. With an unpatched kernel, I'm getting the dreaded Serror for all
$CM/$PCIE combinations. That's reproducible with:
- the 6.1.y kernel shipped in Debian 12;
- a locally-built v6.4-rc7-194-g8a28a0b6f1a1d kernel.
2. With a patched kernel (v6.4-rc7-194-g8a28a0b6f1a1d + this series),
for all $CM/$PCIE combinations, I'm getting a system that boots,
sees the flash drive, and gives decent read performance on the USB
flash drive (200+ MB/s on the CM4 Lite, 220+ MB/s on the non-Lite
versions).
In passing, since that looks like it could be merged finally: I suppose
it's fair to say this series adds support for hardware that wasn't
working before, which means it's not a candidate for inclusion via
stable@ (even if it gets rid of a nasty failure to boot depending on
what hardware is plugged in at that time)?
In other words, downstream distributions should be expected to either
adjust their build systems to pick some future Linux release or consider
backporting this series on their own, to each base Linux version they
support?
Thanks again for all the help figuring this out.
Cheers,
--
Cyril Brulebois ([email protected]) <https://debamax.com/>
D-I release manager -- Release team member -- Freelance Consultant
On Fri, Jun 23, 2023 at 10:40:56AM -0400, Jim Quinlan wrote:
> During long periods of the PCIe RC HW being in an L1SS sleep state, there
> may be a timeout on an internal bus access, even though there may not be
> any PCIe access involved. Such a timeout will cause a subsequent CPU
> abort.
>
> So, when "brcm,enable-l1ss" is observed, we increase the timeout value to
> four seconds instead of using its HW default.
>
> Signed-off-by: Jim Quinlan <[email protected]>
> Tested-by: Florian Fainelli <[email protected]>
> ---
> drivers/pci/controller/pcie-brcmstb.c | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index d30636a725d7..fe0415a98c63 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -1034,6 +1034,21 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> return 0;
> }
>
> +/*
> + * This extends the timeout period for an access to an internal bus. This
> + * access timeout may occur during L1SS sleep periods even without the
> + * presence of a PCIe access.
> + */
> +static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
> +{
> + /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */
> + const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
Nit: you could define an offset for the TIMEOUT register, if that makes
it any cleaner, up to you.
> + u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
It would be useful to describe why this has to be 4 seconds in case
someone in the future will have to change it.
Thanks,
Lorenzo
> + /* Each unit in timeout register is 1/216,000,000 seconds */
> + writel(216 * timeout_us, pcie->base + REG_OFFSET);
> +}
> +
> static void brcm_config_clkreq(struct brcm_pcie *pcie)
> {
> bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss");
> @@ -1059,6 +1074,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie)
> * of 400ns, as specified in 3.2.5.2.2 of the PCI Express
> * Mini CEM 2.0 specification.
> */
> + brcm_extend_rbus_timeout(pcie);
> clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
> dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings");
> } else {
> --
> 2.17.1
>
On Mon, Aug 14, 2023 at 03:30:07PM -0400, Jim Quinlan wrote:
> On Fri, Jul 28, 2023 at 12:15 PM Jim Quinlan <[email protected]> wrote:
> > On Thu, Jul 27, 2023, 10:44 PM Lorenzo Pieralisi <[email protected]> wrote:
> >> On Fri, Jun 23, 2023 at 10:40:56AM -0400, Jim Quinlan wrote:
> >> > During long periods of the PCIe RC HW being in an L1SS sleep state, there
> >> > may be a timeout on an internal bus access, even though there may not be
> >> > any PCIe access involved. Such a timeout will cause a subsequent CPU
> >> > abort.
> >> >
> >> > So, when "brcm,enable-l1ss" is observed, we increase the timeout value to
> >> > four seconds instead of using its HW default.
> >> >
> >> > Signed-off-by: Jim Quinlan <[email protected]>
> >> > Tested-by: Florian Fainelli <[email protected]>
> >> > ---
> >> > drivers/pci/controller/pcie-brcmstb.c | 16 ++++++++++++++++
> >> > 1 file changed, 16 insertions(+)
> >> >
> >> > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> >> > index d30636a725d7..fe0415a98c63 100644
> >> > --- a/drivers/pci/controller/pcie-brcmstb.c
> >> > +++ b/drivers/pci/controller/pcie-brcmstb.c
> >> > @@ -1034,6 +1034,21 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> >> > return 0;
> >> > }
> >> >
> >> > +/*
> >> > + * This extends the timeout period for an access to an internal bus. This
> >> > + * access timeout may occur during L1SS sleep periods even without the
> >> > + * presence of a PCIe access.
> >> > + */
> >> > +static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
> >> > +{
> >> > + /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */
> >> > + const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
> >>
> >> Nit: you could define an offset for the TIMEOUT register, if that makes
> >> it any cleaner, up to you.
> >>
> >> > + u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
> >>
> >> It would be useful to describe why this has to be 4 seconds in case
> >> someone in the future will have to change it.
> >
> > IIRC our customer requested 2s and we doubled it. Bjorn, can you
> > please add this comment or a paraphrase of it before applying --
> > I'm currently on vacation.
>
> Is the above request okay with you? What is the status of these
> commits -- will they be applied to pci-next in the near future?
The "brcm,enable-l1ss" DT property is either unnecessary or an
indication of a hardware defect in the controller.
Requiring the property is a terrible user experience, completely
antithetical to the PCI compatibility story, and per the conversation
at [1], there are no known problems that would occur if we ignored
"brcm,enable-l1ss" and always configured mode (c) ("Bidirectional
CLKREQ# for L1SS capable devices").
Even when configured as mode (c), L1SS is not *always* enabled. It's
certainly not enabled before ASPM init, and users can always disable
L1SS whenever they desire via the sysfs interfaces or pcie_aspm=off,
so if there's some problem with running in mode (c) with L1SS
disabled, we're still likely to see it.
But if you want to require the DT property, I guess it's mainly an
issue for you and your customers.
So to answer your question, yes, I'm OK with this series.
Bjorn
[1] https://lore.kernel.org/r/[email protected]
> >> > + /* Each unit in timeout register is 1/216,000,000 seconds */
> >> > + writel(216 * timeout_us, pcie->base + REG_OFFSET);
> >> > +}
> >> > +
> >> > static void brcm_config_clkreq(struct brcm_pcie *pcie)
> >> > {
> >> > bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss");
> >> > @@ -1059,6 +1074,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie)
> >> > * of 400ns, as specified in 3.2.5.2.2 of the PCI Express
> >> > * Mini CEM 2.0 specification.
> >> > */
> >> > + brcm_extend_rbus_timeout(pcie);
> >> > clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK;
> >> > dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings");
> >> > } else {
On Fri, Jun 23, 2023 at 10:40:53AM -0400, Jim Quinlan wrote:
> v6 -- No code has been changed.
> -- Changed commit subject and comment in "#PERST" commit (Bjorn, Cyril)
> -- Changed sign-off and author email address for all commits.
> This was due to a change in Broadcom's upstreaming policy.
>
> v5 -- Remove DT property "brcm,completion-timeout-us" from
> "DT bindings" commit. Although this error may be reported
> as a completion timeout, its cause was traced to an
> internal bus timeout which may occur even when there is
> no PCIe access being processed. We set a timeout of four
> seconds only if we are operating in "L1SS CLKREQ#" mode.
> -- Correct CEM 2.0 reference provided by HW engineer,
> s/3.2.5.2.5/3.2.5.2.2/ (Bjorn)
> -- Add newline to dev_info() string (Stefan)
> -- Change variable rval to unsigned (Stefan)
> -- s/implementaion/implementation/ (Bjorn)
> -- s/superpowersave/powersupersave/ (Bjorn)
> -- Slightly modify message on "PERST#" commit.
> -- Rebase to torvalds master
>
> v4 -- New commit that asserts PERST# for 2711/RPi SOCs at PCIe RC
> driver probe() time. This is done in Raspian Linux and its
> absence may be the cause of a failing test case.
> -- New commit that removes stale comment.
>
> v3 -- Rewrote commit msgs and comments refering panics if L1SS
> is enabled/disabled; the code snippet that unadvertises L1SS
> eliminates the panic scenario. (Bjorn)
> -- Add reference for "400ns of CLKREQ# assertion" blurb (Bjorn)
> -- Put binding names in DT commit Subject (Bjorn)
> -- Add a verb to a commit's subject line (Bjorn)
> -- s/accomodat(\w+)/accommodat$1/g (Bjorn)
> -- Rewrote commit msgs and comments refering panics if L1SS
> is enabled/disabled; the code snippet that unadvertises L1SS
> eliminates the panic scenario. (Bjorn)
>
> v2 -- Changed binding property 'brcm,completion-timeout-msec' to
> 'brcm,completion-timeout-us'. (StefanW for standard suffix).
> -- Warn when clamping timeout value, and include clamped
> region in message. Also add min and max in YAML. (StefanW)
> -- Qualify description of "brcm,completion-timeout-us" so that
> it refers to PCIe transactions. (StefanW)
> -- Remvove mention of Linux specifics in binding description. (StefanW)
> -- s/clkreq#/CLKREQ#/g (Bjorn)
> -- Refactor completion-timeout-us code to compare max and min to
> value given by the property (as opposed to the computed value).
>
> v1 -- The current driver assumes the downstream devices can
> provide CLKREQ# for ASPM. These commits accomodate devices
> w/ or w/o clkreq# and also handle L1SS-capable devices.
>
> -- The Raspian Linux folks have already been using a PCIe RC
> property "brcm,enable-l1ss". These commits use the same
> property, in a backward-compatible manner, and the implementaion
> adds more detail and also automatically identifies devices w/o
> a clkreq# signal, i.e. most devices plugged into an RPi CM4
> IO board.
>
>
> Jim Quinlan (5):
> dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property
> PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream
> device
I am not merging the first two patches since the discussion thread
is still open and I'd like to understand better what can/should be
done, sorry.
> PCI: brcmstb: Set higher value for internal bus timeout
> PCI: brcmstb: Assert PERST# on BCM2711
> PCI: brcmstb: Remove stale comment
Is it OK to apply these three on their own ? Overall it would be
great to avoid mixing patches with different end goals in a single
series.
Thanks,
Lorenzo
> .../bindings/pci/brcm,stb-pcie.yaml | 9 ++
> drivers/pci/controller/pcie-brcmstb.c | 91 ++++++++++++++++---
> 2 files changed, 89 insertions(+), 11 deletions(-)
>
>
> base-commit: 8a28a0b6f1a1dcbf5a834600a9acfbe2ba51e5eb
> --
> 2.17.1
>
On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> This commit adds the boolean "brcm,enable-l1ss" property:
>
> The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> requires the driver probe() to deliberately place the HW one of three
> CLKREQ# modes:
>
> (a) CLKREQ# driven by the RC unconditionally
> (b) CLKREQ# driven by the EP for ASPM L0s, L1
> (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
>
> The HW+driver can tell the difference between downstream devices that
> need (a) and (b), but does not know when to configure (c). All devices
> should work fine when the driver chooses (a) or (b), but (c) may be
> desired to realize the extra power savings that L1SS offers. So we
> introduce the boolean "brcm,enable-l1ss" property to inform the driver
> that (c) is desired. Setting this property only makes sense when the
> downstream device is L1SS-capable and the OS is configured to activate
> this mode (e.g. policy==powersupersave).
>
> This property is already present in the Raspian version of Linux, but the
> upstream driver implementation that follows adds more details and
> discerns between (a) and (b).
>
> Signed-off-by: Jim Quinlan <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> ---
> Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> index 7e15aae7d69e..8b61c2179608 100644
> --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> @@ -64,6 +64,15 @@ properties:
>
> aspm-no-l0s: true
>
> + brcm,enable-l1ss:
> + description: Indicates that PCIe L1SS power savings
> + are desired, the downstream device is L1SS-capable, and the
> + OS has been configured to enable this mode. For boards
What does this mean ? I don't think DT properties are supposed
to carry information related to how the OS is configured.
Again - it depends on what DT should be used for, I am not claiming to
have any authority on that, just asking.
Thanks,
Lorenzo
> + using a mini-card connector, this mode may not meet the
> + TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> + of the PCI Express Mini CEM 2.0 specification.
> + type: boolean
> +
> brcm,scb-sizes:
> description: u64 giving the 64bit PCIe memory
> viewport size of a memory controller. There may be up to
> --
> 2.17.1
>
On Mon, Aug 21, 2023 at 11:25:11AM -0400, Jim Quinlan wrote:
> On Mon, Aug 21, 2023 at 10:47 AM Lorenzo Pieralisi
> <[email protected]> wrote:
> >
> > On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> > > This commit adds the boolean "brcm,enable-l1ss" property:
> > >
> > > The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > requires the driver probe() to deliberately place the HW one of three
> > > CLKREQ# modes:
> > >
> > > (a) CLKREQ# driven by the RC unconditionally
> > > (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > >
> > > The HW+driver can tell the difference between downstream devices that
> > > need (a) and (b), but does not know when to configure (c). All devices
> > > should work fine when the driver chooses (a) or (b), but (c) may be
> > > desired to realize the extra power savings that L1SS offers. So we
> > > introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > that (c) is desired. Setting this property only makes sense when the
> > > downstream device is L1SS-capable and the OS is configured to activate
> > > this mode (e.g. policy==powersupersave).
> > >
> > > This property is already present in the Raspian version of Linux, but the
> > > upstream driver implementation that follows adds more details and
> > > discerns between (a) and (b).
> > >
> > > Signed-off-by: Jim Quinlan <[email protected]>
> > > Reviewed-by: Rob Herring <[email protected]>
> > > ---
> > > Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > 1 file changed, 9 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > index 7e15aae7d69e..8b61c2179608 100644
> > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > @@ -64,6 +64,15 @@ properties:
> > >
> > > aspm-no-l0s: true
> > >
> > > + brcm,enable-l1ss:
> > > + description: Indicates that PCIe L1SS power savings
> > > + are desired, the downstream device is L1SS-capable, and the
> > > + OS has been configured to enable this mode. For boards
> >
> > What does this mean ? I don't think DT properties are supposed
> > to carry information related to how the OS is configured.
>
> The DT setting in question is unrelated to the statement "and the OS
> has been configured to
> enable this mode".
>
> This is merely saying that even if you enable "brcm,l1ss-enable"
> that you may not get L1SS power savings w/o setting
> "CONFIG_PCIEASPM_POWER_SUPERSAVE=y".
> I mentioned that exact term but a reviewer nakked it because
> apparently DT descriptions should not be OS specific.
>
> I am actually open for this to be a command-line option but I wanted to honor
> what the Raspian OS folks have already done. RaspianOS already has
> "brcm,enable-l1ss"
> set in their DTS files.
This is about the mainline kernel, I don't have any visibility into
downstream kernels (where that property management was added without DT
and PCI maintainers supervision).
Raspian OS folks' choice is theirs but it can't and it shouldn't override
the mainline review process even though I understand the position you
are in.
Thanks,
Lorenzo
>
> Regards,
> Jim
>
> > Again - it depends on what DT should be used for, I am not claiming to
> > have any authority on that, just asking.
> >
> > Thanks,
> > Lorenzo
> >
> > > + using a mini-card connector, this mode may not meet the
> > > + TCRLon maximum time of 400ns, as specified in 3.2.5.2.2
> > > + of the PCI Express Mini CEM 2.0 specification.
> > > + type: boolean
> > > +
> > > brcm,scb-sizes:
> > > description: u64 giving the 64bit PCIe memory
> > > viewport size of a memory controller. There may be up to
> > > --
> > > 2.17.1
> > >
> >
> >
On Wed, Aug 23, 2023 at 2:30 AM Lorenzo Pieralisi <[email protected]> wrote:
>
> On Mon, Aug 21, 2023 at 12:01:50PM -0400, Jim Quinlan wrote:
> > On Mon, Aug 21, 2023 at 11:41 AM Lorenzo Pieralisi
> > <[email protected]> wrote:
> > >
> > > On Mon, Aug 21, 2023 at 11:25:11AM -0400, Jim Quinlan wrote:
> > > > On Mon, Aug 21, 2023 at 10:47 AM Lorenzo Pieralisi
> > > > <[email protected]> wrote:
> > > > >
> > > > > On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> > > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > > >
> > > > > > The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > > > requires the driver probe() to deliberately place the HW one of three
> > > > > > CLKREQ# modes:
> > > > > >
> > > > > > (a) CLKREQ# driven by the RC unconditionally
> > > > > > (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > > > (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > > >
> > > > > > The HW+driver can tell the difference between downstream devices that
> > > > > > need (a) and (b), but does not know when to configure (c). All devices
> > > > > > should work fine when the driver chooses (a) or (b), but (c) may be
> > > > > > desired to realize the extra power savings that L1SS offers. So we
> > > > > > introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > > > that (c) is desired. Setting this property only makes sense when the
> > > > > > downstream device is L1SS-capable and the OS is configured to activate
> > > > > > this mode (e.g. policy==powersupersave).
> > > > > >
> > > > > > This property is already present in the Raspian version of Linux, but the
> > > > > > upstream driver implementation that follows adds more details and
> > > > > > discerns between (a) and (b).
> > > > > >
> > > > > > Signed-off-by: Jim Quinlan <[email protected]>
> > > > > > Reviewed-by: Rob Herring <[email protected]>
> > > > > > ---
> > > > > > Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > > > 1 file changed, 9 insertions(+)
> > > > > >
> > > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > @@ -64,6 +64,15 @@ properties:
> > > > > >
> > > > > > aspm-no-l0s: true
> > > > > >
> > > > > > + brcm,enable-l1ss:
> > > > > > + description: Indicates that PCIe L1SS power savings
> > > > > > + are desired, the downstream device is L1SS-capable, and the
> > > > > > + OS has been configured to enable this mode. For boards
> > > > >
> > > > > What does this mean ? I don't think DT properties are supposed
> > > > > to carry information related to how the OS is configured.
> > > >
> > > > The DT setting in question is unrelated to the statement "and the OS
> > > > has been configured to
> > > > enable this mode".
> > > >
> > > > This is merely saying that even if you enable "brcm,l1ss-enable"
> > > > that you may not get L1SS power savings w/o setting
> > > > "CONFIG_PCIEASPM_POWER_SUPERSAVE=y".
> > > > I mentioned that exact term but a reviewer nakked it because
> > > > apparently DT descriptions should not be OS specific.
Yeah, probably the OS part should be dropped.
> > > >
> > > > I am actually open for this to be a command-line option but I wanted to honor
> > > > what the Raspian OS folks have already done. RaspianOS already has
> > > > "brcm,enable-l1ss"
> > > > set in their DTS files.
> > >
> > > This is about the mainline kernel, I don't have any visibility into
> > > downstream kernels (where that property management was added without DT
> > > and PCI maintainers supervision).
> > >
> > > Raspian OS folks' choice is theirs but it can't and it shouldn't override
> > > the mainline review process even though I understand the position you
> > > are in.
Sure, but we shouldn't change things just to be different from
downstream. If we're only discussing the color of the shed, then no
point changing it.
> >
> > Understood, but using the command line has its warts as well; I now recall the
> > discussion Bjorn and I had regarding this option. I'm pretty sure
> > that upstreaam will not allow the following
> > possible command line kernel params:
> >
> > brcm,enable-l1ss
> > pci=brcm,entable-l1ss
> >
> > Bjorn suggested using the documented but (IMO) obscure and rarely
> > used format
> >
> > pci=[<domain>:]<bus>:<dev>.<func>[/<dev>.<func>]*pci:<vendor>:<device>[:<subvendor>:<subdevice>]
> >
> > but this is just going in the wrong direction; here's why. Using the
> > above iformat s completely dependent on the
> > PCI "linux-domaiin" property, a non-HW related DT property I might
> > add. Since "linux-domain" is already
> > a valid and well-used DT property, and the value of the above
> > command line format is dependent
> > on the value of the "linux-domain", why not be consistent and let
> > "brcm,enable-l1ss" be a Broadcom specific property?
>
> I am just asking to add a module_param to the host controller driver.
FWIW, gregkh pretty much always nacks new module parameters.
>
> Anyway - time is running out for v6.6, I need Rob's feedback, if I don't
> hear from him today I will merge the last three patches and postpone the
> discussion.
You've already got my reviewed-by. If you aren't happy with this, then
fine. I don't know enough about L1SS to comment further. Is it
normally always supported or discoverable? If so, then I'd think we'd
want it default enabled with a disable override flag. Maybe it should
be generic?
Rob
On Wed, Aug 23, 2023 at 09:30:48AM +0200, Lorenzo Pieralisi wrote:
> On Mon, Aug 21, 2023 at 12:01:50PM -0400, Jim Quinlan wrote:
> > On Mon, Aug 21, 2023 at 11:41 AM Lorenzo Pieralisi
> > <[email protected]> wrote:
> > > On Mon, Aug 21, 2023 at 11:25:11AM -0400, Jim Quinlan wrote:
> > > > On Mon, Aug 21, 2023 at 10:47 AM Lorenzo Pieralisi
> > > > <[email protected]> wrote:
> > > > > On Fri, Jun 23, 2023 at 10:40:54AM -0400, Jim Quinlan wrote:
> > > > > > This commit adds the boolean "brcm,enable-l1ss" property:
> > > > > >
> > > > > > The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs --
> > > > > > requires the driver probe() to deliberately place the HW one of three
> > > > > > CLKREQ# modes:
> > > > > >
> > > > > > (a) CLKREQ# driven by the RC unconditionally
> > > > > > (b) CLKREQ# driven by the EP for ASPM L0s, L1
> > > > > > (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS).
> > > > > >
> > > > > > The HW+driver can tell the difference between downstream devices that
> > > > > > need (a) and (b), but does not know when to configure (c). All devices
> > > > > > should work fine when the driver chooses (a) or (b), but (c) may be
> > > > > > desired to realize the extra power savings that L1SS offers. So we
> > > > > > introduce the boolean "brcm,enable-l1ss" property to inform the driver
> > > > > > that (c) is desired. Setting this property only makes sense when the
> > > > > > downstream device is L1SS-capable and the OS is configured to activate
> > > > > > this mode (e.g. policy==powersupersave).
> > > > > >
> > > > > > This property is already present in the Raspian version of Linux, but the
> > > > > > upstream driver implementation that follows adds more details and
> > > > > > discerns between (a) and (b).
> > > > > >
> > > > > > Signed-off-by: Jim Quinlan <[email protected]>
> > > > > > Reviewed-by: Rob Herring <[email protected]>
> > > > > > ---
> > > > > > Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++
> > > > > > 1 file changed, 9 insertions(+)
> > > > > >
> > > > > > diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > index 7e15aae7d69e..8b61c2179608 100644
> > > > > > --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> > > > > > @@ -64,6 +64,15 @@ properties:
> > > > > >
> > > > > > aspm-no-l0s: true
> > > > > >
> > > > > > + brcm,enable-l1ss:
> > > > > > + description: Indicates that PCIe L1SS power savings
> > > > > > + are desired, the downstream device is L1SS-capable, and the
> > > > > > + OS has been configured to enable this mode. For boards
> > > > >
> > > > > What does this mean ? I don't think DT properties are supposed
> > > > > to carry information related to how the OS is configured.
> > > >
> > > > The DT setting in question is unrelated to the statement "and the OS
> > > > has been configured to
> > > > enable this mode".
> > > >
> > > > This is merely saying that even if you enable "brcm,l1ss-enable"
> > > > that you may not get L1SS power savings w/o setting
> > > > "CONFIG_PCIEASPM_POWER_SUPERSAVE=y".
> > > > I mentioned that exact term but a reviewer nakked it because
> > > > apparently DT descriptions should not be OS specific.
> > > >
> > > > I am actually open for this to be a command-line option but I wanted to honor
> > > > what the Raspian OS folks have already done. RaspianOS already has
> > > > "brcm,enable-l1ss"
> > > > set in their DTS files.
> > >
> > > This is about the mainline kernel, I don't have any visibility into
> > > downstream kernels (where that property management was added without DT
> > > and PCI maintainers supervision).
> > >
> > > Raspian OS folks' choice is theirs but it can't and it shouldn't override
> > > the mainline review process even though I understand the position you
> > > are in.
> >
> > Understood, but using the command line has its warts as well; I now recall the
> > discussion Bjorn and I had regarding this option. I'm pretty sure
> > that upstreaam will not allow the following
> > possible command line kernel params:
> >
> > brcm,enable-l1ss
> > pci=brcm,entable-l1ss
> >
> > Bjorn suggested using the documented but (IMO) obscure and rarely
> > used format
> >
> > pci=[<domain>:]<bus>:<dev>.<func>[/<dev>.<func>]*pci:<vendor>:<device>[:<subvendor>:<subdevice>]
> >
> > but this is just going in the wrong direction; here's why. Using the
> > above iformat s completely dependent on the
> > PCI "linux-domaiin" property, a non-HW related DT property I might
> > add. Since "linux-domain" is already
> > a valid and well-used DT property, and the value of the above
> > command line format is dependent
> > on the value of the "linux-domain", why not be consistent and let
> > "brcm,enable-l1ss" be a Broadcom specific property?
>
> I am just asking to add a module_param to the host controller driver.
A module_param sounds possible to me. IIRC the bidirectional CLKREQ#
(config (c)) has been tested and there are no known problems even if
the OS doesn't enable L1SS. The only issue (again, IIRC) is that the
hardware engineer has unspecified reservations about it.
Is there any room to make (c) the default and have a module_param to
*disable* the L1SS support? I think the driver knows enough to then
select (a) or (b) by itself.
Bjorn