As requested by Rob Herring, this series split the PHY part into a separate driver.
Then, it adds support for Kirin 970 on a single patch.
With this change, the PHY-specific device tree bindings for Kirin 960 moved
to its own PHY properties.
Tested on Hikey970:
$ lspci
00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3670 (rev 01)
01:00.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:01.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:04.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:05.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:07.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
02:09.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
06:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 07)
$ ethtool enp6s0
Settings for enp6s0:
Supported ports: [ TP MII ]
Supported link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Half 1000baseT/Full
Supported pause frame use: Symmetric Receive-only
Supports auto-negotiation: Yes
Supported FEC modes: Not reported
Advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
1000baseT/Half 1000baseT/Full
Advertised pause frame use: Symmetric Receive-only
Advertised auto-negotiation: Yes
Advertised FEC modes: Not reported
Link partner advertised link modes: 10baseT/Half 10baseT/Full
100baseT/Half 100baseT/Full
Link partner advertised pause frame use: Symmetric Receive-only
Link partner advertised auto-negotiation: Yes
Link partner advertised FEC modes: Not reported
Speed: 100Mb/s
Duplex: Full
Auto-negotiation: on
master-slave cfg: preferred slave
master-slave status: slave
Port: Twisted Pair
PHYAD: 0
Transceiver: external
MDI-X: Unknown
netlink error: Operation not permitted
Link detected: yes
Partially tested on Hikey 960[1]:
$ lspci
00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3660 (rev 01)
[1] The Hikey 960 doesn't come with any internal PCIe device.
Its hardware supports just an external device via a M.2 slot that
doesn't support SATA. I ordered a NVMe device to test, but the vendor
is currently out of supply. It should take 4-5 weeks to arrive here. I'll
run an extra test on it once it arrives.
---
v4:
- dropped the DTS patch, as it depends on a PMIC-related patch series;
- minor changes at the patch description;
- HiKey and HiSilicon are now using the preferred CamelCase format.
Mauro Carvalho Chehab (8):
dt-bindings: phy: Add bindings for HiKey 960 PCIe PHY
dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY
dt-bindings: PCI: kirin: Fix compatible string
dt-bindings: PCI: kirin: Drop PHY properties
phy: HiSilicon: Add driver for Kirin 960 PCIe PHY
phy: HiSilicon: add driver for Kirin 970 PCIe PHY
PCI: kirin: Drop the PHY logic from the driver
PCI: kirin: Use regmap for APB registers
.../devicetree/bindings/pci/kirin-pcie.txt | 21 +-
.../phy/hisilicon,phy-hi3660-pcie.yaml | 82 ++
.../phy/hisilicon,phy-hi3670-pcie.yaml | 101 ++
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 29 +-
drivers/pci/controller/dwc/pcie-kirin.c | 298 ++----
drivers/phy/hisilicon/Kconfig | 20 +
drivers/phy/hisilicon/Makefile | 2 +
drivers/phy/hisilicon/phy-hi3660-pcie.c | 325 +++++++
drivers/phy/hisilicon/phy-hi3670-pcie.c | 892 ++++++++++++++++++
9 files changed, 1500 insertions(+), 270 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml
create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
create mode 100644 drivers/phy/hisilicon/phy-hi3660-pcie.c
create mode 100644 drivers/phy/hisilicon/phy-hi3670-pcie.c
--
2.31.1
There are several properties there that belong to the PHY
interface. Drop them, as a new binding file will describe
the PHY properties for Kirin 960.
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
---
.../devicetree/bindings/pci/kirin-pcie.txt | 16 +++-------------
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/kirin-pcie.txt b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
index 71cac2b74002..a93a8cfa1afb 100644
--- a/Documentation/devicetree/bindings/pci/kirin-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/kirin-pcie.txt
@@ -10,13 +10,11 @@ Additional properties are described here:
Required properties
- compatible:
"hisilicon,kirin960-pcie"
-- reg: Should contain rc_dbi, apb, phy, config registers location and length.
+- reg: Should contain rc_dbi, apb, config registers location and length.
- reg-names: Must include the following entries:
"dbi": controller configuration registers;
"apb": apb Ctrl register defined by Kirin;
- "phy": apb PHY register defined by Kirin;
"config": PCIe configuration space registers.
-- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
Optional properties:
@@ -25,8 +23,8 @@ Example based on kirin960:
pcie@f4000000 {
compatible = "hisilicon,kirin960-pcie";
reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
- <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
- reg-names = "dbi","apb","phy", "config";
+ <0x0 0xF4000000 0 0x2000>;
+ reg-names = "dbi","apb", "config";
bus-range = <0x0 0x1>;
#address-cells = <3>;
#size-cells = <2>;
@@ -39,12 +37,4 @@ Example based on kirin960:
<0x0 0 0 2 &gic 0 0 0 283 4>,
<0x0 0 0 3 &gic 0 0 0 284 4>,
<0x0 0 0 4 &gic 0 0 0 285 4>;
- clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
- <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
- <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
- <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
- <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
- clock-names = "pcie_phy_ref", "pcie_aux",
- "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
- reset-gpios = <&gpio11 1 0 >;
};
--
2.31.1
Document the bindings for HiKey 960 (hi3660) PCIe PHY
interface, supported via the pcie-kirin driver.
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
---
.../phy/hisilicon,phy-hi3660-pcie.yaml | 82 +++++++++++++++++++
1 file changed, 82 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml
diff --git a/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml
new file mode 100644
index 000000000000..81c93e76cef4
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/hisilicon,phy-hi3660-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: HiSilicon Kirin960 PCIe PHY
+
+maintainers:
+ - Mauro Carvalho Chehab <[email protected]>
+
+description: |+
+ Bindings for PCIe PHY on HiSilicon Kirin 960.
+
+properties:
+ compatible:
+ const: hisilicon,hi960-pcie-phy
+
+ "#phy-cells":
+ const: 0
+
+ reg:
+ maxItems: 1
+ description: PHY Control registers
+
+ reg-names:
+ const: phy
+
+ clocks:
+ items:
+ - description: PCIe PHY clock
+ - description: PCIe AUX clock
+ - description: PCIe APB PHY clock
+ - description: PCIe APB SYS clock
+ - description: PCIe ACLK clock
+
+ clock-names:
+ items:
+ - const: pcie_phy_ref
+ - const: pcie_aux
+ - const: pcie_apb_phy
+ - const: pcie_apb_sys
+ - const: pcie_aclk
+
+ reset-gpios:
+ description: PCI PERST reset GPIO
+
+required:
+ - "#phy-cells"
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - reset-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/hi3660-clock.h>
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pcie_phy: pcie-phy@f3f2000 {
+ compatible = "hisilicon,hi960-pcie-phy";
+ reg = <0x0 0xf3f20000 0x0 0x40000>;
+ reg-names = "phy";
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys",
+ "pcie_aclk";
+ reset-gpios = <&gpio11 1 0 >;
+ #phy-cells = <0>;
+ };
+ };
+...
--
2.31.1