The USB multiport controller found in SC8180X is used to driver the
camera in the Lenovo Flex 5G, and a couple of additional USB ports on
the Primus AUX board.
Signed-off-by: Bjorn Andersson <[email protected]>
---
Bjorn Andersson (10):
dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add sc8180x USB3 compatible
phy: qcom-qmp-usb: Add sc8180x USB UNIPHY
dt-bindings: clock: qcom: Add missing USB MP resets
clk: qcom: gcc-sc8180x: Add missing USB MP resets
dt-bindings: usb: qcom,dwc3: Add SC8180X compatibles
arm64: dts: qcom: sc8180x-pmics: Add second PMC8180 GPIO
arm64: dts: qcom: sc8180x: Align USB nodes with binding
arm64: dts: qcom: sc8180x: Add USB MP controller and phys
arm64: dts: qcom: sc8180x-primus: Enable the two MP USB ports
arm64: dts: qcom: sc8180x-lenovo-flex-5g: Enable USB multiport controller
.../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 3 +
.../devicetree/bindings/usb/qcom,dwc3.yaml | 29 ++++
.../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 32 ++++
arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 16 +-
arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 60 +++++++
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 175 +++++++++++++++++++--
drivers/clk/qcom/gcc-sc8180x.c | 4 +
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3 +
include/dt-bindings/clock/qcom,gcc-sc8180x.h | 4 +
9 files changed, 312 insertions(+), 14 deletions(-)
---
base-commit: 3689b0ef08b70e4e03b82ebd37730a03a672853a
change-id: 20240524-sc8180x-usb-mp-4eb278df7ef1
Best regards,
--
Bjorn Andersson <[email protected]>
From: Bjorn Andersson <[email protected]>
The SC8180X has two USB3 UNIPHY QMP blocks, add a compatible for these.
Signed-off-by: Bjorn Andersson <[email protected]>
---
.../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
index 325585bc881b..5755245ecfd6 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml
@@ -22,6 +22,7 @@ properties:
- qcom,msm8996-qmp-usb3-phy
- com,qdu1000-qmp-usb3-uni-phy
- qcom,sa8775p-qmp-usb3-uni-phy
+ - qcom,sc8180x-qmp-usb3-uni-phy
- qcom,sc8280xp-qmp-usb3-uni-phy
- qcom,sdm845-qmp-usb3-uni-phy
- qcom,sdx55-qmp-usb3-uni-phy
@@ -112,6 +113,7 @@ allOf:
enum:
- qcom,qdu1000-qmp-usb3-uni-phy
- qcom,sa8775p-qmp-usb3-uni-phy
+ - qcom,sc8180x-qmp-usb3-uni-phy
- qcom,sc8280xp-qmp-usb3-uni-phy
- qcom,sm8150-qmp-usb3-uni-phy
- qcom,sm8250-qmp-usb3-uni-phy
@@ -152,6 +154,7 @@ allOf:
contains:
enum:
- qcom,sa8775p-qmp-usb3-uni-phy
+ - qcom,sc8180x-qmp-usb3-uni-phy
- qcom,sc8280xp-qmp-usb3-uni-phy
- qcom,x1e80100-qmp-usb3-uni-phy
then:
--
2.43.0
From: Bjorn Andersson <[email protected]>
The SC8180X platform has two UNIPHY blocks, add support for these in the
QMP driver.
Signed-off-by: Bjorn Andersson <[email protected]>
---
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index c174463c58a3..9b0eb87b1680 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -2252,6 +2252,9 @@ static const struct of_device_id qmp_usb_of_match_table[] = {
}, {
.compatible = "qcom,sa8775p-qmp-usb3-uni-phy",
.data = &sa8775p_usb3_uniphy_cfg,
+ }, {
+ .compatible = "qcom,sc8180x-qmp-usb3-uni-phy",
+ .data = &sm8150_usb3_uniphy_cfg,
}, {
.compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
.data = &sc8280xp_usb3_uniphy_cfg,
--
2.43.0
From: Bjorn Andersson <[email protected]>
The USB multiport controller needs a few additional resets, add these to
the driver.
Signed-off-by: Bjorn Andersson <[email protected]>
---
drivers/clk/qcom/gcc-sc8180x.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c
index 5261bfc92b3d..f77578e98ca7 100644
--- a/drivers/clk/qcom/gcc-sc8180x.c
+++ b/drivers/clk/qcom/gcc-sc8180x.c
@@ -4546,6 +4546,10 @@ static const struct qcom_reset_map gcc_sc8180x_resets[] = {
[GCC_USB3_PHY_SEC_BCR] = { 0x50018 },
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x5001c },
[GCC_USB3_DP_PHY_SEC_BCR] = { 0x50020 },
+ [GCC_USB3_UNIPHY_MP0_BCR] = { 0x50024 },
+ [GCC_USB3_UNIPHY_MP1_BCR] = { 0x50028 },
+ [GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x5002c },
+ [GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x50030 },
[GCC_SDCC2_BCR] = { 0x14000 },
[GCC_SDCC4_BCR] = { 0x16000 },
[GCC_TSIF_BCR] = { 0x36000 },
--
2.43.0
From: Bjorn Andersson <[email protected]>
The USB multiport controller needs a few missing resets, describe them
in the binding.
Signed-off-by: Bjorn Andersson <[email protected]>
---
include/dt-bindings/clock/qcom,gcc-sc8180x.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/dt-bindings/clock/qcom,gcc-sc8180x.h b/include/dt-bindings/clock/qcom,gcc-sc8180x.h
index 90c6e021a035..487b12c19db5 100644
--- a/include/dt-bindings/clock/qcom,gcc-sc8180x.h
+++ b/include/dt-bindings/clock/qcom,gcc-sc8180x.h
@@ -294,6 +294,10 @@
#define GCC_VIDEO_AXI0_CLK_BCR 42
#define GCC_VIDEO_AXI1_CLK_BCR 43
#define GCC_USB3_DP_PHY_SEC_BCR 44
+#define GCC_USB3_UNIPHY_MP0_BCR 45
+#define GCC_USB3_UNIPHY_MP1_BCR 46
+#define GCC_USB3UNIPHY_PHY_MP0_BCR 47
+#define GCC_USB3UNIPHY_PHY_MP1_BCR 48
/* GCC GDSCRs */
#define EMAC_GDSC 0
--
2.43.0
From: Bjorn Andersson <[email protected]>
The SC8180X comes with two PMC8180 PMICs, with the GPIO block being used
to control VBUS supply of the second USB multiport port.
Rename the GPIO controller in the first PMC8180 to match the schematics
and define this second controller.
Signed-off-by: Bjorn Andersson <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi
index ddc84282f142..95656b5ed481 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi
@@ -141,11 +141,11 @@ rtc@6000 {
interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
};
- pmc8180_gpios: gpio@c000 {
+ pmc8180_1_gpios: gpio@c000 {
compatible = "qcom,pmc8180-gpio", "qcom,spmi-gpio";
reg = <0xc000>;
gpio-controller;
- gpio-ranges = <&pmc8180_gpios 0 0 10>;
+ gpio-ranges = <&pmc8180_1_gpios 0 0 10>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
@@ -200,11 +200,21 @@ pmic@6 {
#size-cells = <0>;
};
- pmic@8 {
+ pmc8180_2: pmic@8 {
compatible = "qcom,pm8150", "qcom,spmi-pmic";
reg = <0x8 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
+
+ pmc8180_2_gpios: gpio@c000 {
+ compatible = "qcom,pmc8180-gpio", "qcom,spmi-gpio";
+ reg = <0xc000>;
+ gpio-controller;
+ gpio-ranges = <&pmc8180_2_gpios 0 0 10>;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
pmic@a {
--
2.43.0
From: Bjorn Andersson <[email protected]>
The SC8180X platform comes with a multiport DWC3 controller with two
ports, each connected to a pair of HighSpeed and QMP SuperSpeed PHYs.
Describe these blocks.
Signed-off-by: Bjorn Andersson <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 146 ++++++++++++++++++++++++++++++++++
1 file changed, 146 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 9ef3fa40e1d8..0950dc7adb20 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -2511,6 +2511,34 @@ usb_sec_hsphy: phy@88e3000 {
status = "disabled";
};
+ usb_mp0_hsphy: phy@88e4000 {
+ compatible = "qcom,sc8180x-usb-hs-phy",
+ "qcom,usb-snps-hs-7nm-phy";
+ reg = <0 0x088e4000 0 0x400>;
+ #phy-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_MP0_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_mp1_hsphy: phy@88e5000 {
+ compatible = "qcom,sc8180x-usb-hs-phy",
+ "qcom,usb-snps-hs-7nm-phy";
+ reg = <0 0x088e5000 0 0x400>;
+ #phy-cells = <0>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_MP1_BCR>;
+
+ status = "disabled";
+ };
+
usb_prim_qmpphy: phy@88e9000 {
compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
reg = <0 0x088e9000 0 0x18c>,
@@ -2577,6 +2605,54 @@ usb_prim_dpphy: dp-phy@88ea200 {
};
};
+ usb_mp0_qmpphy: phy@88eb000 {
+ compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
+ reg = <0 0x088eb000 0 0x1000>;
+
+ clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
+ clock-names = "aux", "ref", "com_aux", "pipe";
+
+ resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
+ <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
+ reset-names = "phy", "phy_phy";
+
+ power-domains = <&gcc USB30_MP_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "usb2_phy0_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_mp1_qmpphy: phy@88ec000 {
+ compatible = "qcom,sc8180x-qmp-usb3-uni-phy";
+ reg = <0 0x088ec000 0 0x1000>;
+
+ clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
+ clock-names = "aux", "ref", "com_aux", "pipe";
+
+ resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
+ <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
+ reset-names = "phy", "phy_phy";
+
+ power-domains = <&gcc USB30_MP_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "usb2_phy1_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
usb_sec_qmpphy: phy@88ee000 {
compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
reg = <0 0x088ee000 0 0x18c>,
@@ -2662,6 +2738,76 @@ gem_noc: interconnect@9680000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ usb_mp: usb@a4f8800 {
+ compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3";
+ reg = <0 0x0a4f8800 0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
+ <&gcc GCC_USB30_MP_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
+ <&gcc GCC_USB30_MP_SLEEP_CLK>,
+ <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB3_SEC_CLKREF_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "xo";
+
+ interconnects = <&aggre1_noc MASTER_USB3_2 0 &mc_virt SLAVE_EBI_CH0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_2 0>;
+ interconnect-names = "usb-ddr", "apps-usb";
+
+ assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_MP_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 59 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 46 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 71 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 68 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event_1", "pwr_event_2",
+ "hs_phy_1", "hs_phy_2",
+ "dp_hs_phy_1", "dm_hs_phy_1",
+ "dp_hs_phy_2", "dm_hs_phy_2",
+ "ss_phy_1", "ss_phy_2";
+
+ power-domains = <&gcc USB30_MP_GDSC>;
+
+ resets = <&gcc GCC_USB30_MP_BCR>;
+
+ status = "disabled";
+
+ usb_mp_dwc3: usb@a400000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a400000 0 0xcd00>;
+ interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x60 0>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ phys = <&usb_mp0_hsphy>,
+ <&usb_mp0_qmpphy>,
+ <&usb_mp1_hsphy>,
+ <&usb_mp1_qmpphy>;
+ phy-names = "usb2-0",
+ "usb3-0",
+ "usb2-1",
+ "usb3-1";
+ dr_mode = "host";
+ };
+ };
+
usb_prim: usb@a6f8800 {
compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
--
2.43.0
From: Bjorn Andersson <[email protected]>
The SC8180X Primus comes with an AUX card with two USB ports, fed by the
two multiport ports.
Enable the involved nodes and define two always-on regulators to enable
VBUS for these ports.
Signed-off-by: Bjorn Andersson <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 60 +++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
index bfee60c93ccc..f7632f13ac43 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-primus.dts
@@ -223,6 +223,32 @@ vreg_s4a_1p8: pm8150-s4 {
vin-supply = <&vph_pwr>;
};
+ vreg_usb2_host_en: regulator-usb2-host-en {
+ compatible = "regulator-fixed";
+ regulator-name = "usb2_host_en";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&pmc8180_1_gpios 9 0>;
+ enable-active-high;
+
+ regulator-always-on;
+ };
+
+ vreg_usb3_host_en: regulator-usb3-host-en {
+ compatible = "regulator-fixed";
+ regulator-name = "usb3_host_en";
+
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ gpio = <&pmc8180_2_gpios 9 0>;
+ enable-active-high;
+
+ regulator-always-on;
+ };
+
usbprim-sbu-mux {
compatible = "pericom,pi3usb102", "gpio-sbu-mux";
@@ -623,6 +649,40 @@ &ufs_mem_phy {
status = "okay";
};
+&usb_mp {
+ status = "okay";
+};
+
+&usb_mp0_hsphy {
+ vdda-pll-supply = <&vreg_l5e_0p88>;
+ vdda18-supply = <&vreg_l12a_1p8>;
+ vdda33-supply = <&vreg_l16e_3p0>;
+
+ status = "okay";
+};
+
+&usb_mp0_qmpphy {
+ vdda-phy-supply = <&vreg_l3c_1p2>;
+ vdda-pll-supply = <&vreg_l5e_0p88>;
+
+ status = "okay";
+};
+
+&usb_mp1_hsphy {
+ vdda-pll-supply = <&vreg_l5e_0p88>;
+ vdda18-supply = <&vreg_l12a_1p8>;
+ vdda33-supply = <&vreg_l16e_3p0>;
+
+ status = "okay";
+};
+
+&usb_mp1_qmpphy {
+ vdda-phy-supply = <&vreg_l3c_1p2>;
+ vdda-pll-supply = <&vreg_l5e_0p88>;
+
+ status = "okay";
+};
+
&usb_prim_hsphy {
vdda-pll-supply = <&vreg_l5e_0p88>;
vdda18-supply = <&vreg_l12a_1p8>;
--
2.43.0
From: Bjorn Andersson <[email protected]>
The SC8180X platform has two single port DWC3 instances and a two-port
DWC3 instance. Add compatibles for these to the binding.
Signed-off-by: Bjorn Andersson <[email protected]>
---
.../devicetree/bindings/usb/qcom,dwc3.yaml | 29 ++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
index cf633d488c3f..efde47a5b145 100644
--- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
@@ -30,6 +30,8 @@ properties:
- qcom,sa8775p-dwc3
- qcom,sc7180-dwc3
- qcom,sc7280-dwc3
+ - qcom,sc8180x-dwc3
+ - qcom,sc8180x-dwc3-mp
- qcom,sc8280xp-dwc3
- qcom,sc8280xp-dwc3-mp
- qcom,sdm660-dwc3
@@ -334,6 +336,8 @@ allOf:
contains:
enum:
- qcom,qcm2290-dwc3
+ - qcom,sc8180x-dwc3
+ - qcom,sc8180x-dwc3-mp
- qcom,sm6115-dwc3
- qcom,sm6125-dwc3
- qcom,sm8150-dwc3
@@ -448,6 +452,7 @@ allOf:
- qcom,sa8775p-dwc3
- qcom,sc7180-dwc3
- qcom,sc7280-dwc3
+ - qcom,sc8180x-dwc3
- qcom,sc8280xp-dwc3
- qcom,sdm670-dwc3
- qcom,sdm845-dwc3
@@ -475,6 +480,30 @@ allOf:
- const: dm_hs_phy_irq
- const: ss_phy_irq
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc8180x-dwc3-mp
+ then:
+ properties:
+ interrupts:
+ minItems: 10
+ maxItems: 10
+ interrupt-names:
+ items:
+ - const: pwr_event_1
+ - const: pwr_event_2
+ - const: hs_phy_1
+ - const: hs_phy_2
+ - const: dp_hs_phy_1
+ - const: dm_hs_phy_1
+ - const: dp_hs_phy_2
+ - const: dm_hs_phy_2
+ - const: ss_phy_1
+ - const: ss_phy_2
+
- if:
properties:
compatible:
--
2.43.0
From: Bjorn Andersson <[email protected]>
The Lenovo Flex 5G has a camera attached to the multiport USB
controller, enable the controller and the four phys to enable this.
Signed-off-by: Bjorn Andersson <[email protected]>
---
.../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 32 ++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
index 6af99116c715..daa3065bcfe5 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
+++ b/arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts
@@ -557,6 +557,38 @@ &ufs_mem_phy {
status = "okay";
};
+&usb_mp {
+ status = "okay";
+};
+
+&usb_mp0_hsphy {
+ status = "okay";
+ vdda-pll-supply = <&vreg_l5e_0p88>;
+ vdda18-supply = <&vreg_l12a_1p8>;
+ vdda33-supply = <&vreg_l16e_3p0>;
+};
+
+&usb_mp0_qmpphy {
+ vdda-phy-supply = <&vreg_l3c_1p2>;
+ vdda-pll-supply = <&vreg_l5e_0p88>;
+
+ status = "okay";
+};
+
+&usb_mp1_hsphy {
+ status = "okay";
+ vdda-pll-supply = <&vreg_l5e_0p88>;
+ vdda18-supply = <&vreg_l12a_1p8>;
+ vdda33-supply = <&vreg_l16e_3p0>;
+};
+
+&usb_mp1_qmpphy {
+ vdda-phy-supply = <&vreg_l3c_1p2>;
+ vdda-pll-supply = <&vreg_l5e_0p88>;
+
+ status = "okay";
+};
+
&usb_prim_hsphy {
vdda-pll-supply = <&vreg_l5e_0p88>;
vdda18-supply = <&vreg_l12a_1p8>;
--
2.43.0
From: Bjorn Andersson <[email protected]>
Add the pwr_event interrupt and rearrange the order of the other
interrupts to match the binding.
Signed-off-by: Bjorn Andersson <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8180x.dtsi | 29 ++++++++++++++++++-----------
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
index 067712310560..9ef3fa40e1d8 100644
--- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
@@ -2665,14 +2665,16 @@ gem_noc: interconnect@9680000 {
usb_prim: usb@a6f8800 {
compatible = "qcom,sc8180x-dwc3", "qcom,dwc3";
reg = <0 0x0a6f8800 0 0x400>;
- interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 9 IRQ_TYPE_EDGE_BOTH>,
<&pdc 8 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 9 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq",
- "ss_phy_irq",
+ <&pdc 6 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
"dm_hs_phy_irq",
- "dp_hs_phy_irq";
+ "ss_phy_irq";
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
<&gcc GCC_USB30_PRIM_MASTER_CLK>,
@@ -2739,12 +2741,17 @@ usb_sec: usb@a8f8800 {
"xo";
resets = <&gcc GCC_USB30_SEC_BCR>;
power-domains = <&gcc USB30_SEC_GDSC>;
- interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
- <&pdc 40 IRQ_TYPE_LEVEL_HIGH>,
+
+ interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
<&pdc 10 IRQ_TYPE_EDGE_BOTH>,
- <&pdc 11 IRQ_TYPE_EDGE_BOTH>;
- interrupt-names = "hs_phy_irq", "ss_phy_irq",
- "dm_hs_phy_irq", "dp_hs_phy_irq";
+ <&pdc 40 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
<&gcc GCC_USB30_SEC_MASTER_CLK>;
--
2.43.0
On Sat, May 25, 2024 at 11:03:55AM -0700, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> The SC8180X platform has two UNIPHY blocks, add support for these in the
> QMP driver.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3 +++
> 1 file changed, 3 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On Sat, May 25, 2024 at 11:03:59AM -0700, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> The SC8180X comes with two PMC8180 PMICs, with the GPIO block being used
> to control VBUS supply of the second USB multiport port.
>
> Rename the GPIO controller in the first PMC8180 to match the schematics
> and define this second controller.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On Sat, May 25, 2024 at 11:04:01AM -0700, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> The SC8180X platform comes with a multiport DWC3 controller with two
> ports, each connected to a pair of HighSpeed and QMP SuperSpeed PHYs.
>
> Describe these blocks.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc8180x.dtsi | 146 ++++++++++++++++++++++++++++++++++
> 1 file changed, 146 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On Sat, May 25, 2024 at 11:04:02AM -0700, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> The SC8180X Primus comes with an AUX card with two USB ports, fed by the
> two multiport ports.
>
> Enable the involved nodes and define two always-on regulators to enable
> VBUS for these ports.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 60 +++++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On Sat, May 25, 2024 at 11:04:03AM -0700, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> The Lenovo Flex 5G has a camera attached to the multiport USB
> controller, enable the controller and the four phys to enable this.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> .../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 32 ++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
Reviewed-by: Dmitry Baryshkov <[email protected]>
>
--
With best wishes
Dmitry
On 25/05/2024 20:03, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> The SC8180X has two USB3 UNIPHY QMP blocks, add a compatible for these.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> .../devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 25/05/2024 20:03, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> The USB multiport controller needs a few missing resets, describe them
> in the binding.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 25/05/2024 20:03, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> The SC8180X platform has two single port DWC3 instances and a two-port
> DWC3 instance. Add compatibles for these to the binding.
>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 5/25/24 20:03, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> The USB multiport controller needs a few additional resets, add these to
> the driver.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
The numbers look good
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On 5/25/24 20:04, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> Add the pwr_event interrupt and rearrange the order of the other
> interrupts to match the binding.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
The new numbers look correct as well
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On 5/25/24 20:04, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> The SC8180X platform comes with a multiport DWC3 controller with two
> ports, each connected to a pair of HighSpeed and QMP SuperSpeed PHYs.
>
> Describe these blocks.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc8180x.dtsi | 146 ++++++++++++++++++++++++++++++++++
> 1 file changed, 146 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8180x.dtsi b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> index 9ef3fa40e1d8..0950dc7adb20 100644
> --- a/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8180x.dtsi
> @@ -2511,6 +2511,34 @@ usb_sec_hsphy: phy@88e3000 {
> status = "disabled";
> };
>
> + usb_mp0_hsphy: phy@88e4000 {
Even though the register names are MPn, I think this is a bit confusing..
There's only one MP controller, so perhaps usb_mp_hsphy0?
[...]
> + clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
> + <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> + <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
PIPE_1_CLK
> + clock-names = "aux", "ref", "com_aux", "pipe";
This could be a vertical list
> +
> + resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
> + <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
> + reset-names = "phy", "phy_phy";
> +
> + power-domains = <&gcc USB30_MP_GDSC>;
> +
> + #clock-cells = <0>;
> + clock-output-names = "usb2_phy1_pipe_clk";
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> usb_sec_qmpphy: phy@88ee000 {
> compatible = "qcom,sc8180x-qmp-usb3-dp-phy";
> reg = <0 0x088ee000 0 0x18c>,
> @@ -2662,6 +2738,76 @@ gem_noc: interconnect@9680000 {
> qcom,bcm-voters = <&apps_bcm_voter>;
> };
>
> + usb_mp: usb@a4f8800 {
> + compatible = "qcom,sc8180x-dwc3-mp", "qcom,dwc3";
> + reg = <0 0x0a4f8800 0 0x400>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + dma-ranges;
> +
> + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
> + <&gcc GCC_USB30_MP_MASTER_CLK>,
> + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
> + <&gcc GCC_USB30_MP_SLEEP_CLK>,
> + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB3_SEC_CLKREF_CLK>;
This is used by the secondary DWC3 (non-MP). Are you sure?
Actually, are we sure that these clocks are really supplying the DWC3s?
> + clock-names = "cfg_noc",
> + "core",
> + "iface",
> + "sleep",
> + "mock_utmi",
> + "xo";
> +
> + interconnects = <&aggre1_noc MASTER_USB3_2 0 &mc_virt SLAVE_EBI_CH0 0>,
> + <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_2 0>;
> + interconnect-names = "usb-ddr", "apps-usb";
> +
> + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
> + <&gcc GCC_USB30_MP_MASTER_CLK>;
> + assigned-clock-rates = <19200000>, <200000000>;
> +
> + interrupts-extended = <&intc GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH>,
> + <&intc GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 59 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 46 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 71 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 68 IRQ_TYPE_EDGE_BOTH>,
> + <&pdc 7 IRQ_TYPE_LEVEL_HIGH>,
> + <&pdc 30 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "pwr_event_1", "pwr_event_2",
> + "hs_phy_1", "hs_phy_2",
> + "dp_hs_phy_1", "dm_hs_phy_1",
> + "dp_hs_phy_2", "dm_hs_phy_2",
> + "ss_phy_1", "ss_phy_2";
> +
> + power-domains = <&gcc USB30_MP_GDSC>;
> +
> + resets = <&gcc GCC_USB30_MP_BCR>;
> +
> + status = "disabled";
> +
> + usb_mp_dwc3: usb@a400000 {
> + compatible = "snps,dwc3";
> + reg = <0 0x0a400000 0 0xcd00>;
> + interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&apps_smmu 0x60 0>;
> + snps,dis_u2_susphy_quirk;
> + snps,dis_enblslpm_quirk;
sa8195-usb.dtsi lists a bunch more fluff:
snps,has-lpm-erratum;
snps,hird-threshold = /bits/ 8 <0x0>;
snps,is-utmi-l1-suspend;
snps,ssp-u3-u0-quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis_u3_susphy_quirk;
snps,force-gen1;
maximum-speed = "super-speed";
the irq numbers look good
Konrad
On 5/25/24 20:04, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> The SC8180X Primus comes with an AUX card with two USB ports, fed by the
> two multiport ports.
>
> Enable the involved nodes and define two always-on regulators to enable
> VBUS for these ports.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
[...]
> + gpio = <&pmc8180_1_gpios 9 0>;
GPIO_ACTIVE_HIGH?
> + enable-active-high;
> +
> + regulator-always-on;
> + };
> +
> + vreg_usb3_host_en: regulator-usb3-host-en {
> + compatible = "regulator-fixed";
> + regulator-name = "usb3_host_en";
> +
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> +
> + gpio = <&pmc8180_2_gpios 9 0>;
GPIO_ACTIVE_HIGH
with that:
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
On 5/25/24 20:04, Bjorn Andersson wrote:
> From: Bjorn Andersson <[email protected]>
>
> The Lenovo Flex 5G has a camera attached to the multiport USB
> controller, enable the controller and the four phys to enable this.
Any chance you could leave a comment above each pair of PHYs that would
say e.g.
/* Left rear port */
&usb_mp0_hsphy {
..
?
[...]
> +&usb_mp0_hsphy {
> + status = "okay";
> + vdda-pll-supply = <&vreg_l5e_0p88>;
> + vdda18-supply = <&vreg_l12a_1p8>;
> + vdda33-supply = <&vreg_l16e_3p0>;
status last
> +};
> +
> +&usb_mp0_qmpphy {
> + vdda-phy-supply = <&vreg_l3c_1p2>;
> + vdda-pll-supply = <&vreg_l5e_0p88>;
> +
> + status = "okay";
> +};
> +
> +&usb_mp1_hsphy {
> + status = "okay";
> + vdda-pll-supply = <&vreg_l5e_0p88>;
> + vdda18-supply = <&vreg_l12a_1p8>;
> + vdda33-supply = <&vreg_l16e_3p0>;
ditto
Konrad
On Sat, 25 May 2024 11:03:53 -0700, Bjorn Andersson wrote:
> The USB multiport controller found in SC8180X is used to driver the
> camera in the Lenovo Flex 5G, and a couple of additional USB ports on
> the Primus AUX board.
>
> Signed-off-by: Bjorn Andersson <[email protected]>
> ---
> Bjorn Andersson (10):
> dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add sc8180x USB3 compatible
> phy: qcom-qmp-usb: Add sc8180x USB UNIPHY
> dt-bindings: clock: qcom: Add missing USB MP resets
> clk: qcom: gcc-sc8180x: Add missing USB MP resets
> dt-bindings: usb: qcom,dwc3: Add SC8180X compatibles
> arm64: dts: qcom: sc8180x-pmics: Add second PMC8180 GPIO
> arm64: dts: qcom: sc8180x: Align USB nodes with binding
> arm64: dts: qcom: sc8180x: Add USB MP controller and phys
> arm64: dts: qcom: sc8180x-primus: Enable the two MP USB ports
> arm64: dts: qcom: sc8180x-lenovo-flex-5g: Enable USB multiport controller
>
> .../phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml | 3 +
> .../devicetree/bindings/usb/qcom,dwc3.yaml | 29 ++++
> .../arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dts | 32 ++++
> arch/arm64/boot/dts/qcom/sc8180x-pmics.dtsi | 16 +-
> arch/arm64/boot/dts/qcom/sc8180x-primus.dts | 60 +++++++
> arch/arm64/boot/dts/qcom/sc8180x.dtsi | 175 +++++++++++++++++++--
> drivers/clk/qcom/gcc-sc8180x.c | 4 +
> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3 +
> include/dt-bindings/clock/qcom,gcc-sc8180x.h | 4 +
> 9 files changed, 312 insertions(+), 14 deletions(-)
> ---
> base-commit: 3689b0ef08b70e4e03b82ebd37730a03a672853a
> change-id: 20240524-sc8180x-usb-mp-4eb278df7ef1
>
> Best regards,
> --
> Bjorn Andersson <[email protected]>
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
New warnings running 'make CHECK_DTBS=y qcom/sc8180x-lenovo-flex-5g.dtb qcom/sc8180x-primus.dtb' for [email protected]:
arch/arm64/boot/dts/qcom/sc8180x-lenovo-flex-5g.dtb: clock-controller@af00000: clocks: [[41, 0], [42], [120, 0], [120, 1], [124, 0], [124, 1], [127, 0], [127, 1]] is too long
from schema $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
arch/arm64/boot/dts/qcom/sc8180x-primus.dtb: clock-controller@af00000: clocks: [[41, 0], [42], [122, 0], [122, 1], [126, 0], [126, 1], [129, 0], [129, 1]] is too long
from schema $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
On Sat, 25 May 2024 11:03:53 -0700, Bjorn Andersson wrote:
> The USB multiport controller found in SC8180X is used to driver the
> camera in the Lenovo Flex 5G, and a couple of additional USB ports on
> the Primus AUX board.
>
>
Applied, thanks!
[01/10] dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add sc8180x USB3 compatible
commit: 4dc7e51a9e40f07dc0da7eea05577633984ea9f2
[02/10] phy: qcom-qmp-usb: Add sc8180x USB UNIPHY
commit: b279a835192834565db5025205394e3ef943fbd2
Best regards,
--
Vinod Koul <[email protected]>