Certain TEMP_ALARM GEN2 PMIC peripherals need over-temperature
stage 2 automatic PMIC partial shutdown to be enabled in order to
avoid repeated faults in the event of reaching over-temperature
stage 3. Modify the stage 2 shutdown control logic to ensure that
stage 2 shutdown is enabled on all affected PMICs. Read the
digital major and minor revision registers to identify these
PMICs.
Signed-off-by: David Collins <[email protected]>
---
drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 31 +++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
index 770f82cc9bca..91556118a7b8 100644
--- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
+++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c
@@ -18,6 +18,7 @@
#include "../thermal_core.h"
#include "../thermal_hwmon.h"
+#define QPNP_TM_REG_DIG_MINOR 0x00
#define QPNP_TM_REG_DIG_MAJOR 0x01
#define QPNP_TM_REG_TYPE 0x04
#define QPNP_TM_REG_SUBTYPE 0x05
@@ -73,6 +74,7 @@ struct qpnp_tm_chip {
struct device *dev;
struct thermal_zone_device *tz_dev;
unsigned int subtype;
+ unsigned int dig_revision;
long temp;
unsigned int thresh;
unsigned int stage;
@@ -224,6 +226,7 @@ static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip,
long stage2_threshold_min = (*chip->temp_map)[THRESH_MIN][1];
long stage2_threshold_max = (*chip->temp_map)[THRESH_MAX][1];
bool disable_s2_shutdown = false;
+ bool require_s2_shutdown = false;
u8 reg;
WARN_ON(!mutex_is_locked(&chip->lock));
@@ -255,9 +258,25 @@ static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip,
"No ADC is configured and critical temperature is above the maximum stage 2 threshold of 140 C! Configuring stage 2 shutdown at 140 C.\n");
}
+ if (chip->subtype == QPNP_TM_SUBTYPE_GEN2) {
+ /*
+ * Check if stage 2 automatic partial shutdown must remain
+ * enabled to avoid potential repeated faults upon reaching
+ * over-temperature stage 3.
+ */
+ switch (chip->dig_revision) {
+ case 0x0001:
+ case 0x0002:
+ case 0x0100:
+ case 0x0101:
+ require_s2_shutdown = true;
+ break;
+ }
+ }
+
skip:
reg |= chip->thresh;
- if (disable_s2_shutdown)
+ if (disable_s2_shutdown && !require_s2_shutdown)
reg |= SHUTDOWN_CTRL1_OVERRIDE_S2;
return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg);
@@ -372,7 +391,7 @@ static int qpnp_tm_probe(struct platform_device *pdev)
{
struct qpnp_tm_chip *chip;
struct device_node *node;
- u8 type, subtype, dig_major;
+ u8 type, subtype, dig_major, dig_minor;
u32 res;
int ret, irq;
@@ -428,6 +447,14 @@ static int qpnp_tm_probe(struct platform_device *pdev)
return ret;
}
+ ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MINOR, &dig_minor);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "could not read dig_minor\n");
+ return ret;
+ }
+
+ chip->dig_revision = (dig_major << 8) | dig_minor;
+
if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1
&& subtype != QPNP_TM_SUBTYPE_GEN2)) {
dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n",
--
2.25.1