Resending as patch 10/11 and 11/11 were not sent.
Takahiro, since you already have to test all these flashes, I took the
liberty and added some other changes that would be good to have. The
first one lets SFDP determine the flash size and sector size. Michael is
in the process of changing how INFO is handled, we'd like to get rid of
these params when SFDP tables are defined. The other 2 patches
consolidates a bit the spansion code with the idea that we should use
the same code paths for both single (SCP) and multi chip package (MCP)
flashes were possible. We avoid this way code duplication and have
better test coverage on the code. On your patches I modified how/where
"if (!params->n_dice || !params->vreg_offset)" is handled. Please review
all and if you agree with the changes, retest on all flashes. Everything
looks good to me, if the tests pass, I'll queue all.
Cheers,
ta
Takahiro Kuwano (8):
mtd: spi-nor: spansion: use CLPEF as an alternative to CLSR
mtd: spi-nor: spansion: preserve CFR2V[7] when writing MEMLAT
mtd: spi-nor: spansion: prepare octal dtr methods for multi chip
support
mtd: spi-nor: spansion: switch set_octal_dtr method to use vreg_offset
mtd: spi-nor: spansion: switch h28hx's ready() to use vreg_offset
mtd: spi-nor: spansion: add MCP support in set_octal_dtr()
mtd: spi-nor: spansion: add octal DTR support in RD_ANY_REG_OP
mtd: spi-nor: spansion: add support for S28HS02GT
Tudor Ambarus (3):
mtd: spi-nor: spansion: let SFDP determine the flash and sector size
mtd: spi-nor: spansion: switch s25hx_t to use vreg_offset for
quad_enable()
mtd: spi-nor: spansion: switch cypress_nor_get_page_size() to use
vreg_offset
drivers/mtd/spi-nor/atmel.c | 8 +-
drivers/mtd/spi-nor/core.c | 23 ++-
drivers/mtd/spi-nor/core.h | 4 +-
drivers/mtd/spi-nor/issi.c | 4 +-
drivers/mtd/spi-nor/macronix.c | 4 +-
drivers/mtd/spi-nor/micron-st.c | 4 +-
drivers/mtd/spi-nor/spansion.c | 294 +++++++++++++++++++++-----------
drivers/mtd/spi-nor/sst.c | 8 +-
drivers/mtd/spi-nor/winbond.c | 4 +-
drivers/mtd/spi-nor/xilinx.c | 4 +-
10 files changed, 239 insertions(+), 118 deletions(-)
--
2.34.1
From: Takahiro Kuwano <[email protected]>
All the Infineon flashes that currently support octal DTR mode
define the optional SCCR SFDP table, thus all retrieve vreg_offset.
Switch all the available octal DTR Infineon flashes to use the
volatile register offset to set the configuration registers. The goal
is to have a single pair of methods for both single/multi-chip package
devices.
Signed-off-by: Takahiro Kuwano <[email protected]>
---
drivers/mtd/spi-nor/spansion.c | 23 +++++++++++++++++++----
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 51eabddf2b16..dc4841891b74 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -6,6 +6,7 @@
#include <linux/bitfield.h>
#include <linux/device.h>
+#include <linux/errno.h>
#include <linux/mtd/spi-nor.h>
#include "core.h"
@@ -202,14 +203,18 @@ static int cypress_nor_set_octal_dtr_bits(struct spi_nor *nor, u64 addr)
static int cypress_nor_octal_dtr_en(struct spi_nor *nor)
{
+ const struct spi_nor_flash_parameter *params = nor->params;
u8 *buf = nor->bouncebuf;
+ u64 addr;
int ret;
- ret = cypress_nor_set_memlat(nor, SPINOR_REG_CYPRESS_CFR2V);
+ addr = params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR2;
+ ret = cypress_nor_set_memlat(nor, addr);
if (ret)
return ret;
- ret = cypress_nor_set_octal_dtr_bits(nor, SPINOR_REG_CYPRESS_CFR5V);
+ addr = params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5;
+ ret = cypress_nor_set_octal_dtr_bits(nor, addr);
if (ret)
return ret;
@@ -247,9 +252,11 @@ static int cypress_nor_set_single_spi_bits(struct spi_nor *nor, u64 addr)
static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
{
u8 *buf = nor->bouncebuf;
+ u64 addr;
int ret;
- ret = cypress_nor_set_single_spi_bits(nor, SPINOR_REG_CYPRESS_CFR5V);
+ addr = nor->params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5;
+ ret = cypress_nor_set_single_spi_bits(nor, addr);
if (ret)
return ret;
@@ -714,7 +721,15 @@ static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor,
static int s28hx_t_late_init(struct spi_nor *nor)
{
- nor->params->set_octal_dtr = cypress_nor_set_octal_dtr;
+ struct spi_nor_flash_parameter *params = nor->params;
+
+ if (!params->n_dice || !params->vreg_offset) {
+ dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n",
+ __func__);
+ return -EOPNOTSUPP;
+ }
+
+ params->set_octal_dtr = cypress_nor_set_octal_dtr;
cypress_nor_ecc_init(nor);
return 0;
--
2.34.1
From: Takahiro Kuwano <[email protected]>
Infineon multi-chip package (MCP) devices require the Octal DTR
configuraion to be set on each die. We can access to configuration
registers in each die by using params->n_dice and params->vreg_offset[]
populated from SFDP. Add MCP support in set_octal_dtr().
Signed-off-by: Takahiro Kuwano <[email protected]>
---
drivers/mtd/spi-nor/spansion.c | 33 +++++++++++++++++++--------------
1 file changed, 19 insertions(+), 14 deletions(-)
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 5b6f36b56e9f..28d0a995f3b9 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -206,17 +206,19 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor)
const struct spi_nor_flash_parameter *params = nor->params;
u8 *buf = nor->bouncebuf;
u64 addr;
- int ret;
+ int i, ret;
- addr = params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR2;
- ret = cypress_nor_set_memlat(nor, addr);
- if (ret)
- return ret;
+ for (i = 0; i < params->n_dice; i++) {
+ addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR2;
+ ret = cypress_nor_set_memlat(nor, addr);
+ if (ret)
+ return ret;
- addr = params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5;
- ret = cypress_nor_set_octal_dtr_bits(nor, addr);
- if (ret)
- return ret;
+ addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5;
+ ret = cypress_nor_set_octal_dtr_bits(nor, addr);
+ if (ret)
+ return ret;
+ }
/* Read flash ID to make sure the switch was successful. */
ret = spi_nor_read_id(nor, nor->addr_nbytes, 3, buf,
@@ -251,14 +253,17 @@ static int cypress_nor_set_single_spi_bits(struct spi_nor *nor, u64 addr)
static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
{
+ const struct spi_nor_flash_parameter *params = nor->params;
u8 *buf = nor->bouncebuf;
u64 addr;
- int ret;
+ int i, ret;
- addr = nor->params->vreg_offset[0] + SPINOR_REG_CYPRESS_CFR5;
- ret = cypress_nor_set_single_spi_bits(nor, addr);
- if (ret)
- return ret;
+ for (i = 0; i < params->n_dice; i++) {
+ addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5;
+ ret = cypress_nor_set_single_spi_bits(nor, addr);
+ if (ret)
+ return ret;
+ }
/* Read flash ID to make sure the switch was successful. */
ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
--
2.34.1
From: Takahiro Kuwano <[email protected]>
Infineon's multi-chip package (MCP) devices require the octal DTR
configuration to be set for each die. Split common code in
dedicated methods to ease the octal DDR MCP support addition.
Signed-off-by: Takahiro Kuwano <[email protected]>
---
drivers/mtd/spi-nor/spansion.c | 50 +++++++++++++++++++++++++---------
1 file changed, 37 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 6460d2247bdf..51eabddf2b16 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -156,7 +156,7 @@ static int cypress_nor_sr_ready_and_clear(struct spi_nor *nor)
return 1;
}
-static int cypress_nor_octal_dtr_en(struct spi_nor *nor)
+static int cypress_nor_set_memlat(struct spi_nor *nor, u64 addr)
{
struct spi_mem_op op;
u8 *buf = nor->bouncebuf;
@@ -164,8 +164,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor)
u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
op = (struct spi_mem_op)
- CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes,
- SPINOR_REG_CYPRESS_CFR2V, 0, buf);
+ CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, buf);
ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
if (ret)
@@ -176,8 +175,7 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor)
*buf |= FIELD_PREP(SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK,
SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24);
op = (struct spi_mem_op)
- CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes,
- SPINOR_REG_CYPRESS_CFR2V, 1, buf);
+ CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, addr, 1, buf);
ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
if (ret)
@@ -185,13 +183,33 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor)
nor->read_dummy = 24;
+ return 0;
+}
+
+static int cypress_nor_set_octal_dtr_bits(struct spi_nor *nor, u64 addr)
+{
+ struct spi_mem_op op;
+ u8 *buf = nor->bouncebuf;
+
/* Set the octal and DTR enable bits. */
buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN;
op = (struct spi_mem_op)
- CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes,
- SPINOR_REG_CYPRESS_CFR5V, 1, buf);
+ CYPRESS_NOR_WR_ANY_REG_OP(nor->params->addr_mode_nbytes,
+ addr, 1, buf);
- ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+ return spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+}
+
+static int cypress_nor_octal_dtr_en(struct spi_nor *nor)
+{
+ u8 *buf = nor->bouncebuf;
+ int ret;
+
+ ret = cypress_nor_set_memlat(nor, SPINOR_REG_CYPRESS_CFR2V);
+ if (ret)
+ return ret;
+
+ ret = cypress_nor_set_octal_dtr_bits(nor, SPINOR_REG_CYPRESS_CFR5V);
if (ret)
return ret;
@@ -209,11 +227,10 @@ static int cypress_nor_octal_dtr_en(struct spi_nor *nor)
return 0;
}
-static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
+static int cypress_nor_set_single_spi_bits(struct spi_nor *nor, u64 addr)
{
struct spi_mem_op op;
u8 *buf = nor->bouncebuf;
- int ret;
/*
* The register is 1-byte wide, but 1-byte transactions are not allowed
@@ -223,9 +240,16 @@ static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS;
buf[1] = 0;
op = (struct spi_mem_op)
- CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes,
- SPINOR_REG_CYPRESS_CFR5V, 2, buf);
- ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
+ CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, addr, 2, buf);
+ return spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
+}
+
+static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
+{
+ u8 *buf = nor->bouncebuf;
+ int ret;
+
+ ret = cypress_nor_set_single_spi_bits(nor, SPINOR_REG_CYPRESS_CFR5V);
if (ret)
return ret;
--
2.34.1
From: Takahiro Kuwano <[email protected]>
Add support for S28HS02GT. Infineon S28HS02GT is a 2Gb,
multi-chip package, Octal SPI Flash.
Signed-off-by: Takahiro Kuwano <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
---
drivers/mtd/spi-nor/spansion.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 2fc3e65686b3..1f2b4a469719 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -695,22 +695,23 @@ static int cypress_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor)
{
+ struct spi_nor_flash_parameter *params = nor->params;
/*
* On older versions of the flash the xSPI Profile 1.0 table has the
* 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE.
*/
- if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)
- nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =
+ if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)
+ params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =
SPINOR_OP_CYPRESS_RD_FAST;
/* This flash is also missing the 4-byte Page Program opcode bit. */
- spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP],
+ spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
/*
* Since xSPI Page Program opcode is backward compatible with
* Legacy SPI, use Legacy SPI opcode there as well.
*/
- spi_nor_set_pp_settings(&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR],
+ spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR],
SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR);
/*
@@ -718,7 +719,11 @@ static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor)
* address bytes needed for Read Status Register command as 0 but the
* actual value for that is 4.
*/
- nor->params->rdsr_addr_nbytes = 4;
+ params->rdsr_addr_nbytes = 4;
+
+ /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */
+ if (params->size == SZ_256M)
+ params->n_dice = 2;
return cypress_nor_get_page_size(nor);
}
@@ -918,6 +923,11 @@ static const struct flash_info spansion_nor_parts[] = {
MFR_FLAGS(USE_CLPEF)
.fixups = &s28hx_t_fixups,
},
+ { "s28hs02gt", INFO(0x345b1c, 0, 0, 0)
+ PARSE_SFDP
+ MFR_FLAGS(USE_CLPEF)
+ .fixups = &s28hx_t_fixups,
+ },
};
/**
--
2.34.1
sector_size is used to determine the flash size and the erase size in
case of uniform erase. n_sectors is used to determine the flash_size.
But the flash size and the erase sizes are determined when parsing SFDP,
let SFDP determine them.
Signed-off-by: Tudor Ambarus <[email protected]>
---
drivers/mtd/spi-nor/spansion.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/mtd/spi-nor/spansion.c b/drivers/mtd/spi-nor/spansion.c
index 1f2b4a469719..413573cdb4fc 100644
--- a/drivers/mtd/spi-nor/spansion.c
+++ b/drivers/mtd/spi-nor/spansion.c
@@ -875,11 +875,11 @@ static const struct flash_info spansion_nor_parts[] = {
PARSE_SFDP
MFR_FLAGS(USE_CLPEF)
.fixups = &s25fs256t_fixups },
- { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 256 * 1024, 256)
+ { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 0, 0)
PARSE_SFDP
MFR_FLAGS(USE_CLPEF)
.fixups = &s25hx_t_fixups },
- { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 256 * 1024, 512)
+ { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 0, 0)
PARSE_SFDP
MFR_FLAGS(USE_CLPEF)
.fixups = &s25hx_t_fixups },
@@ -888,11 +888,11 @@ static const struct flash_info spansion_nor_parts[] = {
MFR_FLAGS(USE_CLPEF)
FLAGS(NO_CHIP_ERASE)
.fixups = &s25hx_t_fixups },
- { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 256 * 1024, 256)
+ { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 0, 0)
PARSE_SFDP
MFR_FLAGS(USE_CLPEF)
.fixups = &s25hx_t_fixups },
- { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 256 * 1024, 512)
+ { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 0, 0)
PARSE_SFDP
MFR_FLAGS(USE_CLPEF)
.fixups = &s25hx_t_fixups },
@@ -903,22 +903,22 @@ static const struct flash_info spansion_nor_parts[] = {
.fixups = &s25hx_t_fixups },
{ "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1)
FLAGS(SPI_NOR_NO_ERASE) },
- { "s28hl512t", INFO(0x345a1a, 0, 256 * 1024, 256)
+ { "s28hl512t", INFO(0x345a1a, 0, 0, 0)
PARSE_SFDP
MFR_FLAGS(USE_CLPEF)
.fixups = &s28hx_t_fixups,
},
- { "s28hl01gt", INFO(0x345a1b, 0, 256 * 1024, 512)
+ { "s28hl01gt", INFO(0x345a1b, 0, 0, 0)
PARSE_SFDP
MFR_FLAGS(USE_CLPEF)
.fixups = &s28hx_t_fixups,
},
- { "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256)
+ { "s28hs512t", INFO(0x345b1a, 0, 0, 0)
PARSE_SFDP
MFR_FLAGS(USE_CLPEF)
.fixups = &s28hx_t_fixups,
},
- { "s28hs01gt", INFO(0x345b1b, 0, 256 * 1024, 512)
+ { "s28hs01gt", INFO(0x345b1b, 0, 0, 0)
PARSE_SFDP
MFR_FLAGS(USE_CLPEF)
.fixups = &s28hx_t_fixups,
--
2.34.1
Hi Tudor,
I tested all SEMPER flash devices below.
S25FS256T
S25HS512T, S25HL512T, S25HS01GT, S25HL01GT
S25HS02GT, S25HL02GT
S28HS512T, S28HL512T, S28HS01GT, S28HL01GT
S28HS02GT
As I sent another email, S25FS256T failed due to SCCR map.
All other devices are OK.
Now we can remove these macros as we use vreg_offset.
#define SPINOR_REG_CYPRESS_CFR1V \
(SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR1)
#define SPINOR_REG_CYPRESS_CFR3V \
(SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR3)
#define SPINOR_REG_CYPRESS_CFR5V \
(SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR5)
Thanks,
Takahiro
On 7/24/2023 5:12 PM, Tudor Ambarus wrote:
> Resending as patch 10/11 and 11/11 were not sent.
>
> Takahiro, since you already have to test all these flashes, I took the
> liberty and added some other changes that would be good to have. The
> first one lets SFDP determine the flash size and sector size. Michael is
> in the process of changing how INFO is handled, we'd like to get rid of
> these params when SFDP tables are defined. The other 2 patches
> consolidates a bit the spansion code with the idea that we should use
> the same code paths for both single (SCP) and multi chip package (MCP)
> flashes were possible. We avoid this way code duplication and have
> better test coverage on the code. On your patches I modified how/where
> "if (!params->n_dice || !params->vreg_offset)" is handled. Please review
> all and if you agree with the changes, retest on all flashes. Everything
> looks good to me, if the tests pass, I'll queue all.
>
> Cheers,
> ta
>
>
> Takahiro Kuwano (8):
> mtd: spi-nor: spansion: use CLPEF as an alternative to CLSR
> mtd: spi-nor: spansion: preserve CFR2V[7] when writing MEMLAT
> mtd: spi-nor: spansion: prepare octal dtr methods for multi chip
> support
> mtd: spi-nor: spansion: switch set_octal_dtr method to use vreg_offset
> mtd: spi-nor: spansion: switch h28hx's ready() to use vreg_offset
> mtd: spi-nor: spansion: add MCP support in set_octal_dtr()
> mtd: spi-nor: spansion: add octal DTR support in RD_ANY_REG_OP
> mtd: spi-nor: spansion: add support for S28HS02GT
>
> Tudor Ambarus (3):
> mtd: spi-nor: spansion: let SFDP determine the flash and sector size
> mtd: spi-nor: spansion: switch s25hx_t to use vreg_offset for
> quad_enable()
> mtd: spi-nor: spansion: switch cypress_nor_get_page_size() to use
> vreg_offset
>
> drivers/mtd/spi-nor/atmel.c | 8 +-
> drivers/mtd/spi-nor/core.c | 23 ++-
> drivers/mtd/spi-nor/core.h | 4 +-
> drivers/mtd/spi-nor/issi.c | 4 +-
> drivers/mtd/spi-nor/macronix.c | 4 +-
> drivers/mtd/spi-nor/micron-st.c | 4 +-
> drivers/mtd/spi-nor/spansion.c | 294 +++++++++++++++++++++-----------
> drivers/mtd/spi-nor/sst.c | 8 +-
> drivers/mtd/spi-nor/winbond.c | 4 +-
> drivers/mtd/spi-nor/xilinx.c | 4 +-
> 10 files changed, 239 insertions(+), 118 deletions(-)
>