Add support to the FPGA manager for programming Lattice ECP5 FPGA over
slave SPI sysCONFIG interface.
ChangeLog:
v1 -> v2:
* remove "spi" from compatible string
* reword description in dt-bindings doc
* add reference to spi-peripheral-props.yaml in dt-binding doc
* fix DTS example in dt-bindings doc: 4-spaces indentations, no
undersores in node names.
v2 -> v3:
* fix typo "##size-cells" -> "#size-cells" in dt-bindings example
v3 -> v4:
* dt-bindings: reword description
* dt-bindings: revert props order
v4 -> v5:
* dt-bindings: remove trailing dot from title
* dt-bindings: reword description to avoid driver reference
* dt-bindings: add "Reviewed-by: Krzysztof Kozlowski" tag
v5 -> v6:
* ecp5-spi: lock SPI bus for exclusive usage in
ecp5_ops_write_init(), release in ecp5_ops_write_complete()
or on error
v6 -> v7:
* ecp5-spi.c -> lattice-sysconfig-spi.c. Reworked to represent
generalized sysCONFIG port with implementations for ECP5 and
MachXO2
* lattice,ecp5-fpga-mgr.yaml -> lattice,sysconfig.yaml. Reworked to
document both ECP5 and MachXO2 sysCONFIG.
* dt-bindings: remove "Reviewed-by: Krzysztof Kozlowski" tag as doc
was rewritten by a considerable amount.
v7 -> v8:
* dt-bindings: move "program-gpios", "init-gpios" and "done-gpios"
to top-level properties and disallow them for MachXO2 variant.
v8 -> v9:
* dt-bindings: "program-gpios", "init-gpios" and "done-gpios" are
now optional for both ECP5 and MachXO2
* lattice-sysconfig-spi.c -> sysconfig-spi.c + sysconfig.c +
sysconfig.h
** reworked to be one sysCONFIG FPGA Manager rather than two
distinct ECP5 and MachXO2 managers
** splitted to port type agnostic sysconfig.c and SPI-specific
sysconfig-spi.c
** command transfer function moved to callback for ease of
adding another port type, such as I2C
v9 -> v10:
* split sysconfig_transfer() callback into separate command_write()
and command_write_then_read(). There are too many transfers
without readback.
* add command_write_with_data() callback which performs single
transfer of command + data. It's needed for better abstraction of
paged bitstream write routine.
* move sysconfig_lsc_burst_init() to bitstream_burst_write_init()
callback to break dependence of sysconfig.c from sysconfig-spi.c
* move sysconfig_lsc_burst_complete() to bitstream_burst_write_complete()
callback to break dependence of sysconfig.c from sysconfig-spi.c
* add bitstream_burst_write() to abstract fpga_manager_ops->write()
from bus type
* remove struct spi_device from struct sysconfig_priv, use
to_spi_device()
* move fpga_manager_ops initialization to sysconfig.c
v10 -> v11:
* rename sysconfig_lsc_burst_init() to sysconfig_spi_lsc_burst_init()
* rename sysconfig_bitstream_burst_write() to
sysconfig_spi_bitstream_burst_write()
* rename sysconfig_lsc_burst_complete() to
sysconfig_spi_lsc_burst_complete()
* rename "ecp5-fpga-mgr" to "sysconfig-ecp5"
* rename "machxo2-fpga-mgr" to "sysconfig-machxo2"
* move spi_max_speed_hz from struct sysconfig_fpga_priv to
struct sysconfig_spi_fpga_priv, which is local to sysconfig-spi.c
* remove SPI bus unlock on write error form
sysconfig_spi_bitstream_burst_write(), call
sysconfig_burst_write_complete() on error in
sysconfig_bitstream_burst_write() instead.
v11 -> v12:
* build sysconfig core as separate module to prevent duplication of
common code segments across different binaries
* rename sysconfig.c to lattice-sysconfig.c
* rename sysconfig.h to lattice-sysconfig.h
* rename sysconfig-spi.c to lattice-sysconfig-spi.c
* rename sysconfig_spi_cmd_write_then_read() to
sysconfig_spi_cmd_read()
* rename command_write_then_read() callback to command_read()
* rename sysconfig_cmd_write_then_read() to sysconfig_cmd_read()
* rename sysconfig_spi_lsc_burst_init() to
sysconfig_spi_bitstream_burst_init()
* rename sysconfig_spi_lsc_burst_complete() to
sysconfig_spi_bitstream_burst_complete()
* remove excessive !spi check from sysconfig_spi_cmd_write(),
sysconfig_spi_cmd_read(), sysconfig_spi_bitstream_burst_init(),
sysconfig_spi_bitstream_burst_write() and
sysconfig_spi_bitstream_burst_complete()
* drop MachXO2 support
** drop struct sysconfig_fpga_priv
** drop paged write
** drop command_write_with_data() and friends
** drop ISC_PROGRAM_DONE routine
** drop refresh from sysconfig_isc_finish()
** sysconfig_isc_erase() only erase SRAM
** drop MachXO2 mentions from DT bindings doc
v12 -> v13:
* use device_get_match_data() instead of of_device_get_match_data()
and drop of_device.h inclusion
* in polling routines use time_before(jiffies, timeout) instead of
retries count
* add usleep_range() to gpio polling routine
* check fail status of command in more pronounced way
* check definition of sysconfig_priv callbacks at probe
* (BIT(23) | BIT(24) | BIT(25)) -> GENMASK(25, 23)
v13 -> v14:
* return -ETIMEDOUT instead of -EBUSY from sysconfig_poll_busy() to
align with sysconfig_poll_gpio()
v14 -> v15:
* move sysCONFIG commands from stack to heap, as spi-summary doc
says: "I/O buffers use the usual Linux rules, and must be
DMA-safe. [...] Don't use the stack, or anything that's declared
"static"."
** add u8 cmd_tx_buf[4] and u8 cmd_rx_buf[4] to
struct sysconfig_priv
** copy commands to cmd_tx_buf before sending to the device
** use cmd_rx_buf for commands readback
** change command_write() and command_read() signatures, as
command buffers are now embedded to sysconfig_priv
** combine sysconfig_read_busy() with sysconfig_poll_busy() to
avoid same memcpy in the loop
v15 -> v16:
* revert to v14
* combine command_write() and command_read() to command_transfer()
which uses spi_write_then_read() underhood. spi_write_then_read()
is dma-safe for on-stack buffers.
* in sysconfig_spi_bitstream_burst_init() bounce on-stack buffer
with LSC_BITSTREAM_BURST command to the heap. Now everything
should be dma-safe.
Ivan Bornyakov (2):
fpga: lattice-sysconfig-spi: add Lattice sysCONFIG FPGA manager
dt-bindings: fpga: document Lattice sysCONFIG FPGA manager
.../bindings/fpga/lattice,sysconfig.yaml | 81 ++++
drivers/fpga/Kconfig | 11 +
drivers/fpga/Makefile | 2 +
drivers/fpga/lattice-sysconfig-spi.c | 154 +++++++
drivers/fpga/lattice-sysconfig.c | 428 ++++++++++++++++++
drivers/fpga/lattice-sysconfig.h | 39 ++
6 files changed, 715 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/lattice,sysconfig.yaml
create mode 100644 drivers/fpga/lattice-sysconfig-spi.c
create mode 100644 drivers/fpga/lattice-sysconfig.c
create mode 100644 drivers/fpga/lattice-sysconfig.h
--
2.35.1
Add support to the FPGA manager for programming Lattice ECP5 FPGA over
slave SPI sysCONFIG interface.
sysCONFIG interface core functionality is separate from both ECP5 and
SPI specifics, so support for other FPGAs with different port types can
be added in the future.
Signed-off-by: Ivan Bornyakov <[email protected]>
---
drivers/fpga/Kconfig | 11 +
drivers/fpga/Makefile | 2 +
drivers/fpga/lattice-sysconfig-spi.c | 154 ++++++++++
drivers/fpga/lattice-sysconfig.c | 428 +++++++++++++++++++++++++++
drivers/fpga/lattice-sysconfig.h | 39 +++
5 files changed, 634 insertions(+)
create mode 100644 drivers/fpga/lattice-sysconfig-spi.c
create mode 100644 drivers/fpga/lattice-sysconfig.c
create mode 100644 drivers/fpga/lattice-sysconfig.h
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 09a014fba07c..1b8ea1a27274 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -267,4 +267,15 @@ config FPGA_MGR_MICROCHIP_SPI
programming over slave SPI interface with .dat formatted
bitstream image.
+config FPGA_MGR_LATTICE_SYSCONFIG
+ tristate
+
+config FPGA_MGR_LATTICE_SYSCONFIG_SPI
+ tristate "Lattice sysCONFIG SPI FPGA manager"
+ depends on SPI
+ select FPGA_MGR_LATTICE_SYSCONFIG
+ help
+ FPGA manager driver support for Lattice FPGAs programming over slave
+ SPI sysCONFIG interface.
+
endif # FPGA
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 1c97c196af50..0436f2c57065 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -20,6 +20,8 @@ obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o
obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o
obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o
obj-$(CONFIG_FPGA_MGR_MICROCHIP_SPI) += microchip-spi.o
+obj-$(CONFIG_FPGA_MGR_LATTICE_SYSCONFIG) += lattice-sysconfig.o
+obj-$(CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI) += lattice-sysconfig-spi.o
obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o
obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core-plat.o
diff --git a/drivers/fpga/lattice-sysconfig-spi.c b/drivers/fpga/lattice-sysconfig-spi.c
new file mode 100644
index 000000000000..bc264f30f18d
--- /dev/null
+++ b/drivers/fpga/lattice-sysconfig-spi.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Lattice FPGA programming over slave SPI sysCONFIG interface.
+ */
+
+#include <linux/spi/spi.h>
+
+#include "lattice-sysconfig.h"
+
+static const u32 ecp5_spi_max_speed_hz = 60000000;
+
+static int sysconfig_spi_cmd_transfer(struct sysconfig_priv *priv,
+ const void *tx_buf, size_t tx_len,
+ void *rx_buf, size_t rx_len)
+{
+ struct spi_device *spi = to_spi_device(priv->dev);
+
+ return spi_write_then_read(spi, tx_buf, tx_len, rx_buf, rx_len);
+}
+
+static int sysconfig_spi_bitstream_burst_init(struct sysconfig_priv *priv)
+{
+ const u8 lsc_bitstream_burst[] = SYSCONFIG_LSC_BITSTREAM_BURST;
+ struct spi_device *spi = to_spi_device(priv->dev);
+ struct spi_transfer xfer = { 0 };
+ struct spi_message msg;
+ size_t buf_len;
+ void *buf;
+ int ret;
+
+ buf_len = sizeof(lsc_bitstream_burst);
+
+ buf = kmalloc(buf_len, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ memcpy(buf, lsc_bitstream_burst, buf_len);
+
+ xfer.len = buf_len;
+ xfer.tx_buf = buf;
+ xfer.cs_change = 1;
+
+ spi_message_init_with_transfers(&msg, &xfer, 1);
+
+ /*
+ * Lock SPI bus for exclusive usage until FPGA programming is done.
+ * SPI bus will be released in sysconfig_spi_bitstream_burst_complete().
+ */
+ spi_bus_lock(spi->controller);
+
+ ret = spi_sync_locked(spi, &msg);
+ if (ret)
+ spi_bus_unlock(spi->controller);
+
+ kfree(buf);
+
+ return ret;
+}
+
+static int sysconfig_spi_bitstream_burst_write(struct sysconfig_priv *priv,
+ const char *buf, size_t len)
+{
+ struct spi_device *spi = to_spi_device(priv->dev);
+ struct spi_transfer xfer = {
+ .tx_buf = buf,
+ .len = len,
+ .cs_change = 1,
+ };
+ struct spi_message msg;
+
+ spi_message_init_with_transfers(&msg, &xfer, 1);
+
+ return spi_sync_locked(spi, &msg);
+}
+
+static int sysconfig_spi_bitstream_burst_complete(struct sysconfig_priv *priv)
+{
+ struct spi_device *spi = to_spi_device(priv->dev);
+
+ /* Bitstream burst write is done, release SPI bus */
+ spi_bus_unlock(spi->controller);
+
+ /* Toggle CS to finish bitstream write */
+ return spi_write(spi, NULL, 0);
+}
+
+static int sysconfig_spi_probe(struct spi_device *spi)
+{
+ const struct spi_device_id *dev_id;
+ struct device *dev = &spi->dev;
+ struct sysconfig_priv *priv;
+ const u32 *spi_max_speed;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spi_max_speed = device_get_match_data(dev);
+ if (!spi_max_speed) {
+ dev_id = spi_get_device_id(spi);
+ if (!dev_id)
+ return -ENODEV;
+
+ spi_max_speed = (const u32 *)dev_id->driver_data;
+ }
+
+ if (!spi_max_speed)
+ return -EINVAL;
+
+ if (spi->max_speed_hz > *spi_max_speed) {
+ dev_err(dev, "SPI speed %u is too high, maximum speed is %u\n",
+ spi->max_speed_hz, *spi_max_speed);
+ return -EINVAL;
+ }
+
+ priv->dev = dev;
+ priv->command_transfer = sysconfig_spi_cmd_transfer;
+ priv->bitstream_burst_write_init = sysconfig_spi_bitstream_burst_init;
+ priv->bitstream_burst_write = sysconfig_spi_bitstream_burst_write;
+ priv->bitstream_burst_write_complete = sysconfig_spi_bitstream_burst_complete;
+
+ return sysconfig_probe(priv);
+}
+
+static const struct spi_device_id sysconfig_spi_ids[] = {
+ {
+ .name = "sysconfig-ecp5",
+ .driver_data = (kernel_ulong_t)&ecp5_spi_max_speed_hz,
+ }, {},
+};
+MODULE_DEVICE_TABLE(spi, sysconfig_spi_ids);
+
+#if IS_ENABLED(CONFIG_OF)
+static const struct of_device_id sysconfig_of_ids[] = {
+ {
+ .compatible = "lattice,sysconfig-ecp5",
+ .data = &ecp5_spi_max_speed_hz,
+ }, {},
+};
+MODULE_DEVICE_TABLE(of, sysconfig_of_ids);
+#endif /* IS_ENABLED(CONFIG_OF) */
+
+static struct spi_driver lattice_sysconfig_driver = {
+ .probe = sysconfig_spi_probe,
+ .id_table = sysconfig_spi_ids,
+ .driver = {
+ .name = "lattice_sysconfig_spi_fpga_mgr",
+ .of_match_table = of_match_ptr(sysconfig_of_ids),
+ },
+};
+module_spi_driver(lattice_sysconfig_driver);
+
+MODULE_DESCRIPTION("Lattice sysCONFIG Slave SPI FPGA Manager");
+MODULE_LICENSE("GPL");
diff --git a/drivers/fpga/lattice-sysconfig.c b/drivers/fpga/lattice-sysconfig.c
new file mode 100644
index 000000000000..fd4d224b9b62
--- /dev/null
+++ b/drivers/fpga/lattice-sysconfig.c
@@ -0,0 +1,428 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Lattice FPGA sysCONFIG interface functions independent of port type.
+ */
+
+#include <linux/delay.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/gpio/consumer.h>
+
+#include "lattice-sysconfig.h"
+
+static int sysconfig_cmd_write(struct sysconfig_priv *priv, const void *buf,
+ size_t buf_len)
+{
+ return priv->command_transfer(priv, buf, buf_len, NULL, 0);
+}
+
+static int sysconfig_cmd_read(struct sysconfig_priv *priv, const void *tx_buf,
+ size_t tx_len, void *rx_buf, size_t rx_len)
+{
+ return priv->command_transfer(priv, tx_buf, tx_len, rx_buf, rx_len);
+}
+
+static int sysconfig_read_busy(struct sysconfig_priv *priv)
+{
+ const u8 lsc_check_busy[] = SYSCONFIG_LSC_CHECK_BUSY;
+ u8 busy;
+ int ret;
+
+ ret = sysconfig_cmd_read(priv, lsc_check_busy, sizeof(lsc_check_busy),
+ &busy, sizeof(busy));
+
+ return ret ? : busy;
+}
+
+static int sysconfig_poll_busy(struct sysconfig_priv *priv)
+{
+ unsigned long timeout;
+ int ret;
+
+ timeout = jiffies + msecs_to_jiffies(SYSCONFIG_POLL_BUSY_TIMEOUT_MS);
+
+ while (time_before(jiffies, timeout)) {
+ ret = sysconfig_read_busy(priv);
+ if (ret <= 0)
+ return ret;
+
+ usleep_range(SYSCONFIG_POLL_INTERVAL_US,
+ SYSCONFIG_POLL_INTERVAL_US * 2);
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int sysconfig_read_status(struct sysconfig_priv *priv, u32 *status)
+{
+ const u8 lsc_read_status[] = SYSCONFIG_LSC_READ_STATUS;
+ __be32 device_status;
+ int ret;
+
+ ret = sysconfig_cmd_read(priv, lsc_read_status, sizeof(lsc_read_status),
+ &device_status, sizeof(device_status));
+ if (ret)
+ return ret;
+
+ *status = be32_to_cpu(device_status);
+
+ return 0;
+}
+
+static int sysconfig_poll_status(struct sysconfig_priv *priv, u32 *status)
+{
+ int ret = sysconfig_poll_busy(priv);
+
+ if (ret)
+ return ret;
+
+ return sysconfig_read_status(priv, status);
+}
+
+static int sysconfig_poll_gpio(struct gpio_desc *gpio, bool is_active)
+{
+ unsigned long timeout;
+ int value;
+
+ timeout = jiffies + msecs_to_jiffies(SYSCONFIG_POLL_GPIO_TIMEOUT_MS);
+
+ while (time_before(jiffies, timeout)) {
+ value = gpiod_get_value(gpio);
+ if (value < 0)
+ return value;
+
+ if ((is_active && value) || (!is_active && !value))
+ return 0;
+
+ usleep_range(SYSCONFIG_POLL_INTERVAL_US,
+ SYSCONFIG_POLL_INTERVAL_US * 2);
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int sysconfig_gpio_refresh(struct sysconfig_priv *priv)
+{
+ struct gpio_desc *program = priv->program;
+ struct gpio_desc *init = priv->init;
+ struct gpio_desc *done = priv->done;
+ int ret;
+
+ /* Enter init mode */
+ gpiod_set_value(program, 1);
+
+ ret = sysconfig_poll_gpio(init, true);
+ if (!ret)
+ ret = sysconfig_poll_gpio(done, false);
+
+ if (ret)
+ return ret;
+
+ /* Enter program mode */
+ gpiod_set_value(program, 0);
+
+ return sysconfig_poll_gpio(init, false);
+}
+
+static int sysconfig_lsc_refresh(struct sysconfig_priv *priv)
+{
+ static const u8 lsc_refresh[] = SYSCONFIG_LSC_REFRESH;
+ int ret;
+
+ ret = sysconfig_cmd_write(priv, lsc_refresh, sizeof(lsc_refresh));
+ if (ret)
+ return ret;
+
+ usleep_range(4000, 8000);
+
+ return 0;
+}
+
+static int sysconfig_refresh(struct sysconfig_priv *priv)
+{
+ struct gpio_desc *program = priv->program;
+ struct gpio_desc *init = priv->init;
+ struct gpio_desc *done = priv->done;
+
+ if (program && init && done)
+ return sysconfig_gpio_refresh(priv);
+
+ return sysconfig_lsc_refresh(priv);
+}
+
+static int sysconfig_isc_enable(struct sysconfig_priv *priv)
+{
+ u8 isc_enable[] = SYSCONFIG_ISC_ENABLE;
+ u32 status;
+ int ret;
+
+ ret = sysconfig_cmd_write(priv, isc_enable, sizeof(isc_enable));
+ if (ret)
+ return ret;
+
+ ret = sysconfig_poll_status(priv, &status);
+ if (ret)
+ return ret;
+
+ if (status & SYSCONFIG_STATUS_FAIL)
+ return -EFAULT;
+
+ return 0;
+}
+
+static int sysconfig_isc_erase(struct sysconfig_priv *priv)
+{
+ u8 isc_erase[] = SYSCONFIG_ISC_ERASE;
+ u32 status;
+ int ret;
+
+ ret = sysconfig_cmd_write(priv, isc_erase, sizeof(isc_erase));
+ if (ret)
+ return ret;
+
+ ret = sysconfig_poll_status(priv, &status);
+ if (ret)
+ return ret;
+
+ if (status & SYSCONFIG_STATUS_FAIL)
+ return -EFAULT;
+
+ return 0;
+}
+
+static int sysconfig_isc_init(struct sysconfig_priv *priv)
+{
+ int ret = sysconfig_isc_enable(priv);
+
+ if (ret)
+ return ret;
+
+ return sysconfig_isc_erase(priv);
+}
+
+static int sysconfig_lsc_init_addr(struct sysconfig_priv *priv)
+{
+ const u8 lsc_init_addr[] = SYSCONFIG_LSC_INIT_ADDR;
+
+ return sysconfig_cmd_write(priv, lsc_init_addr, sizeof(lsc_init_addr));
+}
+
+static int sysconfig_burst_write_init(struct sysconfig_priv *priv)
+{
+ return priv->bitstream_burst_write_init(priv);
+}
+
+static int sysconfig_burst_write_complete(struct sysconfig_priv *priv)
+{
+ return priv->bitstream_burst_write_complete(priv);
+}
+
+static int sysconfig_bitstream_burst_write(struct sysconfig_priv *priv,
+ const char *buf, size_t count)
+{
+ int ret = priv->bitstream_burst_write(priv, buf, count);
+
+ if (ret)
+ sysconfig_burst_write_complete(priv);
+
+ return ret;
+}
+
+static int sysconfig_isc_disable(struct sysconfig_priv *priv)
+{
+ const u8 isc_disable[] = SYSCONFIG_ISC_DISABLE;
+
+ return sysconfig_cmd_write(priv, isc_disable, sizeof(isc_disable));
+}
+
+static void sysconfig_cleanup(struct sysconfig_priv *priv)
+{
+ sysconfig_isc_erase(priv);
+ sysconfig_refresh(priv);
+}
+
+static int sysconfig_isc_finish(struct sysconfig_priv *priv)
+{
+ struct gpio_desc *done_gpio = priv->done;
+ u32 status;
+ int ret;
+
+ if (done_gpio) {
+ ret = sysconfig_isc_disable(priv);
+ if (ret)
+ return ret;
+
+ return sysconfig_poll_gpio(done_gpio, true);
+ }
+
+ ret = sysconfig_poll_status(priv, &status);
+ if (ret)
+ return ret;
+
+ if ((status & SYSCONFIG_STATUS_DONE) &&
+ !(status & SYSCONFIG_STATUS_BUSY) &&
+ !(status & SYSCONFIG_STATUS_ERR))
+ return sysconfig_isc_disable(priv);
+
+ return -EFAULT;
+}
+
+static enum fpga_mgr_states sysconfig_ops_state(struct fpga_manager *mgr)
+{
+ struct sysconfig_priv *priv = mgr->priv;
+ struct gpio_desc *done = priv->done;
+ u32 status;
+ int ret;
+
+ if (done && (gpiod_get_value(done) > 0))
+ return FPGA_MGR_STATE_OPERATING;
+
+ ret = sysconfig_read_status(priv, &status);
+ if (!ret && (status & SYSCONFIG_STATUS_DONE))
+ return FPGA_MGR_STATE_OPERATING;
+
+ return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static int sysconfig_ops_write_init(struct fpga_manager *mgr,
+ struct fpga_image_info *info,
+ const char *buf, size_t count)
+{
+ struct sysconfig_priv *priv = mgr->priv;
+ struct device *dev = &mgr->dev;
+ int ret;
+
+ if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
+ dev_err(dev, "Partial reconfiguration is not supported\n");
+ return -EOPNOTSUPP;
+ }
+
+ /* Enter program mode */
+ ret = sysconfig_refresh(priv);
+ if (ret) {
+ dev_err(dev, "Failed to go to program mode\n");
+ return ret;
+ }
+
+ /* Enter ISC mode */
+ ret = sysconfig_isc_init(priv);
+ if (ret) {
+ dev_err(dev, "Failed to go to ISC mode\n");
+ return ret;
+ }
+
+ /* Initialize the Address Shift Register */
+ ret = sysconfig_lsc_init_addr(priv);
+ if (ret) {
+ dev_err(dev,
+ "Failed to initialize the Address Shift Register\n");
+ return ret;
+ }
+
+ /* Prepare for bitstream burst write */
+ ret = sysconfig_burst_write_init(priv);
+ if (ret)
+ dev_err(dev, "Failed to prepare for bitstream burst write\n");
+
+ return ret;
+}
+
+static int sysconfig_ops_write(struct fpga_manager *mgr, const char *buf,
+ size_t count)
+{
+ return sysconfig_bitstream_burst_write(mgr->priv, buf, count);
+}
+
+static int sysconfig_ops_write_complete(struct fpga_manager *mgr,
+ struct fpga_image_info *info)
+{
+ struct sysconfig_priv *priv = mgr->priv;
+ struct device *dev = &mgr->dev;
+ int ret;
+
+ ret = sysconfig_burst_write_complete(priv);
+ if (!ret)
+ ret = sysconfig_poll_busy(priv);
+
+ if (ret) {
+ dev_err(dev, "Error while waiting bitstream write to finish\n");
+ goto fail;
+ }
+
+ ret = sysconfig_isc_finish(priv);
+
+fail:
+ if (ret)
+ sysconfig_cleanup(priv);
+
+ return ret;
+}
+
+static const struct fpga_manager_ops sysconfig_fpga_mgr_ops = {
+ .state = sysconfig_ops_state,
+ .write_init = sysconfig_ops_write_init,
+ .write = sysconfig_ops_write,
+ .write_complete = sysconfig_ops_write_complete,
+};
+
+int sysconfig_probe(struct sysconfig_priv *priv)
+{
+ struct gpio_desc *program, *init, *done;
+ struct device *dev = priv->dev;
+ struct fpga_manager *mgr;
+ int ret;
+
+ if (!dev)
+ return -ENODEV;
+
+ if (!priv->bitstream_burst_write_init) {
+ dev_err(dev,
+ "Callback for preparation for bitstream burst write is not defined\n");
+ return -EOPNOTSUPP;
+ }
+
+ if (!priv->bitstream_burst_write) {
+ dev_err(dev,
+ "Callback for bitstream burst write is not defined\n");
+ return -EOPNOTSUPP;
+ }
+
+ if (!priv->bitstream_burst_write_complete) {
+ dev_err(dev,
+ "Callback for finishing bitstream burst write is not defined\n");
+ return -EOPNOTSUPP;
+ }
+
+ program = devm_gpiod_get_optional(dev, "program", GPIOD_OUT_LOW);
+ if (IS_ERR(program)) {
+ ret = PTR_ERR(program);
+ dev_err(dev, "Failed to get PROGRAM GPIO: %d\n", ret);
+ return ret;
+ }
+
+ init = devm_gpiod_get_optional(dev, "init", GPIOD_IN);
+ if (IS_ERR(init)) {
+ ret = PTR_ERR(init);
+ dev_err(dev, "Failed to get INIT GPIO: %d\n", ret);
+ return ret;
+ }
+
+ done = devm_gpiod_get_optional(dev, "done", GPIOD_IN);
+ if (IS_ERR(done)) {
+ ret = PTR_ERR(done);
+ dev_err(dev, "Failed to get DONE GPIO: %d\n", ret);
+ return ret;
+ }
+
+ priv->program = program;
+ priv->init = init;
+ priv->done = done;
+
+ mgr = devm_fpga_mgr_register(dev, "Lattice sysCONFIG FPGA Manager",
+ &sysconfig_fpga_mgr_ops, priv);
+
+ return PTR_ERR_OR_ZERO(mgr);
+}
+EXPORT_SYMBOL(sysconfig_probe);
+
+MODULE_DESCRIPTION("Lattice sysCONFIG FPGA Manager Core");
+MODULE_LICENSE("GPL");
diff --git a/drivers/fpga/lattice-sysconfig.h b/drivers/fpga/lattice-sysconfig.h
new file mode 100644
index 000000000000..e6af841b5a0e
--- /dev/null
+++ b/drivers/fpga/lattice-sysconfig.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __LATTICE_SYSCONFIG_H
+#define __LATTICE_SYSCONFIG_H
+
+#define SYSCONFIG_ISC_ENABLE {0xC6, 0x00, 0x00, 0x00}
+#define SYSCONFIG_ISC_DISABLE {0x26, 0x00, 0x00, 0x00}
+#define SYSCONFIG_ISC_ERASE {0x0E, 0x01, 0x00, 0x00}
+#define SYSCONFIG_LSC_READ_STATUS {0x3C, 0x00, 0x00, 0x00}
+#define SYSCONFIG_LSC_CHECK_BUSY {0xF0, 0x00, 0x00, 0x00}
+#define SYSCONFIG_LSC_REFRESH {0x79, 0x00, 0x00, 0x00}
+#define SYSCONFIG_LSC_INIT_ADDR {0x46, 0x00, 0x00, 0x00}
+#define SYSCONFIG_LSC_BITSTREAM_BURST {0x7a, 0x00, 0x00, 0x00}
+
+#define SYSCONFIG_STATUS_DONE BIT(8)
+#define SYSCONFIG_STATUS_BUSY BIT(12)
+#define SYSCONFIG_STATUS_FAIL BIT(13)
+#define SYSCONFIG_STATUS_ERR GENMASK(25, 23)
+
+#define SYSCONFIG_POLL_INTERVAL_US 30
+#define SYSCONFIG_POLL_BUSY_TIMEOUT_MS 1000
+#define SYSCONFIG_POLL_GPIO_TIMEOUT_MS 100
+
+struct sysconfig_priv {
+ struct gpio_desc *program;
+ struct gpio_desc *init;
+ struct gpio_desc *done;
+ struct device *dev;
+ int (*command_transfer)(struct sysconfig_priv *priv, const void *tx_buf,
+ size_t tx_len, void *rx_buf, size_t rx_len);
+ int (*bitstream_burst_write_init)(struct sysconfig_priv *priv);
+ int (*bitstream_burst_write)(struct sysconfig_priv *priv,
+ const char *tx_buf, size_t tx_len);
+ int (*bitstream_burst_write_complete)(struct sysconfig_priv *priv);
+};
+
+int sysconfig_probe(struct sysconfig_priv *priv);
+
+#endif /* __LATTICE_SYSCONFIG_H */
--
2.35.1
Hello Ivan,
On 10.10.22 19:27, Ivan Bornyakov wrote:
> Add support to the FPGA manager for programming Lattice ECP5 FPGA over
> slave SPI sysCONFIG interface.
>
> sysCONFIG interface core functionality is separate from both ECP5 and
> SPI specifics, so support for other FPGAs with different port types can
> be added in the future.
>
> Signed-off-by: Ivan Bornyakov <[email protected]>
I found a small issue with the probe function, see below. While at it,
I noted two nitpicks you could address.
> +static int sysconfig_spi_bitstream_burst_init(struct sysconfig_priv *priv)
> +{
> + const u8 lsc_bitstream_burst[] = SYSCONFIG_LSC_BITSTREAM_BURST;
> + struct spi_device *spi = to_spi_device(priv->dev);
> + struct spi_transfer xfer = { 0 };
Nitpick: You want to zero all members. Using {} makes your
intention clearer even if they are functionally equivalent.
> +static int sysconfig_poll_busy(struct sysconfig_priv *priv)
> +{
> + unsigned long timeout;
> + int ret;
> +
> + timeout = jiffies + msecs_to_jiffies(SYSCONFIG_POLL_BUSY_TIMEOUT_MS);
> +
> + while (time_before(jiffies, timeout)) {
> + ret = sysconfig_read_busy(priv);
> + if (ret <= 0)
> + return ret;
> +
> + usleep_range(SYSCONFIG_POLL_INTERVAL_US,
> + SYSCONFIG_POLL_INTERVAL_US * 2);
> + }
Nitpick: I believe you could rewrite that using read_poll_timeout().
> +int sysconfig_probe(struct sysconfig_priv *priv)
[snip]
> + program = devm_gpiod_get_optional(dev, "program", GPIOD_OUT_LOW);
> + if (IS_ERR(program)) {
> + ret = PTR_ERR(program);
> + dev_err(dev, "Failed to get PROGRAM GPIO: %d\n", ret);
> + return ret;
This would print an error message for -EPROBE_DEFER, which just confuses users.
Please use dev_err_probe instead here and elsewhere in the probe function
to avoid this.
Cheers,
Ahmad
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