2022-12-30 16:10:58

by Krzysztof Kozlowski

Subject: [PATCH 1/7] arm64: dts: qcom: sc8280xp: remove GCC from CX power domain

Bindings do not allow power-domain property in GCC clock controller and
documentation does not indicate that GCC is part of VDD_CX.

Signed-off-by: Krzysztof Kozlowski <[email protected]>

---

Maybe the bindings should be fixed? Maybe this was added as workaround?
Anyway looking at documentation I do not see such relation, except
downstream vdd_cx-supply (which is the same as in other SoCs and we do
not represent it in upstream).
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 -
1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 1d1420c8720c..d14663c9f34c 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -799,7 +799,6 @@ gcc: clock-controller@100000 {
<&pcie4_phy>,
<0>,
<0>;
- power-domains = <&rpmhpd SC8280XP_CX>;
};

ipcc: mailbox@408000 {
--
2.34.1

2022-12-30 16:13:34

by Krzysztof Kozlowski

Subject: [PATCH 2/7] arm64: dts: qcom: sc8280xp: align PSCI domain names with DT schema

Bindings expect power domains to follow generic naming pattern:

sc8280xp-crd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index d14663c9f34c..c39e51391286 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -549,55 +549,55 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";

- CPU_PD0: cpu0 {
+ CPU_PD0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD1: cpu1 {
+ CPU_PD1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD2: cpu2 {
+ CPU_PD2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD3: cpu3 {
+ CPU_PD3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD4: cpu4 {
+ CPU_PD4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};

- CPU_PD5: cpu5 {
+ CPU_PD5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};

- CPU_PD6: cpu6 {
+ CPU_PD6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};

- CPU_PD7: cpu7 {
+ CPU_PD7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};

- CLUSTER_PD: cpu-cluster0 {
+ CLUSTER_PD: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
};
--
2.34.1

2022-12-30 16:26:04

by Krzysztof Kozlowski

Subject: [PATCH 3/7] arm64: dts: qcom: sm6375: align PSCI domain names with DT schema

Bindings expect power domains to follow generic naming pattern:

sm6375-sony-xperia-murray-pdx225.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6375.dtsi | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
index 12cf5dbe5bd6..31b88c738510 100644
--- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
@@ -264,55 +264,55 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";

- CPU_PD0: cpu0 {
+ CPU_PD0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD1: cpu1 {
+ CPU_PD1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD2: cpu2 {
+ CPU_PD2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD3: cpu3 {
+ CPU_PD3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD4: cpu4 {
+ CPU_PD4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD5: cpu5 {
+ CPU_PD5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD6: cpu6 {
+ CPU_PD6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};

- CPU_PD7: cpu7 {
+ CPU_PD7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};

- CLUSTER_PD: cpu-cluster0 {
+ CLUSTER_PD: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
};
--
2.34.1

2022-12-30 16:27:00

by Krzysztof Kozlowski

Subject: [PATCH 4/7] arm64: dts: qcom: sm8150: align PSCI domain names with DT schema

Bindings expect power domains to follow generic naming pattern:

sm8150-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 5886710b3c65..08f8ff359b84 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -610,55 +610,55 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";

- CPU_PD0: cpu0 {
+ CPU_PD0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD1: cpu1 {
+ CPU_PD1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD2: cpu2 {
+ CPU_PD2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD3: cpu3 {
+ CPU_PD3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD4: cpu4 {
+ CPU_PD4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};

- CPU_PD5: cpu5 {
+ CPU_PD5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};

- CPU_PD6: cpu6 {
+ CPU_PD6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};

- CPU_PD7: cpu7 {
+ CPU_PD7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};

- CLUSTER_PD: cpu-cluster0 {
+ CLUSTER_PD: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
};
--
2.34.1

2022-12-30 16:27:38

by Krzysztof Kozlowski

Subject: [PATCH 7/7] arm64: dts: qcom: sm8450: align PSCI domain names with DT schema

Bindings expect power domains to follow generic naming pattern:

sm8450-qrd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 33db6b6c4123..5530bdee6f25 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -311,55 +311,55 @@ psci {
compatible = "arm,psci-1.0";
method = "smc";

- CPU_PD0: cpu0 {
+ CPU_PD0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD1: cpu1 {
+ CPU_PD1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD2: cpu2 {
+ CPU_PD2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD3: cpu3 {
+ CPU_PD3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};

- CPU_PD4: cpu4 {
+ CPU_PD4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};

- CPU_PD5: cpu5 {
+ CPU_PD5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};

- CPU_PD6: cpu6 {
+ CPU_PD6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};

- CPU_PD7: cpu7 {
+ CPU_PD7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};

- CLUSTER_PD: cpu-cluster0 {
+ CLUSTER_PD: power-domain-cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
};
--
2.34.1

2022-12-30 23:47:22

by Konrad Dybcio

Subject: Re: [PATCH 7/7] arm64: dts: qcom: sm8450: align PSCI domain names with DT schema

On 30.12.2022 17:01, Krzysztof Kozlowski wrote:
> Bindings expect power domains to follow generic naming pattern:
>
> sm8450-qrd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
> 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>

Konrad
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 33db6b6c4123..5530bdee6f25 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -311,55 +311,55 @@ psci {
> compatible = "arm,psci-1.0";
> method = "smc";
>
> - CPU_PD0: cpu0 {
> + CPU_PD0: power-domain-cpu0 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD1: cpu1 {
> + CPU_PD1: power-domain-cpu1 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD2: cpu2 {
> + CPU_PD2: power-domain-cpu2 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD3: cpu3 {
> + CPU_PD3: power-domain-cpu3 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD4: cpu4 {
> + CPU_PD4: power-domain-cpu4 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&BIG_CPU_SLEEP_0>;
> };
>
> - CPU_PD5: cpu5 {
> + CPU_PD5: power-domain-cpu5 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&BIG_CPU_SLEEP_0>;
> };
>
> - CPU_PD6: cpu6 {
> + CPU_PD6: power-domain-cpu6 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&BIG_CPU_SLEEP_0>;
> };
>
> - CPU_PD7: cpu7 {
> + CPU_PD7: power-domain-cpu7 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&BIG_CPU_SLEEP_0>;
> };
>
> - CLUSTER_PD: cpu-cluster0 {
> + CLUSTER_PD: power-domain-cpu-cluster0 {
> #power-domain-cells = <0>;
> domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
> };

2022-12-30 23:51:23

by Konrad Dybcio

Subject: Re: [PATCH 2/7] arm64: dts: qcom: sc8280xp: align PSCI domain names with DT schema

On 30.12.2022 17:00, Krzysztof Kozlowski wrote:
> Bindings expect power domains to follow generic naming pattern:
>
> sc8280xp-crd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
> 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>

Konrad
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index d14663c9f34c..c39e51391286 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -549,55 +549,55 @@ psci {
> compatible = "arm,psci-1.0";
> method = "smc";
>
> - CPU_PD0: cpu0 {
> + CPU_PD0: power-domain-cpu0 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD1: cpu1 {
> + CPU_PD1: power-domain-cpu1 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD2: cpu2 {
> + CPU_PD2: power-domain-cpu2 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD3: cpu3 {
> + CPU_PD3: power-domain-cpu3 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD4: cpu4 {
> + CPU_PD4: power-domain-cpu4 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&BIG_CPU_SLEEP_0>;
> };
>
> - CPU_PD5: cpu5 {
> + CPU_PD5: power-domain-cpu5 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&BIG_CPU_SLEEP_0>;
> };
>
> - CPU_PD6: cpu6 {
> + CPU_PD6: power-domain-cpu6 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&BIG_CPU_SLEEP_0>;
> };
>
> - CPU_PD7: cpu7 {
> + CPU_PD7: power-domain-cpu7 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&BIG_CPU_SLEEP_0>;
> };
>
> - CLUSTER_PD: cpu-cluster0 {
> + CLUSTER_PD: power-domain-cpu-cluster0 {
> #power-domain-cells = <0>;
> domain-idle-states = <&CLUSTER_SLEEP_0>;
> };

2022-12-30 23:54:13

by Konrad Dybcio

Subject: Re: [PATCH 3/7] arm64: dts: qcom: sm6375: align PSCI domain names with DT schema

On 30.12.2022 17:00, Krzysztof Kozlowski wrote:
> Bindings expect power domains to follow generic naming pattern:
>
> sm6375-sony-xperia-murray-pdx225.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
> 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>

Konrad
> arch/arm64/boot/dts/qcom/sm6375.dtsi | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi
> index 12cf5dbe5bd6..31b88c738510 100644
> --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi
> @@ -264,55 +264,55 @@ psci {
> compatible = "arm,psci-1.0";
> method = "smc";
>
> - CPU_PD0: cpu0 {
> + CPU_PD0: power-domain-cpu0 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD1: cpu1 {
> + CPU_PD1: power-domain-cpu1 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD2: cpu2 {
> + CPU_PD2: power-domain-cpu2 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD3: cpu3 {
> + CPU_PD3: power-domain-cpu3 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD4: cpu4 {
> + CPU_PD4: power-domain-cpu4 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD5: cpu5 {
> + CPU_PD5: power-domain-cpu5 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD6: cpu6 {
> + CPU_PD6: power-domain-cpu6 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&BIG_CPU_SLEEP_0>;
> };
>
> - CPU_PD7: cpu7 {
> + CPU_PD7: power-domain-cpu7 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&BIG_CPU_SLEEP_0>;
> };
>
> - CLUSTER_PD: cpu-cluster0 {
> + CLUSTER_PD: power-domain-cpu-cluster0 {
> #power-domain-cells = <0>;
> domain-idle-states = <&CLUSTER_SLEEP_0>;
> };

2022-12-30 23:55:51

by Konrad Dybcio

Subject: Re: [PATCH 1/7] arm64: dts: qcom: sc8280xp: remove GCC from CX power domain

On 30.12.2022 17:00, Krzysztof Kozlowski wrote:
> Bindings do not allow power-domain property in GCC clock controller and
> documentation does not indicate that GCC is part of VDD_CX.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>
> ---
>
> Maybe the bindings should be fixed? Maybe this was added as workaround?
> Anyway looking at documentation I do not see such relation, except
> downstream vdd_cx-supply (which is the same as in other SoCs and we do
> not represent it in upstream).
Some clocks scale with _CX, which is annotated on downstream with vdd-levels.
We take care of that by using opp tables in consumer drivers. Usually if
power-domains is added to a clock controller, it means that at least one of
the clocks needs the power domain to be on (which.. should be true for CX
if the ARM part runs anyway, no?), as for example VDD_MX/VDD_GFX may not be
on at boot and trying to enable such clocks would result in a big kaboom..

TL;DR: if nothing exploded, it's fine to remove it

Konrad
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 1d1420c8720c..d14663c9f34c 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -799,7 +799,6 @@ gcc: clock-controller@100000 {
> <&pcie4_phy>,
> <0>,
> <0>;
> - power-domains = <&rpmhpd SC8280XP_CX>;
> };
>
> ipcc: mailbox@408000 {

2022-12-31 00:00:58

by Konrad Dybcio

Subject: Re: [PATCH 4/7] arm64: dts: qcom: sm8150: align PSCI domain names with DT schema

On 30.12.2022 17:01, Krzysztof Kozlowski wrote:
> Bindings expect power domains to follow generic naming pattern:
>
> sm8150-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
> 'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>

Konrad
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index 5886710b3c65..08f8ff359b84 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -610,55 +610,55 @@ psci {
> compatible = "arm,psci-1.0";
> method = "smc";
>
> - CPU_PD0: cpu0 {
> + CPU_PD0: power-domain-cpu0 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD1: cpu1 {
> + CPU_PD1: power-domain-cpu1 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD2: cpu2 {
> + CPU_PD2: power-domain-cpu2 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD3: cpu3 {
> + CPU_PD3: power-domain-cpu3 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
> };
>
> - CPU_PD4: cpu4 {
> + CPU_PD4: power-domain-cpu4 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&BIG_CPU_SLEEP_0>;
> };
>
> - CPU_PD5: cpu5 {
> + CPU_PD5: power-domain-cpu5 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&BIG_CPU_SLEEP_0>;
> };
>
> - CPU_PD6: cpu6 {
> + CPU_PD6: power-domain-cpu6 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&BIG_CPU_SLEEP_0>;
> };
>
> - CPU_PD7: cpu7 {
> + CPU_PD7: power-domain-cpu7 {
> #power-domain-cells = <0>;
> power-domains = <&CLUSTER_PD>;
> domain-idle-states = <&BIG_CPU_SLEEP_0>;
> };
>
> - CLUSTER_PD: cpu-cluster0 {
> + CLUSTER_PD: power-domain-cpu-cluster0 {
> #power-domain-cells = <0>;
> domain-idle-states = <&CLUSTER_SLEEP_0>;
> };

2022-12-31 11:22:45

by Bryan O'Donoghue

Subject: Re: [PATCH 1/7] arm64: dts: qcom: sc8280xp: remove GCC from CX power domain

On Fri, Dec 30, 2022 at 4:04 PM Krzysztof Kozlowski
<[email protected]> wrote:
>
> Bindings do not allow power-domain property in GCC clock controller and
> documentation does not indicate that GCC is part of VDD_CX.
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>
> ---
>
> Maybe the bindings should be fixed? Maybe this was added as workaround?
> Anyway looking at documentation I do not see such relation, except
> downstream vdd_cx-supply (which is the same as in other SoCs and we do
> not represent it in upstream).
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 1d1420c8720c..d14663c9f34c 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -799,7 +799,6 @@ gcc: clock-controller@100000 {
> <&pcie4_phy>,
> <0>,
> <0>;
> - power-domains = <&rpmhpd SC8280XP_CX>;
> };
>
> ipcc: mailbox@408000 {
> --
> 2.34.1
>

You'd be better off adding the documentation. The CX rail is required
to power the clock controller.
If you are pulling this out and finding nothing breaks, its probably
because the bootloader left it on.

Per my understanding of what dts is though, we ought to be
representing the hardware dependency.

gcc is a root clock for just about every peripheral so, you can be
sure it is on when you boot.

Seems to me as if the right thing to do is to retain the dts and
update the documentation.

---
bod

2023-01-02 09:09:30

by Krzysztof Kozlowski

Subject: Re: [PATCH 1/7] arm64: dts: qcom: sc8280xp: remove GCC from CX power domain

On 31/12/2022 00:41, Konrad Dybcio wrote:
>
>
> On 30.12.2022 17:00, Krzysztof Kozlowski wrote:
>> Bindings do not allow power-domain property in GCC clock controller and
>> documentation does not indicate that GCC is part of VDD_CX.
>>
>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>>
>> ---
>>
>> Maybe the bindings should be fixed? Maybe this was added as workaround?
>> Anyway looking at documentation I do not see such relation, except
>> downstream vdd_cx-supply (which is the same as in other SoCs and we do
>> not represent it in upstream).
> Some clocks scale with _CX, which is annotated on downstream with vdd-levels.
> We take care of that by using opp tables in consumer drivers. Usually if
> power-domains is added to a clock controller, it means that at least one of
> the clocks needs the power domain to be on (which.. should be true for CX
> if the ARM part runs anyway, no?), as for example VDD_MX/VDD_GFX may not be
> on at boot and trying to enable such clocks would result in a big kaboom..
>
> TL;DR: if nothing exploded, it's fine to remove it

According to Bjorn, we should keep the domain.

Best regards,
Krzysztof