From: Alastair D'Silva <[email protected]>
When calling flush_icache_range with a size >4GB, we were masking
off the upper 32 bits, so we would incorrectly flush a range smaller
than intended.
This patch replaces the 32 bit shifts with 64 bit ones, so that
the full size is accounted for.
Heads-up for backporters: the old version of flush_dcache_range is
subject to a similar bug (this has since been replaced with a C
implementation).
Signed-off-by: Alastair D'Silva <[email protected]>
---
arch/powerpc/kernel/misc_64.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
index b55a7b4cb543..9bc0aa9aeb65 100644
--- a/arch/powerpc/kernel/misc_64.S
+++ b/arch/powerpc/kernel/misc_64.S
@@ -82,7 +82,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
subf r8,r6,r4 /* compute length */
add r8,r8,r5 /* ensure we get enough */
lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of cache block size */
- srw. r8,r8,r9 /* compute line count */
+ srd. r8,r8,r9 /* compute line count */
beqlr /* nothing to do? */
mtctr r8
1: dcbst 0,r6
@@ -98,7 +98,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
subf r8,r6,r4 /* compute length */
add r8,r8,r5
lwz r9,ICACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of Icache block size */
- srw. r8,r8,r9 /* compute line count */
+ srd. r8,r8,r9 /* compute line count */
beqlr /* nothing to do? */
mtctr r8
2: icbi 0,r6
--
2.21.0
Le 09/08/2019 à 02:45, Alastair D'Silva a écrit :
> From: Alastair D'Silva <[email protected]>
>
> When calling flush_icache_range with a size >4GB, we were masking
> off the upper 32 bits, so we would incorrectly flush a range smaller
> than intended.
>
> This patch replaces the 32 bit shifts with 64 bit ones, so that
> the full size is accounted for.
>
> Heads-up for backporters: the old version of flush_dcache_range is
> subject to a similar bug (this has since been replaced with a C
> implementation).
Can you submit a patch to stable, explaining this ?
>
> Signed-off-by: Alastair D'Silva <[email protected]>
Reviewed-by: Christophe Leroy <[email protected]>
Should add:
Cc: [email protected]
Christophe
> ---
> arch/powerpc/kernel/misc_64.S | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/powerpc/kernel/misc_64.S b/arch/powerpc/kernel/misc_64.S
> index b55a7b4cb543..9bc0aa9aeb65 100644
> --- a/arch/powerpc/kernel/misc_64.S
> +++ b/arch/powerpc/kernel/misc_64.S
> @@ -82,7 +82,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
> subf r8,r6,r4 /* compute length */
> add r8,r8,r5 /* ensure we get enough */
> lwz r9,DCACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of cache block size */
> - srw. r8,r8,r9 /* compute line count */
> + srd. r8,r8,r9 /* compute line count */
> beqlr /* nothing to do? */
> mtctr r8
> 1: dcbst 0,r6
> @@ -98,7 +98,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
> subf r8,r6,r4 /* compute length */
> add r8,r8,r5
> lwz r9,ICACHEL1LOGBLOCKSIZE(r10) /* Get log-2 of Icache block size */
> - srw. r8,r8,r9 /* compute line count */
> + srd. r8,r8,r9 /* compute line count */
> beqlr /* nothing to do? */
> mtctr r8
> 2: icbi 0,r6
>
On Fri, 2019-08-09 at 10:59 +0200, Christophe Leroy wrote:
>
> Le 09/08/2019 à 02:45, Alastair D'Silva a écrit :
> > From: Alastair D'Silva <[email protected]>
> >
> > When calling flush_icache_range with a size >4GB, we were masking
> > off the upper 32 bits, so we would incorrectly flush a range
> > smaller
> > than intended.
> >
> > This patch replaces the 32 bit shifts with 64 bit ones, so that
> > the full size is accounted for.
> >
> > Heads-up for backporters: the old version of flush_dcache_range is
> > subject to a similar bug (this has since been replaced with a C
> > implementation).
>
> Can you submit a patch to stable, explaining this ?
>
This patch was sent to stable too - or did you mean send another patch
for the stable asm version of flush_dcache_range?
--
Alastair D'Silva
Open Source Developer
Linux Technology Centre, IBM Australia
mob: 0423 762 819
Le 12/08/2019 à 03:19, Alastair D'Silva a écrit :
> On Fri, 2019-08-09 at 10:59 +0200, Christophe Leroy wrote:
>>
>> Le 09/08/2019 à 02:45, Alastair D'Silva a écrit :
>>> From: Alastair D'Silva <[email protected]>
>>>
>>> When calling flush_icache_range with a size >4GB, we were masking
>>> off the upper 32 bits, so we would incorrectly flush a range
>>> smaller
>>> than intended.
>>>
>>> This patch replaces the 32 bit shifts with 64 bit ones, so that
>>> the full size is accounted for.
>>>
>>> Heads-up for backporters: the old version of flush_dcache_range is
>>> subject to a similar bug (this has since been replaced with a C
>>> implementation).
>>
>> Can you submit a patch to stable, explaining this ?
>>
>
> This patch was sent to stable too - or did you mean send another patch
> for the stable asm version of flush_dcache_range?
>
Yes I meant a patch for your 'heads-up', in extenso a patch for fixing
flush_dcache_range().
And for this patch, you put stable is copy of the mail, but for it to be
taken into account it needs to also explicitely include a Cc:
[email protected] in the commit message. I guess Michael will add
it for this time.
Christophe