This series includes a few minor binding updates and base device tree
files (to boot to shell) for SC7280 SoC and the IDP board using this SoC.
Maulik Shah (3):
arm64: dts: qcom: sc7280: Add RSC and PDC devices
arm64: dts: qcom: Add reserved memory for fw
arm64: dts: qcom: sc7280: Add cpuidle states
Rajendra Nayak (6):
dt-bindings: arm: qcom: Document sc7280 SoC and board
dt-bindings: firmware: scm: Add sc7280 support
arm64: dts: sc7280: Add basic dts/dtsi files for sc7280 soc
dt-bindings: qcom,pdc: Add compatible for sc7280
arm64: dts: qcom: SC7280: Add rpmhcc clock controller node
arm64: dts: qcom: sc7280: Add rpmh power-domain node
Sai Prakash Ranjan (4):
dt-bindings: arm-smmu: Add compatible for SC7280 SoC
arm64: dts: qcom: sc7280: Add device node for APPS SMMU
dt-bindings: watchdog: Add compatible for SC7280 SoC
arm64: dts: qcom: sc7280: Add APSS watchdog node
satya priya (1):
arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280
Documentation/devicetree/bindings/arm/qcom.yaml | 6 +
.../devicetree/bindings/firmware/qcom,scm.txt | 1 +
.../bindings/interrupt-controller/qcom,pdc.txt | 1 +
.../devicetree/bindings/iommu/arm,smmu.yaml | 1 +
.../devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 ++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 609 +++++++++++++++++++++
8 files changed, 667 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add initial device tree support for the sc7280 SoC and the IDP
boards based on this SoC
Signed-off-by: Rajendra Nayak <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 +++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 299 ++++++++++++++++++++++++++++++++
3 files changed, 347 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 549a7a2..54cd8ea 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -40,6 +40,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-kb.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r3-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
new file mode 100644
index 0000000..950ecb2
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * sc7280 IDP board device tree source
+ *
+ * Copyright (c) 2021, The Linux Foundation. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "sc7280.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. sc7280 IDP platform";
+ compatible = "qcom,sc7280-idp", "qcom,sc7280";
+
+ aliases {
+ serial0 = &uart5;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+/* PINCTRL - additions to nodes defined in sc7280.dtsi */
+
+&qup_uart5_default {
+ tx {
+ pins = "gpio46";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx {
+ pins = "gpio47";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
new file mode 100644
index 0000000..4a56d9c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * sc7280 SoC device tree source
+ *
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ */
+
+#include <dt-bindings/clock/qcom,gcc-sc7280.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen { };
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ clock-frequency = <76800000>;
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L2_100>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ next-level-cache = <&L2_200>;
+ L2_200: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ next-level-cache = <&L2_300>;
+ L2_300: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ next-level-cache = <&L2_400>;
+ L2_400: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ next-level-cache = <&L2_500>;
+ L2_500: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ next-level-cache = <&L2_600>;
+ L2_600: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,kryo";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ next-level-cache = <&L2_700>;
+ L2_700: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0 0x80000000 0 0>;
+ };
+
+ firmware {
+ scm {
+ compatible = "qcom,scm-sc7280", "qcom,scm";
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ soc: soc@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0x10 0>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ compatible = "simple-bus";
+
+ gcc: clock-controller@100000 {
+ compatible = "qcom,gcc-sc7280";
+ reg = <0 0x00100000 0 0x1f0000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ qupv3_id_0: geniqup@9c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x009c0000 0 0x2000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ uart5: serial@994000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0 0x00994000 0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart5_default>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
+
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,sc7280-pinctrl";
+ reg = <0 0x0f100000 0 0x1000000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 175>;
+
+ qup_uart5_default: qup-uart5-default {
+ pins = "gpio46", "gpio47";
+ function = "qup13";
+ };
+ };
+
+ intc: interrupt-controller@17a00000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0 0x17a00000 0 0x10000>, /* GICD */
+ <0 0x17a60000 0 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+
+ gic-its@17a40000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ #msi-cells = <1>;
+ reg = <0 0x17a40000 0 0x20000>;
+ status = "disabled";
+ };
+ };
+
+ timer@17c20000 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ compatible = "arm,armv7-timer-mem";
+ reg = <0 0x17c20000 0 0x1000>;
+
+ frame@17c21000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0 0x17c21000 0 0x1000>,
+ <0 0x17c22000 0 0x1000>;
+ };
+
+ frame@17c23000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0 0x17c23000 0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c25000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0 0x17c25000 0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c27000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0 0x17c27000 0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c29000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0 0x17c29000 0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2b000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0 0x17c2b000 0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2d000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0 0x17c2d000 0 0x1000>;
+ status = "disabled";
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add compatible for sc7280 SoC
Signed-off-by: Rajendra Nayak <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
index a884955..1edc311 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -20,6 +20,7 @@ Required properties:
* "qcom,scm-msm8996"
* "qcom,scm-msm8998"
* "qcom,scm-sc7180"
+ * "qcom,scm-sc7280"
* "qcom,scm-sdm845"
* "qcom,scm-sm8150"
* "qcom,scm-sm8250"
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: Maulik Shah <[email protected]>
Add PDC interrupt controller along with apps RSC device.
Also add reserved memory for command_db.
Signed-off-by: Maulik Shah <[email protected]>
Signed-off-by: Rajendra Nayak <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 44 ++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 4a56d9c..21c2399 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
interrupt-parent = <&intc>;
@@ -30,6 +31,18 @@
};
};
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ aop_cmd_db_mem: memory@80860000 {
+ reg = <0x0 0x80860000 0x0 0x20000>;
+ compatible = "qcom,cmd-db";
+ no-map;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -194,6 +207,19 @@
};
};
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sc7280-pdc", "qcom,pdc";
+ reg = <0 0x0b220000 0 0x30000>;
+ qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
+ <55 306 4>, <59 312 3>, <62 374 2>,
+ <64 434 2>, <66 438 3>, <69 86 1>,
+ <70 520 54>, <124 609 31>, <155 63 1>,
+ <156 716 12>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
tlmm: pinctrl@f100000 {
compatible = "qcom,sc7280-pinctrl";
reg = <0 0x0f100000 0 0x1000000>;
@@ -203,6 +229,7 @@
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 175>;
+ wakeup-parent = <&pdc>;
qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
@@ -287,6 +314,23 @@
status = "disabled";
};
};
+
+ apps_rsc: rsc@18200000 {
+ compatible = "qcom,rpmh-rsc";
+ reg = <0 0x18200000 0 0x10000>,
+ <0 0x18210000 0 0x10000>,
+ <0 0x18220000 0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>,
+ <SLEEP_TCS 3>,
+ <WAKE_TCS 3>,
+ <CONTROL_TCS 1>;
+ };
};
timer {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: Maulik Shah <[email protected]>
Add fw reserved memory area for CPUCP (CPUSS control
processor) and AOP (Always ON processor)
Signed-off-by: Maulik Shah <[email protected]>
Signed-off-by: Rajendra Nayak <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 2d1209f..b4c522a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -37,11 +37,21 @@
#size-cells = <2>;
ranges;
+ aop_mem: memory@80800000 {
+ reg = <0x0 0x80800000 0x0 0x60000>;
+ no-map;
+ };
+
aop_cmd_db_mem: memory@80860000 {
reg = <0x0 0x80860000 0x0 0x20000>;
compatible = "qcom,cmd-db";
no-map;
};
+
+ cpucp_mem: memory@80b00000 {
+ no-map;
+ reg = <0x0 0x80b00000 0x0 0x100000>;
+ };
};
cpus {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: Sai Prakash Ranjan <[email protected]>
Add the SoC specific compatible for SC7280 implementing
arm,mmu-500.
Signed-off-by: Sai Prakash Ranjan <[email protected]>
Signed-off-by: Rajendra Nayak <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index 6ba161d..9d27aa5 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -34,6 +34,7 @@ properties:
items:
- enum:
- qcom,sc7180-smmu-500
+ - qcom,sc7280-smmu-500
- qcom,sc8180x-smmu-500
- qcom,sdm845-smmu-500
- qcom,sm8150-smmu-500
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: Sai Prakash Ranjan <[email protected]>
Adding device node for APPS SMMU available on SC7280 chipset.
This is shared among the multiple client devices such as
display, video, usb, mmc and others.
Signed-off-by: Sai Prakash Ranjan <[email protected]>
Signed-off-by: Rajendra Nayak <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 89 ++++++++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 9bfa1e06..2d1209f 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -246,6 +246,95 @@
};
};
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
+ reg = <0 0x15000000 0 0x100000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ dma-coherent;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: satya priya <[email protected]>
Add SPMI PMIC arbiter device to communicate with PMICs
attached to SPMI bus.
Signed-off-by: satya priya <[email protected]>
Signed-off-by: Rajendra Nayak <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index fe4fdb9..aa6f847 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -239,6 +239,25 @@
interrupt-controller;
};
+ spmi_bus: spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0 0x0c440000 0 0x1100>,
+ <0 0x0c600000 0 0x2000000>,
+ <0 0x0e600000 0 0x100000>,
+ <0 0x0e700000 0 0xa0000>,
+ <0 0x0c40a000 0 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ };
+
tlmm: pinctrl@f100000 {
compatible = "qcom,sc7280-pinctrl";
reg = <0 0x0f100000 0 0x1000000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: Sai Prakash Ranjan <[email protected]>
Add APSS (Application Processor Subsystem) watchdog
DT node for SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan <[email protected]>
Signed-off-by: Rajendra Nayak <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index b4c522a..fe4fdb9 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -365,6 +365,13 @@
};
};
+ watchdog@17c10000 {
+ compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
+ reg = <0 0x17c10000 0 0x1000>;
+ clocks = <&sleep_clk>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
timer@17c20000 {
#address-cells = <2>;
#size-cells = <2>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add the DT node for the rpmhpd power controller on SC7280 SoCs.
Signed-off-by: Rajendra Nayak <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 47 ++++++++++++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 06fbf2e..8af6d77 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@@ -543,6 +544,52 @@
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
+ rpmhpd: power-controller {
+ compatible = "qcom,sc7280-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp1 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_low_svs: opp2 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp4 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_svs_l2: opp5 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+ };
+
+ rpmhpd_opp_nom: opp6 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_turbo: opp8 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp9 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+
rpmhcc: clock-controller {
compatible = "qcom,sc7280-rpmh-clk";
clocks = <&xo_board>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: Sai Prakash Ranjan <[email protected]>
Add compatible for watchdog timer on SC7280 SoC.
Signed-off-by: Sai Prakash Ranjan <[email protected]>
Signed-off-by: Rajendra Nayak <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
index b8e4118..ba60bdf 100644
--- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
@@ -17,6 +17,7 @@ properties:
enum:
- qcom,apss-wdt-qcs404
- qcom,apss-wdt-sc7180
+ - qcom,apss-wdt-sc7280
- qcom,apss-wdt-sdm845
- qcom,apss-wdt-sdx55
- qcom,apss-wdt-sm8150
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
From: Maulik Shah <[email protected]>
Add cpuidle states for little and big cpus.
Signed-off-by: Maulik Shah <[email protected]>
Signed-off-by: Rajendra Nayak <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 78 ++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index aa6f847..06fbf2e 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -63,6 +63,9 @@
compatible = "arm,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -78,6 +81,9 @@
compatible = "arm,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
@@ -90,6 +96,9 @@
compatible = "arm,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
@@ -102,6 +111,9 @@
compatible = "arm,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
+ cpu-idle-states = <&LITTLE_CPU_SLEEP_0
+ &LITTLE_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
@@ -114,6 +126,9 @@
compatible = "arm,kryo";
reg = <0x0 0x400>;
enable-method = "psci";
+ cpu-idle-states = <&BIG_CPU_SLEEP_0
+ &BIG_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_400>;
L2_400: l2-cache {
compatible = "cache";
@@ -126,6 +141,9 @@
compatible = "arm,kryo";
reg = <0x0 0x500>;
enable-method = "psci";
+ cpu-idle-states = <&BIG_CPU_SLEEP_0
+ &BIG_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_500>;
L2_500: l2-cache {
compatible = "cache";
@@ -138,6 +156,9 @@
compatible = "arm,kryo";
reg = <0x0 0x600>;
enable-method = "psci";
+ cpu-idle-states = <&BIG_CPU_SLEEP_0
+ &BIG_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_600>;
L2_600: l2-cache {
compatible = "cache";
@@ -150,12 +171,69 @@
compatible = "arm,kryo";
reg = <0x0 0x700>;
enable-method = "psci";
+ cpu-idle-states = <&BIG_CPU_SLEEP_0
+ &BIG_CPU_SLEEP_1
+ &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_700>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
+
+ idle-states {
+ entry-method = "psci";
+
+ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "little-power-down";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <549>;
+ exit-latency-us = <901>;
+ min-residency-us = <1774>;
+ local-timer-stop;
+ };
+
+ LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "little-rail-power-down";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <702>;
+ exit-latency-us = <915>;
+ min-residency-us = <4001>;
+ local-timer-stop;
+ };
+
+ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "big-power-down";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <523>;
+ exit-latency-us = <1244>;
+ min-residency-us = <2207>;
+ local-timer-stop;
+ };
+
+ BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
+ compatible = "arm,idle-state";
+ idle-state-name = "big-rail-power-down";
+ arm,psci-suspend-param = <0x40000004>;
+ entry-latency-us = <526>;
+ exit-latency-us = <1854>;
+ min-residency-us = <5555>;
+ local-timer-stop;
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "cluster-power-down";
+ arm,psci-suspend-param = <0x40003444>;
+ entry-latency-us = <3263>;
+ exit-latency-us = <6562>;
+ min-residency-us = <9926>;
+ local-timer-stop;
+ };
+ };
};
memory@80000000 {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Quoting Rajendra Nayak (2021-03-03 04:17:47)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> new file mode 100644
> index 0000000..4a56d9c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -0,0 +1,299 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * sc7280 SoC device tree source
> + *
> + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <dt-bindings/clock/qcom,gcc-sc7280.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + clocks {
> + xo_board: xo-board {
> + compatible = "fixed-clock";
> + clock-frequency = <76800000>;
If this is the correct frequency I think we need to update the rpmh clk
driver to use the correct divider? Right now I think it is a 2 when it
should be 4?
> + #clock-cells = <0>;
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
> + #clock-cells = <0>;
> + };
> + };
Quoting Rajendra Nayak (2021-03-03 04:17:49)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 4a56d9c..21c2399 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -30,6 +31,18 @@
> };
> };
>
> + reserved_memory: reserved-memory {
Do we plan to use this label at any point? I'd prefer we remove this
until it becomes useful.
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + aop_cmd_db_mem: memory@80860000 {
> + reg = <0x0 0x80860000 0x0 0x20000>;
> + compatible = "qcom,cmd-db";
> + no-map;
> + };
> + };
> +
> cpus {
> #address-cells = <2>;
> #size-cells = <0>;
> @@ -203,6 +229,7 @@
> interrupt-controller;
> #interrupt-cells = <2>;
> gpio-ranges = <&tlmm 0 0 175>;
> + wakeup-parent = <&pdc>;
>
> qup_uart5_default: qup-uart5-default {
> pins = "gpio46", "gpio47";
> @@ -287,6 +314,23 @@
> status = "disabled";
> };
> };
> +
> + apps_rsc: rsc@18200000 {
Any better name than 'rsc'? Maybe 'power-controller'?
> + compatible = "qcom,rpmh-rsc";
> + reg = <0 0x18200000 0 0x10000>,
> + <0 0x18210000 0 0x10000>,
> + <0 0x18220000 0 0x10000>;
> + reg-names = "drv-0", "drv-1", "drv-2";
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,tcs-offset = <0xd00>;
> + qcom,drv-id = <2>;
> + qcom,tcs-config = <ACTIVE_TCS 2>,
> + <SLEEP_TCS 3>,
> + <WAKE_TCS 3>,
> + <CONTROL_TCS 1>;
> + };
> };
Add rpmhcc clock controller node for SC7280. Also add references to
rpmhcc clocks in gcc.
Signed-off-by: Taniya Das <[email protected]>
Signed-off-by: Rajendra Nayak <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 21c2399..9bfa1e06 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -6,6 +6,7 @@
*/
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -179,6 +180,14 @@
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sc7280";
reg = <0 0x00100000 0 0x1f0000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
+ <0>, <0>, <0>, <0>, <0>, <0>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
+ "pcie_0_pipe_clk", "pcie_1_pipe-clk",
+ "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
+ "ufs_phy_tx_symbol_0_clk",
+ "usb3_phy_wrapper_gcc_usb30_pipe_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@@ -330,6 +339,13 @@
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sc7280-rpmh-clk";
+ clocks = <&xo_board>;
+ clock-names = "xo";
+ #clock-cells = <1>;
+ };
};
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Add the compatible string for sc7180 SoC from Qualcomm
Signed-off-by: Rajendra Nayak <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
index e9afb48..98d89e5 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
@@ -19,6 +19,7 @@ Properties:
Value type: <string>
Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc"
- "qcom,sc7180-pdc": For SC7180
+ - "qcom,sc7280-pdc": For SC7280
- "qcom,sdm845-pdc": For SDM845
- "qcom,sdm8250-pdc": For SM8250
- "qcom,sdm8350-pdc": For SM8350
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Document the sc7280 SoC and the IDP board bindings
Signed-off-by: Rajendra Nayak <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 174134f..847f102 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -37,6 +37,7 @@ description: |
msm8994
msm8996
sc7180
+ sc7280
sdm630
sdm660
sdm845
@@ -166,6 +167,11 @@ properties:
- items:
- enum:
+ - qcom,sc7280-idp
+ - const: qcom,sc7280
+
+ - items:
+ - enum:
- xiaomi,lavender
- const: qcom,sdm660
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Quoting Rajendra Nayak (2021-03-03 04:17:56)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index fe4fdb9..aa6f847 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -239,6 +239,25 @@
> interrupt-controller;
> };
>
> + spmi_bus: spmi@c440000 {
> + compatible = "qcom,spmi-pmic-arb";
> + reg = <0 0x0c440000 0 0x1100>,
> + <0 0x0c600000 0 0x2000000>,
> + <0 0x0e600000 0 0x100000>,
> + <0 0x0e700000 0 0xa0000>,
> + <0 0x0c40a000 0 0x26000>;
> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
> + interrupt-names = "periph_irq";
> + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,ee = <0>;
> + qcom,channel = <0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
I see the binding says these should be 2 instead of 1 but I suspect that
is incorrect.
> + interrupt-controller;
> + #interrupt-cells = <4>;
> + cell-index = <0>;
Is cell-index used? Please remove as I don't see it used anywhere and
not in the binding.
> + };
> +
> tlmm: pinctrl@f100000 {
> compatible = "qcom,sc7280-pinctrl";
> reg = <0 0x0f100000 0 0x1000000>;
Quoting Rajendra Nayak (2021-03-03 04:17:57)
> From: Maulik Shah <[email protected]>
>
> Add cpuidle states for little and big cpus.
Please also say "The latency values are preliminary placeholders and will be updated
once testing provides the real numbers".
>
> Signed-off-by: Maulik Shah <[email protected]>
> Signed-off-by: Rajendra Nayak <[email protected]>
> ---
With that commit text update
Reviewed-by: Stephen Boyd <[email protected]>
Quoting Rajendra Nayak (2021-03-03 04:17:58)
> Add the DT node for the rpmhpd power controller on SC7280 SoCs.
>
> Signed-off-by: Rajendra Nayak <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
On 3/4/2021 5:34 AM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2021-03-03 04:17:49)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 4a56d9c..21c2399 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -30,6 +31,18 @@
>> };
>> };
>>
>> + reserved_memory: reserved-memory {
>
> Do we plan to use this label at any point? I'd prefer we remove this
> until it becomes useful.
sure, i'll drop it
>
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + aop_cmd_db_mem: memory@80860000 {
>> + reg = <0x0 0x80860000 0x0 0x20000>;
>> + compatible = "qcom,cmd-db";
>> + no-map;
>> + };
>> + };
>> +
>> cpus {
>> #address-cells = <2>;
>> #size-cells = <0>;
>> @@ -203,6 +229,7 @@
>> interrupt-controller;
>> #interrupt-cells = <2>;
>> gpio-ranges = <&tlmm 0 0 175>;
>> + wakeup-parent = <&pdc>;
>>
>> qup_uart5_default: qup-uart5-default {
>> pins = "gpio46", "gpio47";
>> @@ -287,6 +314,23 @@
>> status = "disabled";
>> };
>> };
>> +
>> + apps_rsc: rsc@18200000 {
>
> Any better name than 'rsc'? Maybe 'power-controller'?
hmm, Maulik, any thoughts? This would perhaps need the bindings docs
to be updated as well (and maybe the existing platform DTs using rsc too)
>
>> + compatible = "qcom,rpmh-rsc";
>> + reg = <0 0x18200000 0 0x10000>,
>> + <0 0x18210000 0 0x10000>,
>> + <0 0x18220000 0 0x10000>;
>> + reg-names = "drv-0", "drv-1", "drv-2";
>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
>> + qcom,tcs-offset = <0xd00>;
>> + qcom,drv-id = <2>;
>> + qcom,tcs-config = <ACTIVE_TCS 2>,
>> + <SLEEP_TCS 3>,
>> + <WAKE_TCS 3>,
>> + <CONTROL_TCS 1>;
>> + };
>> };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On 3/4/2021 5:42 AM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2021-03-03 04:17:56)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index fe4fdb9..aa6f847 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -239,6 +239,25 @@
>> interrupt-controller;
>> };
>>
>> + spmi_bus: spmi@c440000 {
>> + compatible = "qcom,spmi-pmic-arb";
>> + reg = <0 0x0c440000 0 0x1100>,
>> + <0 0x0c600000 0 0x2000000>,
>> + <0 0x0e600000 0 0x100000>,
>> + <0 0x0e700000 0 0xa0000>,
>> + <0 0x0c40a000 0 0x26000>;
>> + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
>> + interrupt-names = "periph_irq";
>> + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
>> + qcom,ee = <0>;
>> + qcom,channel = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>
> I see the binding says these should be 2 instead of 1 but I suspect that
> is incorrect.
yeah looks like the bindings need to be fixed
>
>> + interrupt-controller;
>> + #interrupt-cells = <4>;
>> + cell-index = <0>;
>
> Is cell-index used? Please remove as I don't see it used anywhere and
> not in the binding.
I'll drop it. thanks
>
>> + };
>> +
>> tlmm: pinctrl@f100000 {
>> compatible = "qcom,sc7280-pinctrl";
>> reg = <0 0x0f100000 0 0x1000000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
On 3/4/2021 5:43 AM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2021-03-03 04:17:57)
>> From: Maulik Shah <[email protected]>
>>
>> Add cpuidle states for little and big cpus.
>
> Please also say "The latency values are preliminary placeholders and will be updated
> once testing provides the real numbers".
will do when I respin, thanks.
>
>>
>> Signed-off-by: Maulik Shah <[email protected]>
>> Signed-off-by: Rajendra Nayak <[email protected]>
>> ---
>
> With that commit text update
>
> Reviewed-by: Stephen Boyd <[email protected]>
>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Hi,
On 3/5/2021 11:12 AM, Rajendra Nayak wrote:
>
> On 3/4/2021 5:34 AM, Stephen Boyd wrote:
>> Quoting Rajendra Nayak (2021-03-03 04:17:49)
>>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> index 4a56d9c..21c2399 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> @@ -30,6 +31,18 @@
>>> };
>>> };
>>> + reserved_memory: reserved-memory {
>>
>> Do we plan to use this label at any point? I'd prefer we remove this
>> until it becomes useful.
>
> sure, i'll drop it
>
>>
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> + ranges;
>>> +
>>> + aop_cmd_db_mem: memory@80860000 {
>>> + reg = <0x0 0x80860000 0x0 0x20000>;
>>> + compatible = "qcom,cmd-db";
>>> + no-map;
>>> + };
>>> + };
>>> +
>>> cpus {
>>> #address-cells = <2>;
>>> #size-cells = <0>;
>>> @@ -203,6 +229,7 @@
>>> interrupt-controller;
>>> #interrupt-cells = <2>;
>>> gpio-ranges = <&tlmm 0 0 175>;
>>> + wakeup-parent = <&pdc>;
>>> qup_uart5_default: qup-uart5-default {
>>> pins = "gpio46", "gpio47";
>>> @@ -287,6 +314,23 @@
>>> status = "disabled";
>>> };
>>> };
>>> +
>>> + apps_rsc: rsc@18200000 {
>>
>> Any better name than 'rsc'? Maybe 'power-controller'?
>
> hmm, Maulik, any thoughts? This would perhaps need the bindings docs
> to be updated as well (and maybe the existing platform DTs using rsc too)
I think we should be good with rsc (resource-state-coordinator). RSC
itself don't do any resource power management.
Thanks,
Maulik
>
>>
>>> + compatible = "qcom,rpmh-rsc";
>>> + reg = <0 0x18200000 0 0x10000>,
>>> + <0 0x18210000 0 0x10000>,
>>> + <0 0x18220000 0 0x10000>;
>>> + reg-names = "drv-0", "drv-1", "drv-2";
>>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
>>> + qcom,tcs-offset = <0xd00>;
>>> + qcom,drv-id = <2>;
>>> + qcom,tcs-config = <ACTIVE_TCS 2>,
>>> + <SLEEP_TCS 3>,
>>> + <WAKE_TCS 3>,
>>> + <CONTROL_TCS 1>;
>>> + };
>>> };
>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
On Wed, 03 Mar 2021 17:47:45 +0530, Rajendra Nayak wrote:
> Document the sc7280 SoC and the IDP board bindings
>
> Signed-off-by: Rajendra Nayak <[email protected]>
> Reviewed-by: Stephen Boyd <[email protected]>
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Acked-by: Rob Herring <[email protected]>
On Wed, 03 Mar 2021 17:47:48 +0530, Rajendra Nayak wrote:
> Add the compatible string for sc7180 SoC from Qualcomm
>
> Signed-off-by: Rajendra Nayak <[email protected]>
> Reviewed-by: Stephen Boyd <[email protected]>
> ---
> Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <[email protected]>
On Wed, 03 Mar 2021 17:47:46 +0530, Rajendra Nayak wrote:
> Add compatible for sc7280 SoC
>
> Signed-off-by: Rajendra Nayak <[email protected]>
> Reviewed-by: Stephen Boyd <[email protected]>
> ---
> Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <[email protected]>
On Wed, 03 Mar 2021 17:47:51 +0530, Rajendra Nayak wrote:
> From: Sai Prakash Ranjan <[email protected]>
>
> Add the SoC specific compatible for SC7280 implementing
> arm,mmu-500.
>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
> Signed-off-by: Rajendra Nayak <[email protected]>
> Reviewed-by: Stephen Boyd <[email protected]>
> ---
> Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <[email protected]>
On Wed, 03 Mar 2021 17:47:54 +0530, Rajendra Nayak wrote:
> From: Sai Prakash Ranjan <[email protected]>
>
> Add compatible for watchdog timer on SC7280 SoC.
>
> Signed-off-by: Sai Prakash Ranjan <[email protected]>
> Signed-off-by: Rajendra Nayak <[email protected]>
> Reviewed-by: Stephen Boyd <[email protected]>
> ---
> Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <[email protected]>
On 3/4/2021 5:37 AM, Stephen Boyd wrote:
> Quoting Rajendra Nayak (2021-03-03 04:17:47)
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> new file mode 100644
>> index 0000000..4a56d9c
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -0,0 +1,299 @@
>> +// SPDX-License-Identifier: BSD-3-Clause
>> +/*
>> + * sc7280 SoC device tree source
>> + *
>> + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/clock/qcom,gcc-sc7280.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> + interrupt-parent = <&intc>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + chosen { };
>> +
>> + clocks {
>> + xo_board: xo-board {
>> + compatible = "fixed-clock";
>> + clock-frequency = <76800000>;
>
> If this is the correct frequency I think we need to update the rpmh clk
> driver to use the correct divider? Right now I think it is a 2 when it
> should be 4?
Looks like this is fixed now [1]
[1] https://lore.kernel.org/patchwork/patch/1393159/
>
>> + #clock-cells = <0>;
>> + };
>> +
>> + sleep_clk: sleep-clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <32000>;
>> + #clock-cells = <0>;
>> + };
>> + };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Quoting Maulik Shah (2021-03-07 21:21:04)
> Hi,
>
> On 3/5/2021 11:12 AM, Rajendra Nayak wrote:
> >
> > On 3/4/2021 5:34 AM, Stephen Boyd wrote:
> >> Quoting Rajendra Nayak (2021-03-03 04:17:49)
> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> index 4a56d9c..21c2399 100644
> >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> >>> @@ -30,6 +31,18 @@
> >>> };
> >>> };
> >>> + reserved_memory: reserved-memory {
> >>
> >> Do we plan to use this label at any point? I'd prefer we remove this
> >> until it becomes useful.
> >
> > sure, i'll drop it
> >
> >>
> >>> + #address-cells = <2>;
> >>> + #size-cells = <2>;
> >>> + ranges;
> >>> +
> >>> + aop_cmd_db_mem: memory@80860000 {
> >>> + reg = <0x0 0x80860000 0x0 0x20000>;
> >>> + compatible = "qcom,cmd-db";
> >>> + no-map;
> >>> + };
> >>> + };
> >>> +
> >>> cpus {
> >>> #address-cells = <2>;
> >>> #size-cells = <0>;
> >>> @@ -203,6 +229,7 @@
> >>> interrupt-controller;
> >>> #interrupt-cells = <2>;
> >>> gpio-ranges = <&tlmm 0 0 175>;
> >>> + wakeup-parent = <&pdc>;
> >>> qup_uart5_default: qup-uart5-default {
> >>> pins = "gpio46", "gpio47";
> >>> @@ -287,6 +314,23 @@
> >>> status = "disabled";
> >>> };
> >>> };
> >>> +
> >>> + apps_rsc: rsc@18200000 {
> >>
> >> Any better name than 'rsc'? Maybe 'power-controller'?
> >
> > hmm, Maulik, any thoughts? This would perhaps need the bindings docs
> > to be updated as well (and maybe the existing platform DTs using rsc too)
>
> I think we should be good with rsc (resource-state-coordinator). RSC
> itself don't do any resource power management.
>
Maybe 'mailbox' then? Or 'remoteproc'? I am not "good" with rsc as it
isn't part of the standardized nodes names per the DT spec.