The lpass audio supports TX/RX/WSA block resets. The LPASS PIL clock
driver is not supported and mark it disabled. Also to keep consistency
update lpasscore to lpass_core.
Fixes: 9499240d15f2 ("arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers")
Signed-off-by: Taniya Das <[email protected]>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index e66fc67de206..180cfd2765b9 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2174,6 +2174,7 @@
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
+ status = "disabled";
};
lpass_audiocc: clock-controller@3300000 {
@@ -2185,6 +2186,7 @@
power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
+ #reset-cells = <1>;
};
lpass_aon: clock-controller@3380000 {
@@ -2198,7 +2200,7 @@
#power-domain-cells = <1>;
};
- lpasscore: clock-controller@3900000 {
+ lpass_core: clock-controller@3900000 {
compatible = "qcom,sc7280-lpasscorecc";
reg = <0 0x03900000 0 0x50000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
--
2.17.1
On Tue, Jun 14, 2022 at 09:41:18PM +0530, Taniya Das wrote:
> The lpass audio supports TX/RX/WSA block resets. The LPASS PIL clock
> driver is not supported and mark it disabled. Also to keep consistency
> update lpasscore to lpass_core.
There is a driver for "qcom,sc7280-lpasscc", what does it mean that is
isn't supported?
IIUC one problem is that 'lpasscc@3000000' and 'lpass_aon / clock-controller@3380000'
have overlapping register ranges, so they can't be used together.
You could just say 'Disable the LPASS PIL clock by default, boards
can enable it if needed'.
> Fixes: 9499240d15f2 ("arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers")
> Signed-off-by: Taniya Das <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index e66fc67de206..180cfd2765b9 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2174,6 +2174,7 @@
> clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
> clock-names = "iface";
> #clock-cells = <1>;
> + status = "disabled";
> };
>
> lpass_audiocc: clock-controller@3300000 {
> @@ -2185,6 +2186,7 @@
> power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
> #clock-cells = <1>;
> #power-domain-cells = <1>;
> + #reset-cells = <1>;
> };
>
> lpass_aon: clock-controller@3380000 {
> @@ -2198,7 +2200,7 @@
> #power-domain-cells = <1>;
> };
>
> - lpasscore: clock-controller@3900000 {
> + lpass_core: clock-controller@3900000 {
> compatible = "qcom,sc7280-lpasscorecc";
> reg = <0 0x03900000 0 0x50000>;
> clocks = <&rpmhcc RPMH_CXO_CLK>;
> --
> 2.17.1
>
Quoting Matthias Kaehlcke (2022-06-14 09:51:57)
> On Tue, Jun 14, 2022 at 09:41:18PM +0530, Taniya Das wrote:
> > The lpass audio supports TX/RX/WSA block resets. The LPASS PIL clock
> > driver is not supported and mark it disabled. Also to keep consistency
> > update lpasscore to lpass_core.
>
> There is a driver for "qcom,sc7280-lpasscc", what does it mean that is
> isn't supported?
>
> IIUC one problem is that 'lpasscc@3000000' and 'lpass_aon / clock-controller@3380000'
> have overlapping register ranges, so they can't be used together.
>
> You could just say 'Disable the LPASS PIL clock by default, boards
> can enable it if needed'.
For the pinctrl driver we added a "qcom,adsp-bypass-mode" property[1] to
indicate that the ADSP was being bypassed or not. Can we do the same
here and combine the device nodes that have overlapping reg properties?
[1] https://lore.kernel.org/r/[email protected]
Hi Taniya,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on linus/master v5.19-rc4 next-20220630]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Taniya-Das/arm64-dts-qcom-sc7280-Update-lpassaudio-clock-controller-for-resets/20220615-001326
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-defconfig (https://download.01.org/0day-ci/archive/20220701/[email protected]/config)
compiler: aarch64-linux-gcc (GCC) 11.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/3156737d3479e335c9ffd0d65e51b1ae6b6d1ec5
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Taniya-Das/arm64-dts-qcom-sc7280-Update-lpassaudio-clock-controller-for-resets/20220615-001326
git checkout 3156737d3479e335c9ffd0d65e51b1ae6b6d1ec5
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
>> ERROR: Input tree has errors, aborting (use -f to force output)
--
0-DAY CI Kernel Test Service
https://01.org/lkp
Hi Stephen,
On 6/15/2022 2:08 AM, Stephen Boyd wrote:
> Quoting Matthias Kaehlcke (2022-06-14 09:51:57)
>> On Tue, Jun 14, 2022 at 09:41:18PM +0530, Taniya Das wrote:
>>> The lpass audio supports TX/RX/WSA block resets. The LPASS PIL clock
>>> driver is not supported and mark it disabled. Also to keep consistency
>>> update lpasscore to lpass_core.
>>
>> There is a driver for "qcom,sc7280-lpasscc", what does it mean that is
>> isn't supported?
>>
>> IIUC one problem is that 'lpasscc@3000000' and 'lpass_aon / clock-controller@3380000'
>> have overlapping register ranges, so they can't be used together.
>>
>> You could just say 'Disable the LPASS PIL clock by default, boards
>> can enable it if needed'.
>
> For the pinctrl driver we added a "qcom,adsp-bypass-mode" property[1] to
> indicate that the ADSP was being bypassed or not. Can we do the same
> here and combine the device nodes that have overlapping reg properties?
>
> [1] https://lore.kernel.org/r/[email protected]
Could we take up as a cleanup and take it forward:
https://lore.kernel.org/lkml/[email protected]/T/#t
--
Thanks & Regards,
Taniya Das.
Quoting Taniya Das (2022-07-07 00:06:59)
>
> Hi Stephen,
>
> On 6/15/2022 2:08 AM, Stephen Boyd wrote:
> > Quoting Matthias Kaehlcke (2022-06-14 09:51:57)
> >> On Tue, Jun 14, 2022 at 09:41:18PM +0530, Taniya Das wrote:
> >>> The lpass audio supports TX/RX/WSA block resets. The LPASS PIL clock
> >>> driver is not supported and mark it disabled. Also to keep consistency
> >>> update lpasscore to lpass_core.
> >>
> >> There is a driver for "qcom,sc7280-lpasscc", what does it mean that is
> >> isn't supported?
> >>
> >> IIUC one problem is that 'lpasscc@3000000' and 'lpass_aon / clock-controller@3380000'
> >> have overlapping register ranges, so they can't be used together.
> >>
> >> You could just say 'Disable the LPASS PIL clock by default, boards
> >> can enable it if needed'.
> >
> > For the pinctrl driver we added a "qcom,adsp-bypass-mode" property[1] to
> > indicate that the ADSP was being bypassed or not. Can we do the same
> > here and combine the device nodes that have overlapping reg properties?
> >
> > [1] https://lore.kernel.org/r/[email protected]
>
> Could we take up as a cleanup and take it forward:
> https://lore.kernel.org/lkml/[email protected]/T/#t
>
I don't think so. The binding would need to change.