[1] is split into separate series in order for individual subsystem
Maintainers to pick up the patches. This series handles the PCIe
hwmod data for DRA7.
Please find the bootlog with these hwmod patches @ [2]
[1] -> https://lkml.org/lkml/2014/5/29/258
[2] -> http://paste.ubuntu.com/7701601/
Kishon Vijay Abraham I (2):
arm: dra7xx: Add hwmod data for pcie1 phy and pcie2 phy
arm: dra7xx: Add hwmod data for pcie1 and pcie2 subsystems
arch/arm/mach-omap2/cm2_7xx.h | 4 ++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 112 +++++++++++++++++++++++++++++
arch/arm/mach-omap2/prm7xx.h | 4 ++
3 files changed, 120 insertions(+)
--
1.7.9.5
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren <[email protected]>
Cc: Russell King <[email protected]>
Cc: Paul Walmsley <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Tested-by: Kishon Vijay Abraham I <[email protected]>
---
Please find the bootlog with these hwmod patches
http://paste.ubuntu.com/7701601/
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +++++++++++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 6ff40a6..934aa9d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+ .name = "pcie",
+};
+
+/* pcie1 */
+static struct omap_hwmod dra7xx_pcie1_hwmod = {
+ .name = "pcie1",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 */
+static struct omap_hwmod dra7xx_pcie2_hwmod = {
+ .name = "pcie2",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'PCIE PHY' class
*
*/
@@ -2448,6 +2485,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l4_cfg -> pcie1 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
.master = &dra7xx_l4_cfg_hwmod,
@@ -2813,6 +2866,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l4_cfg__pcie1,
+ &dra7xx_l4_cfg__pcie2,
&dra7xx_l4_cfg__pcie1_phy,
&dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
--
1.7.9.5
Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
for pcie1 phy and pcie2 phy.
Cc: Tony Lindgren <[email protected]>
Cc: Russell King <[email protected]>
Cc: Paul Walmsley <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Tested-by: Kishon Vijay Abraham I <[email protected]>
---
Please find the bootlog with these hwmod patches
http://paste.ubuntu.com/7701601/
arch/arm/mach-omap2/cm2_7xx.h | 4 ++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 57 +++++++++++++++++++++++++++++
arch/arm/mach-omap2/prm7xx.h | 4 ++
3 files changed, 65 insertions(+)
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
index 9ad7594..e966e3a 100644
--- a/arch/arm/mach-omap2/cm2_7xx.h
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -357,6 +357,10 @@
#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0
#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET 0x00b0
+#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET 0x00b8
+#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0
#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4
#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 3deb76e..6ff40a6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1290,6 +1290,45 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE PHY' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
+ .name = "pcie-phy",
+};
+
+/* pcie1 phy */
+static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
+ .name = "pcie1-phy",
+ .class = &dra7xx_pcie_phy_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 phy */
+static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
+ .name = "pcie2-phy",
+ .class = &dra7xx_pcie_phy_hwmod_class,
+ .clkdm_name = "l3init_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
+ .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'qspi' class
*
*/
@@ -2409,6 +2448,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l4_cfg -> pcie1 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_phy_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 phy */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_phy_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
{
.pa_start = 0x4b300000,
@@ -2758,6 +2813,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l4_cfg__pcie1_phy,
+ &dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
&dra7xx_l4_cfg__sata,
&dra7xx_l4_cfg__smartreflex_core,
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
index d92a840..4bb50fbf 100644
--- a/arch/arm/mach-omap2/prm7xx.h
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -374,6 +374,10 @@
#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
+#define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET 0x00b0
+#define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET 0x00b4
+#define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET 0x00b8
+#define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET 0x00bc
#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4
#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
--
1.7.9.5
On Wednesday 25 June 2014 11:32 PM, Kishon Vijay Abraham I wrote:
> Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
> Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
> for pcie1 phy and pcie2 phy.
>
> Cc: Tony Lindgren <[email protected]>
> Cc: Russell King <[email protected]>
> Cc: Paul Walmsley <[email protected]>
> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
> Tested-by: Kishon Vijay Abraham I <[email protected]>
Looks good to me, feel free to add
Reviewed-by: Rajendra Nayak <[email protected]>
> ---
> Please find the bootlog with these hwmod patches
> http://paste.ubuntu.com/7701601/
> arch/arm/mach-omap2/cm2_7xx.h | 4 ++
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 57 +++++++++++++++++++++++++++++
> arch/arm/mach-omap2/prm7xx.h | 4 ++
> 3 files changed, 65 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
> index 9ad7594..e966e3a 100644
> --- a/arch/arm/mach-omap2/cm2_7xx.h
> +++ b/arch/arm/mach-omap2/cm2_7xx.h
> @@ -357,6 +357,10 @@
> #define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
> #define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0
> #define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4
> +#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET 0x00b0
> +#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0)
> +#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET 0x00b8
> +#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8)
> #define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0
> #define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4
> #define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 3deb76e..6ff40a6 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1290,6 +1290,45 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> };
>
> /*
> + * 'PCIE PHY' class
> + *
> + */
> +
> +static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
> + .name = "pcie-phy",
> +};
> +
> +/* pcie1 phy */
> +static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
> + .name = "pcie1-phy",
> + .class = &dra7xx_pcie_phy_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
> + .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* pcie2 phy */
> +static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
> + .name = "pcie2-phy",
> + .class = &dra7xx_pcie_phy_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
> + .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> * 'qspi' class
> *
> */
> @@ -2409,6 +2448,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
> .user = OCP_USER_MPU | OCP_USER_SDMA,
> };
>
> +/* l4_cfg -> pcie1 phy */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie1_phy_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_cfg -> pcie2 phy */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie2_phy_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
> {
> .pa_start = 0x4b300000,
> @@ -2758,6 +2813,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
> &dra7xx_l4_cfg__mpu,
> &dra7xx_l4_cfg__ocp2scp1,
> &dra7xx_l4_cfg__ocp2scp3,
> + &dra7xx_l4_cfg__pcie1_phy,
> + &dra7xx_l4_cfg__pcie2_phy,
> &dra7xx_l3_main_1__qspi,
> &dra7xx_l4_cfg__sata,
> &dra7xx_l4_cfg__smartreflex_core,
> diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
> index d92a840..4bb50fbf 100644
> --- a/arch/arm/mach-omap2/prm7xx.h
> +++ b/arch/arm/mach-omap2/prm7xx.h
> @@ -374,6 +374,10 @@
> #define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
> #define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
> #define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
> +#define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET 0x00b0
> +#define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET 0x00b4
> +#define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET 0x00b8
> +#define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET 0x00bc
> #define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4
> #define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
> #define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
>
On Wednesday 25 June 2014 11:32 PM, Kishon Vijay Abraham I wrote:
> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>
> Cc: Tony Lindgren <[email protected]>
> Cc: Russell King <[email protected]>
> Cc: Paul Walmsley <[email protected]>
> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
> Tested-by: Kishon Vijay Abraham I <[email protected]>
> ---
> Please find the bootlog with these hwmod patches
> http://paste.ubuntu.com/7701601/
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 55 +++++++++++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 6ff40a6..934aa9d 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> };
>
> /*
> + * 'PCIE' class
> + *
> + */
> +
> +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
> + .name = "pcie",
> +};
> +
> +/* pcie1 */
> +static struct omap_hwmod dra7xx_pcie1_hwmod = {
> + .name = "pcie1",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
The TRM tells me it belongs to 'pcie_clkdm' instead. Can you please recheck?
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* pcie2 */
> +static struct omap_hwmod dra7xx_pcie2_hwmod = {
> + .name = "pcie2",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "l3init_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> * 'PCIE PHY' class
> *
> */
> @@ -2448,6 +2485,22 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
> .user = OCP_USER_MPU | OCP_USER_SDMA,
> };
>
> +/* l4_cfg -> pcie1 */
There seems to be a slave port on l3_init as well which seems to be missing?
Refer to 'Figure 24-157. PCIe Controllers Integration' of TRM version P.
regards,
Rajendra
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie1_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_cfg -> pcie2 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie2_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> /* l4_cfg -> pcie1 phy */
> static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
> .master = &dra7xx_l4_cfg_hwmod,
> @@ -2813,6 +2866,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
> &dra7xx_l4_cfg__mpu,
> &dra7xx_l4_cfg__ocp2scp1,
> &dra7xx_l4_cfg__ocp2scp3,
> + &dra7xx_l4_cfg__pcie1,
> + &dra7xx_l4_cfg__pcie2,
> &dra7xx_l4_cfg__pcie1_phy,
> &dra7xx_l4_cfg__pcie2_phy,
> &dra7xx_l3_main_1__qspi,
>
On Wed, 25 Jun 2014, Kishon Vijay Abraham I wrote:
> Added hwmod data for pcie1 and pcie2 phy present in DRA7xx SOC.
> Also added the missing CLKCTRL OFFSET macro and CONTEXT OFFSET macro
> for pcie1 phy and pcie2 phy.
>
> Cc: Tony Lindgren <[email protected]>
> Cc: Russell King <[email protected]>
> Cc: Paul Walmsley <[email protected]>
> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
> Tested-by: Kishon Vijay Abraham I <[email protected]>
Thanks, queued for v3.17 with Rajendra's ack.
- Paul
Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
Cc: Tony Lindgren <[email protected]>
Cc: Russell King <[email protected]>
Cc: Paul Walmsley <[email protected]>
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Tested-by: Kishon Vijay Abraham I <[email protected]>
---
Changes from v1:
* changed the clock domain to "pcie_clkdm"
* Added PCIe as a slave port for l3_main.
Boot log for dra7xx can be found at http://paste.ubuntu.com/7769402/
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 73 +++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 6ff40a6..2f37ca8 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
};
/*
+ * 'PCIE' class
+ *
+ */
+
+static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
+ .name = "pcie",
+};
+
+/* pcie1 */
+static struct omap_hwmod dra7xx_pcie1_hwmod = {
+ .name = "pcie1",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "pcie_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/* pcie2 */
+static struct omap_hwmod dra7xx_pcie2_hwmod = {
+ .name = "pcie2",
+ .class = &dra7xx_pcie_hwmod_class,
+ .clkdm_name = "pcie_clkdm",
+ .main_clk = "l4_root_clk_div",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
+ },
+ },
+};
+
+/*
* 'PCIE PHY' class
*
*/
@@ -2448,6 +2485,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
+/* l3_main_1 -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_pcie1_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie1 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie1_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l3_main_1 -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
+ .master = &dra7xx_l3_main_1_hwmod,
+ .slave = &dra7xx_pcie2_hwmod,
+ .clk = "l3_iclk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* l4_cfg -> pcie2 */
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
+ .master = &dra7xx_l4_cfg_hwmod,
+ .slave = &dra7xx_pcie2_hwmod,
+ .clk = "l4_root_clk_div",
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
/* l4_cfg -> pcie1 phy */
static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
.master = &dra7xx_l4_cfg_hwmod,
@@ -2813,6 +2882,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
&dra7xx_l4_cfg__mpu,
&dra7xx_l4_cfg__ocp2scp1,
&dra7xx_l4_cfg__ocp2scp3,
+ &dra7xx_l3_main_1__pcie1,
+ &dra7xx_l4_cfg__pcie1,
+ &dra7xx_l3_main_1__pcie2,
+ &dra7xx_l4_cfg__pcie2,
&dra7xx_l4_cfg__pcie1_phy,
&dra7xx_l4_cfg__pcie2_phy,
&dra7xx_l3_main_1__qspi,
--
1.7.9.5
On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>
> Cc: Tony Lindgren <[email protected]>
> Cc: Russell King <[email protected]>
> Cc: Paul Walmsley <[email protected]>
> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
> Tested-by: Kishon Vijay Abraham I <[email protected]>
> ---
> Changes from v1:
> * changed the clock domain to "pcie_clkdm"
> * Added PCIe as a slave port for l3_main.
Looks good to me,
Reviewed-by: Rajendra Nayak <[email protected]>
>
> Boot log for dra7xx can be found at http://paste.ubuntu.com/7769402/
>
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 73 +++++++++++++++++++++++++++++
> 1 file changed, 73 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index 6ff40a6..2f37ca8 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> };
>
> /*
> + * 'PCIE' class
> + *
> + */
> +
> +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
> + .name = "pcie",
> +};
> +
> +/* pcie1 */
> +static struct omap_hwmod dra7xx_pcie1_hwmod = {
> + .name = "pcie1",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "pcie_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/* pcie2 */
> +static struct omap_hwmod dra7xx_pcie2_hwmod = {
> + .name = "pcie2",
> + .class = &dra7xx_pcie_hwmod_class,
> + .clkdm_name = "pcie_clkdm",
> + .main_clk = "l4_root_clk_div",
> + .prcm = {
> + .omap4 = {
> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
> + .modulemode = MODULEMODE_SWCTRL,
> + },
> + },
> +};
> +
> +/*
> * 'PCIE PHY' class
> *
> */
> @@ -2448,6 +2485,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
> .user = OCP_USER_MPU | OCP_USER_SDMA,
> };
>
> +/* l3_main_1 -> pcie1 */
> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
> + .master = &dra7xx_l3_main_1_hwmod,
> + .slave = &dra7xx_pcie1_hwmod,
> + .clk = "l3_iclk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_cfg -> pcie1 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie1_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l3_main_1 -> pcie2 */
> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
> + .master = &dra7xx_l3_main_1_hwmod,
> + .slave = &dra7xx_pcie2_hwmod,
> + .clk = "l3_iclk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> +/* l4_cfg -> pcie2 */
> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
> + .master = &dra7xx_l4_cfg_hwmod,
> + .slave = &dra7xx_pcie2_hwmod,
> + .clk = "l4_root_clk_div",
> + .user = OCP_USER_MPU | OCP_USER_SDMA,
> +};
> +
> /* l4_cfg -> pcie1 phy */
> static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
> .master = &dra7xx_l4_cfg_hwmod,
> @@ -2813,6 +2882,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
> &dra7xx_l4_cfg__mpu,
> &dra7xx_l4_cfg__ocp2scp1,
> &dra7xx_l4_cfg__ocp2scp3,
> + &dra7xx_l3_main_1__pcie1,
> + &dra7xx_l4_cfg__pcie1,
> + &dra7xx_l3_main_1__pcie2,
> + &dra7xx_l4_cfg__pcie2,
> &dra7xx_l4_cfg__pcie1_phy,
> &dra7xx_l4_cfg__pcie2_phy,
> &dra7xx_l3_main_1__qspi,
>
On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote:
> On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
>> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>>
>> Cc: Tony Lindgren <[email protected]>
>> Cc: Russell King <[email protected]>
>> Cc: Paul Walmsley <[email protected]>
>> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
>> Tested-by: Kishon Vijay Abraham I <[email protected]>
>> ---
>> Changes from v1:
>> * changed the clock domain to "pcie_clkdm"
>> * Added PCIe as a slave port for l3_main.
>
> Looks good to me,
> Reviewed-by: Rajendra Nayak <[email protected]>
Paul,
Can you pick this one?
Thanks
Kishon
>
>>
>> Boot log for dra7xx can be found at http://paste.ubuntu.com/7769402/
>>
>> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 73 +++++++++++++++++++++++++++++
>> 1 file changed, 73 insertions(+)
>>
>> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> index 6ff40a6..2f37ca8 100644
>> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
>> @@ -1290,6 +1290,43 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
>> };
>>
>> /*
>> + * 'PCIE' class
>> + *
>> + */
>> +
>> +static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
>> + .name = "pcie",
>> +};
>> +
>> +/* pcie1 */
>> +static struct omap_hwmod dra7xx_pcie1_hwmod = {
>> + .name = "pcie1",
>> + .class = &dra7xx_pcie_hwmod_class,
>> + .clkdm_name = "pcie_clkdm",
>> + .main_clk = "l4_root_clk_div",
>> + .prcm = {
>> + .omap4 = {
>> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
>> + .modulemode = MODULEMODE_SWCTRL,
>> + },
>> + },
>> +};
>> +
>> +/* pcie2 */
>> +static struct omap_hwmod dra7xx_pcie2_hwmod = {
>> + .name = "pcie2",
>> + .class = &dra7xx_pcie_hwmod_class,
>> + .clkdm_name = "pcie_clkdm",
>> + .main_clk = "l4_root_clk_div",
>> + .prcm = {
>> + .omap4 = {
>> + .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
>> + .modulemode = MODULEMODE_SWCTRL,
>> + },
>> + },
>> +};
>> +
>> +/*
>> * 'PCIE PHY' class
>> *
>> */
>> @@ -2448,6 +2485,38 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
>> .user = OCP_USER_MPU | OCP_USER_SDMA,
>> };
>>
>> +/* l3_main_1 -> pcie1 */
>> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
>> + .master = &dra7xx_l3_main_1_hwmod,
>> + .slave = &dra7xx_pcie1_hwmod,
>> + .clk = "l3_iclk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_cfg -> pcie1 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
>> + .master = &dra7xx_l4_cfg_hwmod,
>> + .slave = &dra7xx_pcie1_hwmod,
>> + .clk = "l4_root_clk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l3_main_1 -> pcie2 */
>> +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
>> + .master = &dra7xx_l3_main_1_hwmod,
>> + .slave = &dra7xx_pcie2_hwmod,
>> + .clk = "l3_iclk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> +/* l4_cfg -> pcie2 */
>> +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
>> + .master = &dra7xx_l4_cfg_hwmod,
>> + .slave = &dra7xx_pcie2_hwmod,
>> + .clk = "l4_root_clk_div",
>> + .user = OCP_USER_MPU | OCP_USER_SDMA,
>> +};
>> +
>> /* l4_cfg -> pcie1 phy */
>> static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
>> .master = &dra7xx_l4_cfg_hwmod,
>> @@ -2813,6 +2882,10 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
>> &dra7xx_l4_cfg__mpu,
>> &dra7xx_l4_cfg__ocp2scp1,
>> &dra7xx_l4_cfg__ocp2scp3,
>> + &dra7xx_l3_main_1__pcie1,
>> + &dra7xx_l4_cfg__pcie1,
>> + &dra7xx_l3_main_1__pcie2,
>> + &dra7xx_l4_cfg__pcie2,
>> &dra7xx_l4_cfg__pcie1_phy,
>> &dra7xx_l4_cfg__pcie2_phy,
>> &dra7xx_l3_main_1__qspi,
>>
>
On Mon, 14 Jul 2014, Kishon Vijay Abraham I wrote:
> On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote:
> > On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
> >> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
> >>
> >> Cc: Tony Lindgren <[email protected]>
> >> Cc: Russell King <[email protected]>
> >> Cc: Paul Walmsley <[email protected]>
> >> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
> >> Tested-by: Kishon Vijay Abraham I <[email protected]>
> >> ---
> >> Changes from v1:
> >> * changed the clock domain to "pcie_clkdm"
> >> * Added PCIe as a slave port for l3_main.
> >
> > Looks good to me,
> > Reviewed-by: Rajendra Nayak <[email protected]>
>
> Paul,
>
> Can you pick this one?
Yep, queued for 3.17.
- Paul
On Wednesday 16 July 2014 01:43 AM, Paul Walmsley wrote:
> On Mon, 14 Jul 2014, Kishon Vijay Abraham I wrote:
>
>> On Wednesday 09 July 2014 04:32 PM, Rajendra Nayak wrote:
>>> On Wednesday 09 July 2014 02:32 PM, Kishon Vijay Abraham I wrote:
>>>> Added hwmod data for pcie1 and pcie2 subsystem present in DRA7xx SOC.
>>>>
>>>> Cc: Tony Lindgren <[email protected]>
>>>> Cc: Russell King <[email protected]>
>>>> Cc: Paul Walmsley <[email protected]>
>>>> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
>>>> Tested-by: Kishon Vijay Abraham I <[email protected]>
>>>> ---
>>>> Changes from v1:
>>>> * changed the clock domain to "pcie_clkdm"
>>>> * Added PCIe as a slave port for l3_main.
>>>
>>> Looks good to me,
>>> Reviewed-by: Rajendra Nayak <[email protected]>
>>
>> Paul,
>>
>> Can you pick this one?
>
> Yep, queued for 3.17.
Thanks :-)
-Kishon
>
> - Paul
>