Folks, the following is what I've queued for this.
- Paul
From: Sekhar Nori <[email protected]>
Date: Thu, 18 Feb 2016 16:49:56 +0530
Subject: [PATCH] ARM: DRA7: hwmod: Add custom reset handler for PCIeSS
Add a custom reset handler for DRA7x PCIeSS. This
handler is required to deassert PCIe hardreset lines
after they have been asserted.
This enables the PCIe driver to access registers after
PCIeSS has been runtime enabled without having to
deassert hardreset lines itself.
With this patch applied, used lspci to make sure
connected PCIe device enumerates on DRA74x and DRA72x
EVMs.
Signed-off-by: Sekhar Nori <[email protected]>
Reported-by: Richard Cochran <[email protected]>
Tested-by: Kishon Vijay Abraham I <[email protected]>
Cc: Suman Anna <[email protected]>
Cc: Dave Gerlach <[email protected]>
Cc: Tony Lindgren <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Russell King <[email protected]>
Signed-off-by: Paul Walmsley <[email protected]>
---
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index b61355e2a771..252b74633e31 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -1526,8 +1526,31 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
*
*/
+/*
+ * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
+ * functionality of OMAP HWMOD layer does not deassert the hardreset lines
+ * associated with an IP automatically leaving the driver to handle that
+ * by itself. This does not work for PCIeSS which needs the reset lines
+ * deasserted for the driver to start accessing registers.
+ *
+ * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
+ * lines after asserting them.
+ */
+static int dra7xx_pciess_reset(struct omap_hwmod *oh)
+{
+ int i;
+
+ for (i = 0; i < oh->rst_lines_cnt; i++) {
+ omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
+ omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
+ }
+
+ return 0;
+}
+
static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
.name = "pcie",
+ .reset = dra7xx_pciess_reset,
};
/* pcie1 */
--
2.7.0
Hi,
On Tuesday 01 March 2016 01:55 PM, Paul Walmsley wrote:
>
> Folks, the following is what I've queued for this.
Thanks Paul.
Bjorn,
With this patch merged, enabling pci-dra7xx won't result in system freeze
anymore. I can send a patch to revert depends on BROKEN.
Thanks
Kishon
>
>
> - Paul
>
>
> From: Sekhar Nori <[email protected]>
> Date: Thu, 18 Feb 2016 16:49:56 +0530
> Subject: [PATCH] ARM: DRA7: hwmod: Add custom reset handler for PCIeSS
>
> Add a custom reset handler for DRA7x PCIeSS. This
> handler is required to deassert PCIe hardreset lines
> after they have been asserted.
>
> This enables the PCIe driver to access registers after
> PCIeSS has been runtime enabled without having to
> deassert hardreset lines itself.
>
> With this patch applied, used lspci to make sure
> connected PCIe device enumerates on DRA74x and DRA72x
> EVMs.
>
> Signed-off-by: Sekhar Nori <[email protected]>
> Reported-by: Richard Cochran <[email protected]>
> Tested-by: Kishon Vijay Abraham I <[email protected]>
> Cc: Suman Anna <[email protected]>
> Cc: Dave Gerlach <[email protected]>
> Cc: Tony Lindgren <[email protected]>
> Cc: Bjorn Helgaas <[email protected]>
> Cc: Russell King <[email protected]>
> Signed-off-by: Paul Walmsley <[email protected]>
> ---
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> index b61355e2a771..252b74633e31 100644
> --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> @@ -1526,8 +1526,31 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> *
> */
>
> +/*
> + * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
> + * functionality of OMAP HWMOD layer does not deassert the hardreset lines
> + * associated with an IP automatically leaving the driver to handle that
> + * by itself. This does not work for PCIeSS which needs the reset lines
> + * deasserted for the driver to start accessing registers.
> + *
> + * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
> + * lines after asserting them.
> + */
> +static int dra7xx_pciess_reset(struct omap_hwmod *oh)
> +{
> + int i;
> +
> + for (i = 0; i < oh->rst_lines_cnt; i++) {
> + omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
> + omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
> + }
> +
> + return 0;
> +}
> +
> static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
> .name = "pcie",
> + .reset = dra7xx_pciess_reset,
> };
>
> /* pcie1 */
>
On Tue, Mar 01, 2016 at 05:25:56PM +0530, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 01 March 2016 01:55 PM, Paul Walmsley wrote:
> >
> > Folks, the following is what I've queued for this.
>
> Thanks Paul.
>
> Bjorn,
>
> With this patch merged, enabling pci-dra7xx won't result in system freeze
> anymore. I can send a patch to revert depends on BROKEN.
Great! Please send me that patch, and I'll merge it for v4.6.
> > From: Sekhar Nori <[email protected]>
> > Date: Thu, 18 Feb 2016 16:49:56 +0530
> > Subject: [PATCH] ARM: DRA7: hwmod: Add custom reset handler for PCIeSS
> >
> > Add a custom reset handler for DRA7x PCIeSS. This
> > handler is required to deassert PCIe hardreset lines
> > after they have been asserted.
> >
> > This enables the PCIe driver to access registers after
> > PCIeSS has been runtime enabled without having to
> > deassert hardreset lines itself.
> >
> > With this patch applied, used lspci to make sure
> > connected PCIe device enumerates on DRA74x and DRA72x
> > EVMs.
> >
> > Signed-off-by: Sekhar Nori <[email protected]>
> > Reported-by: Richard Cochran <[email protected]>
> > Tested-by: Kishon Vijay Abraham I <[email protected]>
> > Cc: Suman Anna <[email protected]>
> > Cc: Dave Gerlach <[email protected]>
> > Cc: Tony Lindgren <[email protected]>
> > Cc: Bjorn Helgaas <[email protected]>
> > Cc: Russell King <[email protected]>
> > Signed-off-by: Paul Walmsley <[email protected]>
> > ---
> > arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 23 +++++++++++++++++++++++
> > 1 file changed, 23 insertions(+)
> >
> > diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> > index b61355e2a771..252b74633e31 100644
> > --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> > +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
> > @@ -1526,8 +1526,31 @@ static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
> > *
> > */
> >
> > +/*
> > + * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
> > + * functionality of OMAP HWMOD layer does not deassert the hardreset lines
> > + * associated with an IP automatically leaving the driver to handle that
> > + * by itself. This does not work for PCIeSS which needs the reset lines
> > + * deasserted for the driver to start accessing registers.
> > + *
> > + * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
> > + * lines after asserting them.
> > + */
> > +static int dra7xx_pciess_reset(struct omap_hwmod *oh)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < oh->rst_lines_cnt; i++) {
> > + omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
> > + omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
> > .name = "pcie",
> > + .reset = dra7xx_pciess_reset,
> > };
> >
> > /* pcie1 */
> >
On 03/01/2016 05:55 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Tuesday 01 March 2016 01:55 PM, Paul Walmsley wrote:
>>
>> Folks, the following is what I've queued for this.
>
> Thanks Paul.
>
> Bjorn,
>
> With this patch merged, enabling pci-dra7xx won't result in system freeze
> anymore. I can send a patch to revert depends on BROKEN.
Kishon,
Make sure you send only that after both this patch and the pcie reset
data are in. I see the pcie reset data in Paul's for-4.6 branch.
regards
Suman
[snip]