This series clears the chaos of barrier misuse.
In prepration of light weight barrier series.
Jiaxun Yang (3):
MIPS: Loongson64: Clearify IO barriers
MIPS: io.h use barrier terminology from asm-generic
MIPS: io.h: Remove barriers before MMIO accessors for CPU without WB
arch/mips/Kconfig | 1 -
arch/mips/include/asm/io.h | 25 ++++++++++++++++++++-----
2 files changed, 20 insertions(+), 6 deletions(-)
--
2.35.1
On Mon, 21 Feb 2022, Jiaxun Yang wrote:
> This series clears the chaos of barrier misuse.
> In prepration of light weight barrier series.
What problem are you trying to solve here?
The MIPS port currently implements the semantics documented in
Documentation/memory-barriers.txt, in particular the "KERNEL I/O BARRIER
EFFECTS" section, with extra I/O barriers borrowed from the PowerPC port
for consistency for platform use, due to the weakly ordered architectural
MMIO model (implementations are allowed to have a stronger model in place
of course, and you are free to optimise for them with the respective
configurations).
Stating that we have a "chaos of barrier misuse" doesn't say anything
really in my opinion and isn't particularly constructive either. This
area is very fragile and you need to understand all the consequences when
trying to make any changes here and show it with your submission, that is
properly describe and justify your changes so that people are convinced
your changes are correct and good to make.
Maciej
Remove CPU_HAS_WB from Kconfig as all Loongson64 processors
don't have R3000 style write buffer. This is likely to be
a legacy of Loongson 2E's Bonito64.
Remove Loongson64 from war_io_reorder_wmb. Loongson64
never reorders uncached memory access as per user manual
of GS464, LS3A2000 and LS3A3000. It was intruduced due
to a misunderstanding of Store Fill Buffer.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/Kconfig | 1 -
arch/mips/include/asm/io.h | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 058446f01487..6d2e97342723 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -487,7 +487,6 @@ config MACH_LOONGSON64
select BOARD_SCACHE
select CSRC_R4K
select CEVT_R4K
- select CPU_HAS_WB
select FORCE_PCI
select ISA
select I8259
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 6f5c86d2bab4..065e1ab6401a 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -219,7 +219,7 @@ void iounmap(const volatile void __iomem *addr);
#define ioremap_wc(offset, size) \
ioremap_prot((offset), (size), boot_cpu_data.writecombine)
-#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_CPU_LOONGSON64)
+#if defined(CONFIG_CPU_CAVIUM_OCTEON)
#define war_io_reorder_wmb() wmb()
#else
#define war_io_reorder_wmb() barrier()
--
2.35.1
So we can share understanding of those barriers with other archs
and hopefully one day we will be able to switch asm-generic.
As mmiowb_set_pending is unimplemented on MIPS, __io_aw currently
does nothing, but it need to be implemented later.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/include/asm/io.h | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 065e1ab6401a..8a148277d9e6 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -225,6 +225,17 @@ void iounmap(const volatile void __iomem *addr);
#define war_io_reorder_wmb() barrier()
#endif
+#define __io_br() mb()
+
+/* prevent prefetching of coherent DMA data ahead of a dma-complete */
+#define __io_ar(v) rmb()
+
+/* flush writes to coherent DMA data before possibly triggering a DMA read */
+#define __io_bw() wmb()
+
+/* serialize device access against a spin_unlock, usually handled there. */
+#define __io_aw() do { } while (0)
+
#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, barrier, relax, irq) \
\
static inline void pfx##write##bwlq(type val, \
@@ -234,7 +245,7 @@ static inline void pfx##write##bwlq(type val, \
type __val; \
\
if (barrier) \
- iobarrier_rw(); \
+ __io_bw(); \
else \
war_io_reorder_wmb(); \
\
@@ -265,6 +276,7 @@ static inline void pfx##write##bwlq(type val, \
local_irq_restore(__flags); \
} else \
BUG(); \
+ __io_aw(); \
} \
\
static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
@@ -275,7 +287,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
\
if (barrier) \
- iobarrier_rw(); \
+ __io_br(); \
\
if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
__val = *__mem; \
@@ -300,9 +312,8 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
BUG(); \
} \
\
- /* prevent prefetching of coherent DMA data prematurely */ \
if (!relax) \
- rmb(); \
+ io_ar(__val); \
return pfx##ioswab##bwlq(__mem, __val); \
}
--
2.35.1