Linus,
The following changes since commit a188339ca5a396acc588e5851ed7e19f66b0ebd9:
Linux 5.2-rc1 (2019-05-19 15:47:09 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-v5.2/fixes-rc6
for you to fetch changes up to 259931fd3b96e4386b361b7f80c1d89b266234c8:
riscv: remove unused barrier defines (2019-06-17 07:09:43 -0700)
----------------------------------------------------------------
RISC-V patches for v5.2-rc6
This tag contains fixes, defconfig, and DT data changes for the v5.2-rc
series. The fixes are relatively straightforward:
- Addition of a TLB fence in the vmalloc_fault path, so the CPU doesn't
enter an infinite page fault loop;
- Readdition of the pm_power_off export, so device drivers that
reassign it can now be built as modules;
- A udelay() fix for RV32, fixing a miscomputation of the delay time;
- Removal of deprecated smp_mb__*() barriers.
The tag also adds initial DT data infrastructure for arch/riscv, along
with initial data for the SiFive FU540-C000 SoC and the corresponding
HiFive Unleashed board.
We also update the RV64 defconfig to include some core drivers for the
FU540 in the build.
----------------------------------------------------------------
Andreas Schwab (1):
riscv: export pm_power_off again
Kevin Hilman (1):
RISC-V: defconfig: enable clocks, serial console
Nick Hu (1):
riscv: Fix udelay in RV32.
Paul Walmsley (5):
arch: riscv: add support for building DTB files from DT source data
dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540
dt-bindings: riscv: convert cpu binding to json-schema
riscv: dts: add initial support for the SiFive FU540-C000 SoC
riscv: dts: add initial board data for the SiFive HiFive Unleashed
Rolf Eike Beer (1):
riscv: remove unused barrier defines
ShihPo Hung (1):
riscv: mm: synchronize MMU after pte change
Documentation/devicetree/bindings/riscv/cpus.yaml | 168 ++++++++++++++++
.../devicetree/bindings/riscv/sifive.yaml | 25 +++
MAINTAINERS | 9 +
arch/riscv/boot/dts/Makefile | 2 +
arch/riscv/boot/dts/sifive/Makefile | 2 +
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 215 +++++++++++++++++++++
.../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 65 +++++++
arch/riscv/configs/defconfig | 4 +
arch/riscv/include/asm/bitops.h | 5 -
arch/riscv/kernel/reset.c | 1 +
arch/riscv/lib/delay.c | 2 +-
arch/riscv/mm/fault.c | 13 ++
12 files changed, 505 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/riscv/cpus.yaml
create mode 100644 Documentation/devicetree/bindings/riscv/sifive.yaml
create mode 100644 arch/riscv/boot/dts/Makefile
create mode 100644 arch/riscv/boot/dts/sifive/Makefile
create mode 100644 arch/riscv/boot/dts/sifive/fu540-c000.dtsi
create mode 100644 arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
The pull request you sent on Mon, 17 Jun 2019 08:54:30 -0700 (PDT):
> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv-for-v5.2/fixes-rc6
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/eb7c825bf74755a9ea975b7a463c6d13ffa7f447
Thank you!
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