Linus,
The following changes since commit 6fbc7275c7a9ba97877050335f290341a1fd8dbf:
Linux 5.2-rc7 (2019-06-30 11:25:36 +0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv/for-v5.3-rc1
for you to fetch changes up to 2d69fbf3d01a5b71e98137e2406d4087960c512e:
riscv: fix build break after macro-to-function conversion in generic cacheflush.h (2019-07-18 08:16:56 -0700)
----------------------------------------------------------------
RISC-V updates for v5.3
- Hugepage support
- "Image" header support for RISC-V kernel binaries, compatible with
the current ARM64 "Image" header
- Initial page table setup now split into two stages
- CONFIG_SOC support (starting with SiFive SoCs)
- Avoid reserving memory between RAM start and the kernel in setup_bootmem()
- Enable high-res timers and dynamic tick in the RV64 defconfig
- Remove long-deprecated gate area stubs
- MAINTAINERS updates to switch to the newly-created shared RISC-V git
tree, and to fix a get_maintainers.pl issue for patches involving
SiFive E-mail addresses
Also, one integration fix to resolve a build problem introduced during
in the v5.3-rc1 merge window:
- Fix build break after macro-to-function conversion in
asm-generic/cacheflush.h
----------------------------------------------------------------
Alexandre Ghiti (2):
x86, arm64: Move ARCH_WANT_HUGE_PMD_SHARE config in arch/Kconfig
riscv: Introduce huge page support for 32/64bit kernel
Andy Lutomirski (1):
riscv: Remove gate area stubs
Anup Patel (3):
RISC-V: defconfig: Enable NO_HZ_IDLE and HIGH_RES_TIMERS
RISC-V: Fix memory reservation in setup_bootmem()
RISC-V: Setup initial page tables in two stages
Atish Patra (1):
RISC-V: Add an Image header that boot loader can parse.
Christoph Hellwig (1):
riscv: remove free_initrd_mem
Loys Ollivier (3):
arch: riscv: add config option for building SiFive's SoC resource
riscv: select SiFive platform drivers with SOC_SIFIVE
riscv: defconfig: enable SOC_SIFIVE
Paul Walmsley (3):
MAINTAINERS: don't automatically patches involving SiFive to the linux-riscv list
MAINTAINERS: change the arch/riscv git tree to the new shared tree
riscv: fix build break after macro-to-function conversion in generic cacheflush.h
Yash Shah (1):
riscv: ccache: Remove unused variable
Documentation/riscv/boot-image-header.txt | 50 +++++
MAINTAINERS | 4 +-
arch/Kconfig | 3 +
arch/arm64/Kconfig | 2 +-
arch/riscv/Kconfig | 10 +
arch/riscv/Kconfig.socs | 13 ++
arch/riscv/boot/dts/sifive/Makefile | 2 +-
arch/riscv/configs/defconfig | 8 +-
arch/riscv/configs/rv32_defconfig | 2 +
arch/riscv/include/asm/cacheflush.h | 63 +++++-
arch/riscv/include/asm/fixmap.h | 5 +
arch/riscv/include/asm/hugetlb.h | 18 ++
arch/riscv/include/asm/image.h | 65 ++++++
arch/riscv/include/asm/page.h | 14 +-
arch/riscv/include/asm/pgtable-64.h | 5 +
arch/riscv/include/asm/pgtable.h | 16 +-
arch/riscv/kernel/head.S | 49 ++++-
arch/riscv/kernel/setup.c | 6 +-
arch/riscv/kernel/vdso.c | 19 --
arch/riscv/mm/Makefile | 2 +
arch/riscv/mm/hugetlbpage.c | 44 ++++
arch/riscv/mm/init.c | 326 ++++++++++++++++++++++++------
arch/riscv/mm/sifive_l2_cache.c | 11 +-
arch/x86/Kconfig | 4 +-
24 files changed, 620 insertions(+), 121 deletions(-)
create mode 100644 Documentation/riscv/boot-image-header.txt
create mode 100644 arch/riscv/Kconfig.socs
create mode 100644 arch/riscv/include/asm/hugetlb.h
create mode 100644 arch/riscv/include/asm/image.h
create mode 100644 arch/riscv/mm/hugetlbpage.c
The pull request you sent on Thu, 18 Jul 2019 12:07:36 -0700 (PDT):
> git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git tags/riscv/for-v5.3-rc1
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/0570bc8b7c9b41deba6f61ac218922e7168ad648
Thank you!
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