From: Matthew Gerlach <[email protected]>
This patch set adds a device tree for the Hard Processor System (HPS)
on an Agilex based Intel n6000 board.
Patch 1 defines the device tree binding for the HPS Copy Engine IP
used to copy a bootable image from host memory to HPS DDR.
Patch 2 defines the binding for the Intel n6000 board itself.
Patch 3 adds the device tree for the n6000 board.
Changelog v3 -> v4:
- move binding yaml from soc to soc/intel
Changelog v2 -> v3:
- remove unused label
- move from misc to soc
- remove 0x from #address-cells/#size-cells values
- change hps_cp_eng@0 to dma-controller@0
- remote inaccurate 'items:' tag
- added Acked-by
- add unit number to memory node
- remove spi node with unaccepted compatible value
Changelog v1 -> v2:
- add dt binding for copy enging
- add dt binding for n6000 board
- fix copy engine node name
- fix compatible field for copy engine
- remove redundant status field
- add compatibility field for the board
- fix SPDX
- fix how osc1 clock frequency is set
Matthew Gerlach (3):
dt-bindings: soc: add bindings for Intel HPS Copy Engine
dt-bindings: intel: add binding for Intel n6000
arm64: dts: intel: add device tree for n6000
.../bindings/arm/intel,socfpga.yaml | 1 +
.../soc/intel/intel,hps-copy-engine.yaml | 51 ++++++++++++++
arch/arm64/boot/dts/intel/Makefile | 3 +-
.../boot/dts/intel/socfpga_agilex_n6000.dts | 66 +++++++++++++++++++
4 files changed, 120 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
--
2.25.1
From: Matthew Gerlach <[email protected]>
Add device tree bindings documentation for the Intel Hard
Processor System (HPS) Copy Engine.
Signed-off-by: Matthew Gerlach <[email protected]>
---
v4:
- move from soc to soc/intel/
v3:
- remove unused label
- move from misc to soc
- remove 0x from #address-cells/#size-cells values
- change hps_cp_eng@0 to dma-controller@0
- remote inaccurate 'items:' tag
---
.../soc/intel/intel,hps-copy-engine.yaml | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
diff --git a/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml b/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
new file mode 100644
index 000000000000..8634865015cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (C) 2022, Intel Corporation
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Intel HPS Copy Engine
+
+maintainers:
+ - Matthew Gerlach <[email protected]>
+
+description: |
+ The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy
+ a bootable image from host memory to HPS DDR. Additionally, there is a
+ register the HPS can use to indicate the state of booting the copied image as
+ well as a keep-a-live indication to the host.
+
+properties:
+ compatible:
+ const: intel,hps-copy-engine
+
+ '#dma-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ bus@80000000 {
+ compatible = "simple-bus";
+ reg = <0x80000000 0x60000000>,
+ <0xf9000000 0x00100000>;
+ reg-names = "axi_h2f", "axi_h2f_lw";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
+
+ dma-controller@0 {
+ compatible = "intel,hps-copy-engine";
+ reg = <0x00000000 0x00000000 0x00001000>;
+ #dma-cells = <1>;
+ };
+ };
--
2.25.1
From: Matthew Gerlach <[email protected]>
Add the binding string for the Agilex based Intel n6000 board.
Signed-off-by: Matthew Gerlach <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
---
v3:
- added Acked-by
---
Documentation/devicetree/bindings/arm/intel,socfpga.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
index 6e043459fcd5..61a454a40e87 100644
--- a/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
+++ b/Documentation/devicetree/bindings/arm/intel,socfpga.yaml
@@ -18,6 +18,7 @@ properties:
items:
- enum:
- intel,n5x-socdk
+ - intel,socfpga-agilex-n6000
- intel,socfpga-agilex-socdk
- const: intel,socfpga-agilex
--
2.25.1
From: Matthew Gerlach <[email protected]>
Add a device tree for the n6000 instantiation of Agilex
Hard Processor System (HPS).
Signed-off-by: Matthew Gerlach <[email protected]>
---
v3:
- add unit number to memory node
- remove unused label
- remove 0x from #address-cells/#size-cells values
- change hps_cp_eng@0 to dma-controller@0
- remove spi node with unaccepted compatible value
v2:
- fix copy engine node name
- fix compatible field for copy engine
- remove redundant status field
- add compatibility field for the board
- fix SPDX
- fix how osc1 clock frequency is set
---
arch/arm64/boot/dts/intel/Makefile | 3 +-
.../boot/dts/intel/socfpga_agilex_n6000.dts | 66 +++++++++++++++++++
2 files changed, 68 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile
index 0b5477442263..c2a723838344 100644
--- a/arch/arm64/boot/dts/intel/Makefile
+++ b/arch/arm64/boot/dts/intel/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
-dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_socdk.dtb \
+dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
+ socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_nand.dtb \
socfpga_n5x_socdk.dtb
dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
new file mode 100644
index 000000000000..6231a69204b1
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021-2022, Intel Corporation
+ */
+#include "socfpga_agilex.dtsi"
+
+/ {
+ model = "SoCFPGA Agilex n6000";
+ compatible = "intel,socfpga-agilex-n6000", "intel,socfpga-agilex";
+
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
+
+ soc {
+ bus@80000000 {
+ compatible = "simple-bus";
+ reg = <0x80000000 0x60000000>,
+ <0xf9000000 0x00100000>;
+ reg-names = "axi_h2f", "axi_h2f_lw";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
+
+ dma-controller@0 {
+ compatible = "intel,hps-copy-engine";
+ reg = <0x00000000 0x00000000 0x00001000>;
+ #dma-cells = <1>;
+ };
+ };
+ };
+};
+
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&fpga_mgr {
+ status = "disabled";
+};
--
2.25.1
On 08/05/2022 16:26, [email protected] wrote:
> From: Matthew Gerlach <[email protected]>
>
> Add device tree bindings documentation for the Intel Hard
> Processor System (HPS) Copy Engine.
>
> Signed-off-by: Matthew Gerlach <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 08/05/2022 16:26, [email protected] wrote:
> From: Matthew Gerlach <[email protected]>
>
> Add a device tree for the n6000 instantiation of Agilex
> Hard Processor System (HPS).
>
> Signed-off-by: Matthew Gerlach <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Mon, 9 May 2022, Krzysztof Kozlowski wrote:
> On 08/05/2022 16:26, [email protected] wrote:
>> From: Matthew Gerlach <[email protected]>
>>
>> Add a device tree for the n6000 instantiation of Agilex
>> Hard Processor System (HPS).
>>
>> Signed-off-by: Matthew Gerlach <[email protected]>
>
>
> Acked-by: Krzysztof Kozlowski <[email protected]>
Hi Kryzysztof,
Thanks for the Acked-by. I will add your tag to a v5 patch set
submission.
Matthew
>
>
> Best regards,
> Krzysztof
>
On Mon, 9 May 2022, Krzysztof Kozlowski wrote:
> On 08/05/2022 16:26, [email protected] wrote:
>> From: Matthew Gerlach <[email protected]>
>>
>> Add device tree bindings documentation for the Intel Hard
>> Processor System (HPS) Copy Engine.
>>
>> Signed-off-by: Matthew Gerlach <[email protected]>
>
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
Hi Krzysztof,
Thank you for the review. I will add your tag and submit a v5 patchset.
Matthew
>
>
> Best regards,
> Krzysztof
>
On Tue, May 10, 2022 at 07:17:59AM -0700, [email protected] wrote:
>
>
> On Mon, 9 May 2022, Krzysztof Kozlowski wrote:
>
> > On 08/05/2022 16:26, [email protected] wrote:
> > > From: Matthew Gerlach <[email protected]>
> > >
> > > Add a device tree for the n6000 instantiation of Agilex
> > > Hard Processor System (HPS).
> > >
> > > Signed-off-by: Matthew Gerlach <[email protected]>
> >
> >
> > Acked-by: Krzysztof Kozlowski <[email protected]>
>
> Hi Kryzysztof,
>
> Thanks for the Acked-by. I will add your tag to a v5 patch set submission.
Before I commented, why would there be a v5? TBC, you don't need to
resend just to add tags. The tools (b4, PW) do this for us. But when you
do send another version you need to add the tags as the tools don't look
at prior versions.
Rob
On Sun, May 08, 2022 at 07:26:22AM -0700, [email protected] wrote:
> From: Matthew Gerlach <[email protected]>
>
> Add device tree bindings documentation for the Intel Hard
> Processor System (HPS) Copy Engine.
>
> Signed-off-by: Matthew Gerlach <[email protected]>
> ---
> v4:
> - move from soc to soc/intel/
>
> v3:
> - remove unused label
> - move from misc to soc
> - remove 0x from #address-cells/#size-cells values
> - change hps_cp_eng@0 to dma-controller@0
> - remote inaccurate 'items:' tag
> ---
> .../soc/intel/intel,hps-copy-engine.yaml | 51 +++++++++++++++++++
Also, this should go under bindings/dma/
> 1 file changed, 51 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
On Tue, 10 May 2022, Rob Herring wrote:
> On Tue, May 10, 2022 at 07:17:59AM -0700, [email protected] wrote:
>>
>>
>> On Mon, 9 May 2022, Krzysztof Kozlowski wrote:
>>
>>> On 08/05/2022 16:26, [email protected] wrote:
>>>> From: Matthew Gerlach <[email protected]>
>>>>
>>>> Add a device tree for the n6000 instantiation of Agilex
>>>> Hard Processor System (HPS).
>>>>
>>>> Signed-off-by: Matthew Gerlach <[email protected]>
>>>
>>>
>>> Acked-by: Krzysztof Kozlowski <[email protected]>
>>
>> Hi Kryzysztof,
>>
>> Thanks for the Acked-by. I will add your tag to a v5 patch set submission.
>
> Before I commented, why would there be a v5? TBC, you don't need to
> resend just to add tags. The tools (b4, PW) do this for us. But when you
> do send another version you need to add the tags as the tools don't look
> at prior versions.
Thank you for the clarification.
Matthew
>
> Rob
>
On Sun, May 08, 2022 at 07:26:22AM -0700, [email protected] wrote:
> From: Matthew Gerlach <[email protected]>
>
> Add device tree bindings documentation for the Intel Hard
> Processor System (HPS) Copy Engine.
>
> Signed-off-by: Matthew Gerlach <[email protected]>
> ---
> v4:
> - move from soc to soc/intel/
>
> v3:
> - remove unused label
> - move from misc to soc
> - remove 0x from #address-cells/#size-cells values
> - change hps_cp_eng@0 to dma-controller@0
> - remote inaccurate 'items:' tag
> ---
> .../soc/intel/intel,hps-copy-engine.yaml | 51 +++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
>
> diff --git a/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml b/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
> new file mode 100644
> index 000000000000..8634865015cd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
> @@ -0,0 +1,51 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright (C) 2022, Intel Corporation
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Intel HPS Copy Engine
> +
> +maintainers:
> + - Matthew Gerlach <[email protected]>
> +
> +description: |
> + The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy
> + a bootable image from host memory to HPS DDR. Additionally, there is a
> + register the HPS can use to indicate the state of booting the copied image as
> + well as a keep-a-live indication to the host.
> +
> +properties:
> + compatible:
> + const: intel,hps-copy-engine
> +
> + '#dma-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + bus@80000000 {
> + compatible = "simple-bus";
> + reg = <0x80000000 0x60000000>,
> + <0xf9000000 0x00100000>;
> + reg-names = "axi_h2f", "axi_h2f_lw";
A simple-bus doesn't have regs because it is simple. If you have
registers, then you need a specific compatible. You can have
'simple-bus' as a fallback if the bus is completely setup by firmware
and the OS never needs to configure/manage it.
It also looks odd that ranges only has 4K of bus space and the bus
registers are 1.5GB of space.
That's all kind of outside of the scope of this binding and you should
just drop that part.
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
> +
> + dma-controller@0 {
> + compatible = "intel,hps-copy-engine";
> + reg = <0x00000000 0x00000000 0x00001000>;
> + #dma-cells = <1>;
> + };
> + };
> --
> 2.25.1
>
>
On Tue, 10 May 2022, Rob Herring wrote:
> On Sun, May 08, 2022 at 07:26:22AM -0700, [email protected] wrote:
>> From: Matthew Gerlach <[email protected]>
>>
>> Add device tree bindings documentation for the Intel Hard
>> Processor System (HPS) Copy Engine.
>>
>> Signed-off-by: Matthew Gerlach <[email protected]>
>> ---
>> v4:
>> - move from soc to soc/intel/
>>
>> v3:
>> - remove unused label
>> - move from misc to soc
>> - remove 0x from #address-cells/#size-cells values
>> - change hps_cp_eng@0 to dma-controller@0
>> - remote inaccurate 'items:' tag
>> ---
>> .../soc/intel/intel,hps-copy-engine.yaml | 51 +++++++++++++++++++
>
> Also, this should go under bindings/dma/
I will move .../soc/intel/intel,hps-copy-engine.yaml to
.../dma/intel,hps-copy-engine.yaml unless you think I should start a intel
subdirectory of bindings/dma.
>
>> 1 file changed, 51 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
>
On Tue, 10 May 2022, Rob Herring wrote:
> On Sun, May 08, 2022 at 07:26:22AM -0700, [email protected] wrote:
>> From: Matthew Gerlach <[email protected]>
>>
>> Add device tree bindings documentation for the Intel Hard
>> Processor System (HPS) Copy Engine.
>>
>> Signed-off-by: Matthew Gerlach <[email protected]>
>> ---
>> v4:
>> - move from soc to soc/intel/
>>
>> v3:
>> - remove unused label
>> - move from misc to soc
>> - remove 0x from #address-cells/#size-cells values
>> - change hps_cp_eng@0 to dma-controller@0
>> - remote inaccurate 'items:' tag
>> ---
>> .../soc/intel/intel,hps-copy-engine.yaml | 51 +++++++++++++++++++
>> 1 file changed, 51 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml b/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
>> new file mode 100644
>> index 000000000000..8634865015cd
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
>> @@ -0,0 +1,51 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +# Copyright (C) 2022, Intel Corporation
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: Intel HPS Copy Engine
>> +
>> +maintainers:
>> + - Matthew Gerlach <[email protected]>
>> +
>> +description: |
>> + The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy
>> + a bootable image from host memory to HPS DDR. Additionally, there is a
>> + register the HPS can use to indicate the state of booting the copied image as
>> + well as a keep-a-live indication to the host.
>> +
>> +properties:
>> + compatible:
>> + const: intel,hps-copy-engine
>> +
>> + '#dma-cells':
>> + const: 1
>> +
>> + reg:
>> + maxItems: 1
>> +
>> +required:
>> + - compatible
>> + - reg
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + bus@80000000 {
>> + compatible = "simple-bus";
>> + reg = <0x80000000 0x60000000>,
>> + <0xf9000000 0x00100000>;
>> + reg-names = "axi_h2f", "axi_h2f_lw";
>
> A simple-bus doesn't have regs because it is simple. If you have
> registers, then you need a specific compatible. You can have
> 'simple-bus' as a fallback if the bus is completely setup by firmware
> and the OS never needs to configure/manage it.
The hardware I'm trying to describe above is the connection from the
HPS/SOC to the FPGA. There are two ranges of physical addresses with this
connection referred to as the "HPS to FPGA bridge" and the "Lightweight
HPS to FPGA bridge". Device tree subnodes of bus@80000000 are IP
blocks in the FPGA. The IP blocks may be connected to one or both of the
physical address ranges. Since these physical address ranges are not registers
of the bus@80000000, the field names, reg and reg-names, are probably
wrong. Should the reg field above really be ranges?
>
> It also looks odd that ranges only has 4K of bus space and the bus
> registers are 1.5GB of space.
The intent of the ranges field below is to show the ranges of actual
registers associated subnodes of bus@80000000. This is probably incorrect
as well.
>
> That's all kind of outside of the scope of this binding and you should
> just drop that part.
I agree that discussion of bus@80000000 is outside the scope of this
binding. I will resubmit this binding with only the dma-controller@0 node
as the example.
>
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> + ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
>> +
>> + dma-controller@0 {
>> + compatible = "intel,hps-copy-engine";
>> + reg = <0x00000000 0x00000000 0x00001000>;
>> + #dma-cells = <1>;
>> + };
>> + };
>> --
>> 2.25.1
>>
>>
>
On 5/8/22 09:26, [email protected] wrote:
> From: Matthew Gerlach <[email protected]>
>
> This patch set adds a device tree for the Hard Processor System (HPS)
> on an Agilex based Intel n6000 board.
>
> Patch 1 defines the device tree binding for the HPS Copy Engine IP
> used to copy a bootable image from host memory to HPS DDR.
>
> Patch 2 defines the binding for the Intel n6000 board itself.
>
> Patch 3 adds the device tree for the n6000 board.
>
> Changelog v3 -> v4:
> - move binding yaml from soc to soc/intel
>
> Changelog v2 -> v3:
> - remove unused label
> - move from misc to soc
> - remove 0x from #address-cells/#size-cells values
> - change hps_cp_eng@0 to dma-controller@0
> - remote inaccurate 'items:' tag
> - added Acked-by
> - add unit number to memory node
> - remove spi node with unaccepted compatible value
>
> Changelog v1 -> v2:
> - add dt binding for copy enging
> - add dt binding for n6000 board
> - fix copy engine node name
> - fix compatible field for copy engine
> - remove redundant status field
> - add compatibility field for the board
> - fix SPDX
> - fix how osc1 clock frequency is set
>
> Matthew Gerlach (3):
> dt-bindings: soc: add bindings for Intel HPS Copy Engine
> dt-bindings: intel: add binding for Intel n6000
> arm64: dts: intel: add device tree for n6000
>
> .../bindings/arm/intel,socfpga.yaml | 1 +
> .../soc/intel/intel,hps-copy-engine.yaml | 51 ++++++++++++++
> arch/arm64/boot/dts/intel/Makefile | 3 +-
> .../boot/dts/intel/socfpga_agilex_n6000.dts | 66 +++++++++++++++++++
> 4 files changed, 120 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
> create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
>
Applied!
Thanks,
Dinh
On Thu, 12 May 2022, Dinh Nguyen wrote:
>
>
> On 5/8/22 09:26, [email protected] wrote:
>> From: Matthew Gerlach <[email protected]>
>>
>> This patch set adds a device tree for the Hard Processor System (HPS)
>> on an Agilex based Intel n6000 board.
>>
>> Patch 1 defines the device tree binding for the HPS Copy Engine IP
>> used to copy a bootable image from host memory to HPS DDR.
>>
>> Patch 2 defines the binding for the Intel n6000 board itself.
>>
>> Patch 3 adds the device tree for the n6000 board.
>>
>> Changelog v3 -> v4:
>> - move binding yaml from soc to soc/intel
>>
>> Changelog v2 -> v3:
>> - remove unused label
>> - move from misc to soc
>> - remove 0x from #address-cells/#size-cells values
>> - change hps_cp_eng@0 to dma-controller@0
>> - remote inaccurate 'items:' tag
>> - added Acked-by
>> - add unit number to memory node
>> - remove spi node with unaccepted compatible value
>>
>> Changelog v1 -> v2:
>> - add dt binding for copy enging
>> - add dt binding for n6000 board
>> - fix copy engine node name
>> - fix compatible field for copy engine
>> - remove redundant status field
>> - add compatibility field for the board
>> - fix SPDX
>> - fix how osc1 clock frequency is set
>>
>> Matthew Gerlach (3):
>> dt-bindings: soc: add bindings for Intel HPS Copy Engine
>> dt-bindings: intel: add binding for Intel n6000
>> arm64: dts: intel: add device tree for n6000
>>
>> .../bindings/arm/intel,socfpga.yaml | 1 +
>> .../soc/intel/intel,hps-copy-engine.yaml | 51 ++++++++++++++
>> arch/arm64/boot/dts/intel/Makefile | 3 +-
>> .../boot/dts/intel/socfpga_agilex_n6000.dts | 66 +++++++++++++++++++
>> 4 files changed, 120 insertions(+), 1 deletion(-)
>> create mode 100644
>> Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
>> create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
>>
>
> Applied!
Hi Dinh,
Rob Herring suggested I move
Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml to
Documentation/devicetree/bindings/dma/intel,hps-copy-engine.yaml as well
as some cleanup to the yaml. Rob also had some concerns about the h2f(lw)
bus that I was considering some changes. Should I send a v6 patch set or
a new patchset on top of the v4 to address Rob's concerns, or do you have
some other suggestion?
Thanks,
Matthew
> Thanks,
>
> Dinh
>
On Tue, May 10, 2022 at 03:23:23PM -0700, [email protected] wrote:
>
>
> On Tue, 10 May 2022, Rob Herring wrote:
>
> > On Sun, May 08, 2022 at 07:26:22AM -0700, [email protected] wrote:
> > > From: Matthew Gerlach <[email protected]>
> > >
> > > Add device tree bindings documentation for the Intel Hard
> > > Processor System (HPS) Copy Engine.
> > >
> > > Signed-off-by: Matthew Gerlach <[email protected]>
> > > ---
> > > v4:
> > > - move from soc to soc/intel/
> > >
> > > v3:
> > > - remove unused label
> > > - move from misc to soc
> > > - remove 0x from #address-cells/#size-cells values
> > > - change hps_cp_eng@0 to dma-controller@0
> > > - remote inaccurate 'items:' tag
> > > ---
> > > .../soc/intel/intel,hps-copy-engine.yaml | 51 +++++++++++++++++++
> > > 1 file changed, 51 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml b/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
> > > new file mode 100644
> > > index 000000000000..8634865015cd
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
> > > @@ -0,0 +1,51 @@
> > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > > +# Copyright (C) 2022, Intel Corporation
> > > +%YAML 1.2
> > > +---
> > > +$id: "http://devicetree.org/schemas/soc/intel/intel,hps-copy-engine.yaml#"
> > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > > +
> > > +title: Intel HPS Copy Engine
> > > +
> > > +maintainers:
> > > + - Matthew Gerlach <[email protected]>
> > > +
> > > +description: |
> > > + The Intel Hard Processor System (HPS) Copy Engine is an IP block used to copy
> > > + a bootable image from host memory to HPS DDR. Additionally, there is a
> > > + register the HPS can use to indicate the state of booting the copied image as
> > > + well as a keep-a-live indication to the host.
> > > +
> > > +properties:
> > > + compatible:
> > > + const: intel,hps-copy-engine
> > > +
> > > + '#dma-cells':
> > > + const: 1
> > > +
> > > + reg:
> > > + maxItems: 1
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + bus@80000000 {
> > > + compatible = "simple-bus";
> > > + reg = <0x80000000 0x60000000>,
> > > + <0xf9000000 0x00100000>;
> > > + reg-names = "axi_h2f", "axi_h2f_lw";
> >
> > A simple-bus doesn't have regs because it is simple. If you have
> > registers, then you need a specific compatible. You can have
> > 'simple-bus' as a fallback if the bus is completely setup by firmware
> > and the OS never needs to configure/manage it.
>
> The hardware I'm trying to describe above is the connection from the HPS/SOC
> to the FPGA. There are two ranges of physical addresses with this
> connection referred to as the "HPS to FPGA bridge" and the "Lightweight HPS
> to FPGA bridge". Device tree subnodes of bus@80000000 are IP blocks in the
> FPGA. The IP blocks may be connected to one or both of the
> physical address ranges. Since these physical address ranges are not registers
> of the bus@80000000, the field names, reg and reg-names, are probably wrong.
> Should the reg field above really be ranges?
Yes, sound likes it should be.
Rob