LinuxLists.cc - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:9191:2-15: alloc with no test, possible model on line 9296 (fwd)

2024-01-30 07:23:46

Subject: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:9191:2-15: alloc with no test, possible model on line 9296 (fwd)

It would be good
julia

---------- Forwarded Date: Tue, 30 Jan From: kernel test To: BCC: :::::: branch date: 22 hours ago
:::::: commit date: 11 days ago
config: x86_64-randconfig-104-20240129 compiler: gcc-12
If you fix the issue the same patch/commit), | Reported-by: kernel | Reported-by: Julia | Closes: to make a NULL test for the kzalloc on line 9191.
message ----------
2024 06:48:05 +0800
robot <[email protected]>
ail-protection#f9969cd4929b8c90959db995908a8d8ad79590978c81d79d9c8f">[email protected]
ail-protection#74181f04341d1a0011185a171b19">[email protected], Julia Lawall <[email protected]>
md/display/amdgpu_dm/amdgpu_dm.c:9191:2-15: alloc with
model on line 9296
mail-protection#462a2d36062f2832232a6825292b">[email protected]
ail-protection#3c535911575e49555058115d50507c50554f484f1250555249441258594a">[email protected]
ail-protection#3f5356514a4712545a4d515a537f49585a4d11545a4d515a5311504d58">[email protected]
<[email protected]>
<[email protected]>
href="/cdn-cgi/l/email-protection#2e08425a154f424b5600465b40496e4f434a004d414308495a15"><[email protected]>
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git">https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
03f326a746ac4d429c1dd3
1bc670fc4ea5f034ed062c drm/amd/display: Drop 'acrtc' and add 'new_crtc_state' NULL check for writeback requests.
(https://download.01.org/0day-ci/archive/20240130/[email protected]/config)
(Debian 12.2.0-14) 12.2.0
in a separate patch/commit (i.e. not just a new version of
kindly add following tags
test robot <[email protected]>
Lawall <[email protected]>
//lore.kernel.org/r/202401300629.ICnCt983-lkp@intel.com/">https://lore.kernel.org/r/[email protected]/
ones prefixed by >>)
md/display/amdgpu_dm/amdgpu_dm.c:9191:2-15: alloc with no test, possible model on line 9296
amd/display/amdgpu_dm/amdgpu_dm.c
2023-12-01 8952
2023-06-27 8953 /**
2023-06-27 8954 * amdgpu_dm_atomic_commit_tail() - AMDgpu DM's commit tail implementation.
2023-06-27 8955 * @state: The atomic state to commit
2023-06-27 8956 *
2023-06-27 8957 * This will tell DC to commit the constructed DC state from atomic_check,
2023-06-27 8958 * programming the hardware. Any failures here implies a hardware failure, since
2023-06-27 8959 * atomic check should have filtered anything non-kosher.
2023-06-27 8960 */
2023-06-27 8961 static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
2023-06-27 8962 {
2023-06-27 8963 struct drm_device *dev = state->dev;
2023-06-27 8964 struct amdgpu_device *adev = drm_to_adev(dev);
2023-06-27 8965 struct amdgpu_display_manager *dm = &adev->dm;
2023-06-27 8966 struct dm_atomic_state *dm_state;
2023-06-27 8967 struct dc_state *dc_state = NULL;
2023-06-27 8968 u32 i, j;
2023-06-27 8969 struct drm_crtc *crtc;
2023-06-27 8970 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
2023-06-27 8971 unsigned long flags;
2023-06-27 8972 bool wait_for_vblank = true;
2023-06-27 8973 struct drm_connector *connector;
2023-06-27 8974 struct drm_connector_state *old_con_state, *new_con_state;
2023-06-27 8975 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
2023-06-27 8976 int crtc_disable_count = 0;
2023-06-27 8977
2023-06-27 8978 trace_amdgpu_dm_atomic_commit_tail_begin(state);
2023-06-27 8979
2023-08-03 8980 if (dm->dc->caps.ips_support) {
2023-08-03 8981 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
2023-08-03 8982 if (new_con_state->crtc &&
2023-08-03 8983 new_con_state->crtc->state->active &&
2023-08-03 8984 drm_atomic_crtc_needs_modeset(new_con_state->crtc->state)) {
2023-12-04 8985 dc_dmub_srv_apply_idle_power_optimizations(dm->dc, false);
2023-08-03 8986 break;
2023-08-03 8987 }
2023-08-03 8988 }
2023-08-03 8989 }
2023-08-03 8990
2023-06-27 8991 drm_atomic_helper_update_legacy_modeset_state(dev, state);
2023-06-27 8992 drm_dp_mst_atomic_wait_for_dependencies(state);
2023-06-27 8993
2023-06-27 8994 dm_state = dm_atomic_get_new_state(state);
2023-06-27 8995 if (dm_state && dm_state->context) {
2023-06-27 8996 dc_state = dm_state->context;
2023-06-27 8997 amdgpu_dm_commit_streams(state, dc_state);
2023-06-27 8998 }
2023-06-27 8999
2019-09-16 9000 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
2019-09-16 9001 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
2019-09-16 9002 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
2023-12-01 9003 struct amdgpu_dm_connector *aconnector;
2023-12-01 9004
2023-12-01 9005 if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK)
2023-12-01 9006 continue;
2023-12-01 9007
2023-12-01 9008 aconnector = to_amdgpu_dm_connector(connector);
2019-09-16 9009
2023-03-28 9010 if (!adev->dm.hdcp_workqueue)
2023-03-28 9011 continue;
2023-03-28 9012
2022-11-15 9013 pr_debug("[HDCP_DM] -------------- i : %x ----------\n", i);
2022-11-15 9014
2022-11-15 9015 if (!connector)
2022-11-15 9016 continue;
2022-11-15 9017
2022-11-15 9018 pr_debug("[HDCP_DM] connector->index: %x connect_status: %x dpms: %x\n",
2022-11-15 9019 connector->index, connector->status, connector->dpms);
2022-11-15 9020 pr_debug("[HDCP_DM] state protection old: %x new: %x\n",
2022-11-15 9021 old_con_state->content_protection, new_con_state->content_protection);
2022-11-15 9022
2022-11-15 9023 if (aconnector->dc_sink) {
2022-11-15 9024 if (aconnector->dc_sink->sink_signal != SIGNAL_TYPE_VIRTUAL &&
2022-11-15 9025 aconnector->dc_sink->sink_signal != SIGNAL_TYPE_NONE) {
2022-11-15 9026 pr_debug("[HDCP_DM] pipe_ctx dispname=%s\n",
2022-11-15 9027 aconnector->dc_sink->edid_caps.display_name);
2022-11-15 9028 }
2022-11-15 9029 }
2022-11-15 9030
2019-09-16 9031 new_crtc_state = NULL;
2022-11-15 9032 old_crtc_state = NULL;
2019-09-16 9033
2022-11-15 9034 if (acrtc) {
2019-09-16 9035 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
2022-11-15 9036 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
2022-11-15 9037 }
2022-11-15 9038
2022-11-15 9039 if (old_crtc_state)
2022-11-15 9040 pr_debug("old crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
2022-11-15 9041 old_crtc_state->enable,
2022-11-15 9042 old_crtc_state->active,
2022-11-15 9043 old_crtc_state->mode_changed,
2022-11-15 9044 old_crtc_state->active_changed,
2022-11-15 9045 old_crtc_state->connectors_changed);
2022-11-15 9046
2022-11-15 9047 if (new_crtc_state)
2022-11-15 9048 pr_debug("NEW crtc en: %x a: %x m: %x a-chg: %x c-chg: %x\n",
2022-11-15 9049 new_crtc_state->enable,
2022-11-15 9050 new_crtc_state->active,
2022-11-15 9051 new_crtc_state->mode_changed,
2022-11-15 9052 new_crtc_state->active_changed,
2022-11-15 9053 new_crtc_state->connectors_changed);
2022-11-15 9054 }
2022-11-15 9055
2022-11-15 9056 for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
2022-11-15 9057 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
2022-11-15 9058 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
2022-11-15 9059 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
2022-11-15 9060
2023-03-28 9061 if (!adev->dm.hdcp_workqueue)
2023-03-28 9062 continue;
2023-03-28 9063
2022-11-15 9064 new_crtc_state = NULL;
2022-11-15 9065 old_crtc_state = NULL;
2022-11-15 9066
2022-11-15 9067 if (acrtc) {
2022-11-15 9068 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
2022-11-15 9069 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
2022-11-15 9070 }
2019-09-16 9071
2019-09-16 9072 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2019-09-16 9073
2019-09-16 9074 if (dm_new_crtc_state && dm_new_crtc_state->stream == NULL &&
2019-09-16 9075 connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
2019-09-16 9076 hdcp_reset_display(adev->dm.hdcp_workqueue, aconnector->dc_link->link_index);
2019-09-16 9077 new_con_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED;
2019-09-26 9078 dm_new_con_state->update_hdcp = true;
2019-09-16 9079 continue;
2019-09-16 9080 }
2019-09-16 9081
2022-11-15 9082 if (is_content_protection_different(new_crtc_state, old_crtc_state, new_con_state,
2022-11-15 9083 old_con_state, connector, adev->dm.hdcp_workqueue)) {
2022-11-15 9084 /* when display is unplugged from mst hub, connctor will
2022-11-15 9085 * be destroyed within dm_dp_mst_connector_destroy. connector
2022-11-15 9086 * hdcp perperties, like type, undesired, desired, enabled,
2022-11-15 9087 * will be lost. So, save hdcp properties into hdcp_work within
2022-11-15 9088 * amdgpu_dm_atomic_commit_tail. if the same display is
2022-11-15 9089 * plugged back with same display index, its hdcp properties
2022-11-15 9090 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
2022-11-15 9091 */
2022-11-15 9092
2022-11-15 9093 bool enable_encryption = false;
2022-11-15 9094
2022-11-15 9095 if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED)
2022-11-15 9096 enable_encryption = true;
2022-11-15 9097
2022-11-15 9098 if (aconnector->dc_link && aconnector->dc_sink &&
2022-11-15 9099 aconnector->dc_link->type == dc_connection_mst_branch) {
2022-11-15 9100 struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue;
2022-11-15 9101 struct hdcp_workqueue *hdcp_w =
2022-11-15 9102 &hdcp_work[aconnector->dc_link->link_index];
2022-11-15 9103
2022-11-15 9104 hdcp_w->hdcp_content_type[connector->index] =
2022-11-15 9105 new_con_state->hdcp_content_type;
2022-11-15 9106 hdcp_w->content_protection[connector->index] =
2022-11-15 9107 new_con_state->content_protection;
2022-11-15 9108 }
2022-11-15 9109
2022-11-15 9110 if (new_crtc_state && new_crtc_state->mode_changed &&
2022-11-15 9111 new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED)
2022-11-15 9112 enable_encryption = true;
2022-11-15 9113
2022-11-15 9114 DRM_INFO("[HDCP_DM] hdcp_update_display enable_encryption = %x\n", enable_encryption);
2022-11-15 9115
2019-08-28 9116 hdcp_update_display(
2019-08-28 9117 adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector,
2022-11-15 9118 new_con_state->hdcp_content_type, enable_encryption);
2019-09-16 9119 }
2019-09-16 9120 }
2017-08-10 9121
2018-12-18 9122 /* Handle connector state changes */
2017-10-12 9123) for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) {
2017-10-12 9124) struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
2017-10-12 9125) struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state);
2017-10-12 9126) struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
2023-06-21 9127 struct dc_surface_update *dummy_updates;
2019-02-01 9128 struct dc_stream_update stream_update;
2019-05-28 9129 struct dc_info_packet hdr_packet;
2017-08-10 9130 struct dc_stream_status *status = NULL;
2019-05-28 9131 bool abm_changed, hdr_changed, scaling_changed;
2017-08-10 9132
2019-02-01 9133 memset(&stream_update, 0, sizeof(stream_update));
2019-02-01 9134
2018-03-15 9135 if (acrtc) {
2017-10-12 9136) new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
2018-03-15 9137 old_crtc_state = drm_atomic_get_old_crtc_state(state, &acrtc->base);
2018-03-15 9138 }
2017-10-12 9139)
2017-08-10 9140 /* Skip any modesets/resets */
2017-10-12 9141) if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state))
2017-08-10 9142 continue;
2017-08-10 9143
2017-10-12 9144) dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2018-11-26 9145 dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
2018-11-26 9146
2019-05-28 9147 scaling_changed = is_scaling_state_different(dm_new_con_state,
2019-05-28 9148 dm_old_con_state);
2019-05-28 9149
2019-05-28 9150 abm_changed = dm_new_crtc_state->abm_level !=
2019-05-28 9151 dm_old_crtc_state->abm_level;
2019-05-28 9152
2019-05-28 9153 hdr_changed =
2021-04-30 9154 !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state);
2019-05-28 9155
2019-05-28 9156 if (!scaling_changed && !abm_changed && !hdr_changed)
2018-11-26 9157 continue;
2017-08-10 9158
2019-09-13 9159 stream_update.stream = dm_new_crtc_state->stream;
2019-05-28 9160 if (scaling_changed) {
2017-10-12 9161) update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode,
2019-09-13 9162 dm_new_con_state, dm_new_crtc_state->stream);
2017-08-10 9163
2018-12-18 9164 stream_update.src = dm_new_crtc_state->stream->src;
2018-12-18 9165 stream_update.dst = dm_new_crtc_state->stream->dst;
2018-12-18 9166 }
2018-12-18 9167
2019-05-28 9168 if (abm_changed) {
2018-12-18 9169 dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level;
2018-12-18 9170
2018-12-18 9171 stream_update.abm_level = &dm_new_crtc_state->abm_level;
2018-12-18 9172 }
2017-11-10 9173
2019-05-28 9174 if (hdr_changed) {
2019-05-28 9175 fill_hdr_info_packet(new_con_state, &hdr_packet);
2019-05-28 9176 stream_update.hdr_static_metadata = &hdr_packet;
2019-05-28 9177 }
2019-05-28 9178
2017-10-12 9179) status = dc_stream_get_status(dm_new_crtc_state->stream);
2021-05-27 9180
2021-05-27 9181 if (WARN_ON(!status))
2021-05-27 9182 continue;
2021-05-27 9183
2017-07-27 9184 WARN_ON(!status->plane_count);
2017-08-10 9185
2018-12-18 9186 /*
2018-12-18 9187 * TODO: DC refuses to perform stream updates without a dc_surface_update.
2018-12-18 9188 * Here we create an empty update on each plane.
2018-12-18 9189 * To fix this, DC should permit updating only stream properties.
2018-12-18 9190 */
2023-06-21 @9191 dummy_updates = kzalloc(sizeof(struct dc_surface_update) * MAX_SURFACES, GFP_ATOMIC);
2018-12-18 9192 for (j = 0; j < status->plane_count; j++)
2021-02-18 9193 dummy_updates[j].surface = status->plane_states[0];
2018-08-21 9194
2018-12-18 9195
2018-12-18 9196 mutex_lock(&dm->dc_lock);
2022-10-06 9197 dc_update_planes_and_stream(dm->dc,
2021-02-18 9198 dummy_updates,
2017-07-27 9199 status->plane_count,
2018-12-18 9200 dm_new_crtc_state->stream,
2022-10-06 9201 &stream_update);
2018-12-18 9202 mutex_unlock(&dm->dc_lock);
2023-06-21 9203 kfree(dummy_updates);
2017-08-10 9204 }
2017-08-10 9205
2022-09-21 9206 /**
2022-09-21 9207 * Enable interrupts for CRTCs that are newly enabled or went through
2022-09-21 9208 * a modeset. It was intentionally deferred until after the front end
2022-09-21 9209 * state was modified to wait until the OTG was on and so the IRQ
2022-09-21 9210 * handlers didn't access stale or invalid state.
2022-09-21 9211 */
2022-09-21 9212 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
2022-09-21 9213 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
2022-09-21 9214 #ifdef CONFIG_DEBUG_FS
2022-09-21 9215 enum amdgpu_dm_pipe_crc_source cur_crc_src;
2022-09-21 9216 #endif
2019-04-08 9217 /* Count number of newly disabled CRTCs for dropping PM refs later. */
2018-06-21 9218 if (old_crtc_state->active && !new_crtc_state->active)
2018-06-21 9219 crtc_disable_count++;
2018-06-21 9220
2017-10-12 9221) dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2017-10-18 9222) dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
2019-03-29 9223
2020-08-12 9224 /* For freesync config update on crtc state and params for irq */
2020-08-12 9225 update_stream_irq_parameters(dm, dm_new_crtc_state);
2019-04-15 9226
2021-02-09 9227 #ifdef CONFIG_DEBUG_FS
2021-04-27 9228 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
2021-04-27 9229 cur_crc_src = acrtc->dm_irq_params.crc_src;
2021-04-27 9230 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
2021-02-09 9231 #endif
2020-08-12 9232
2020-07-13 9233 if (new_crtc_state->active &&
2020-07-13 9234 (!old_crtc_state->active ||
2020-07-13 9235 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
2020-08-12 9236 dc_stream_retain(dm_new_crtc_state->stream);
2020-08-12 9237 acrtc->dm_irq_params.stream = dm_new_crtc_state->stream;
2020-07-13 9238 manage_dm_interrupts(adev, acrtc, true);
2022-09-21 9239 }
2022-09-21 9240 /* Handle vrr on->off / off->on transitions */
2022-09-21 9241 amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
2021-01-07 9242
2021-01-07 9243 #ifdef CONFIG_DEBUG_FS
2022-09-21 9244 if (new_crtc_state->active &&
2022-09-21 9245 (!old_crtc_state->active ||
2022-09-21 9246 drm_atomic_crtc_needs_modeset(new_crtc_state))) {
2020-07-13 9247 /**
2020-07-13 9248 * Frontend may have changed so reapply the CRC capture
2020-07-13 9249 * settings for the stream.
2020-07-13 9250 */
2021-02-09 9251 if (amdgpu_dm_is_valid_crc_source(cur_crc_src)) {
2021-03-02 9252 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
2021-04-27 9253 if (amdgpu_dm_crc_window_is_activated(crtc)) {
2021-04-27 9254 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
2022-10-20 9255 acrtc->dm_irq_params.window_param.update_win = true;
2022-10-19 9256
2022-10-19 9257 /**
2022-10-19 9258 * It takes 2 frames for HW to stably generate CRC when
2022-10-19 9259 * resuming from suspend, so we set skip_frame_cnt 2.
2022-10-19 9260 */
2022-10-20 9261 acrtc->dm_irq_params.window_param.skip_frame_cnt = 2;
2021-04-27 9262 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
2021-04-27 9263 }
2021-03-02 9264 #endif
2021-04-28 9265 if (amdgpu_dm_crtc_configure_crc_source(
2021-04-28 9266 crtc, dm_new_crtc_state, cur_crc_src))
2021-04-28 9267 DRM_DEBUG_DRIVER("Failed to configure crc source");
2022-09-21 9268 }
2020-07-13 9269 }
2022-10-14 9270 #endif
2020-07-13 9271 }
2017-08-10 9272
2019-03-01 9273 for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
2019-09-03 9274 if (new_crtc_state->async_flip)
2019-03-01 9275 wait_for_vblank = false;
2019-03-01 9276
2017-08-10 9277 /* update planes when needed per crtc*/
2017-10-12 9278) for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) {
2017-10-12 9279) dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2017-08-10 9280
2017-10-12 9281) if (dm_new_crtc_state->stream)
2023-06-27 9282 amdgpu_dm_commit_planes(state, dev, dm, crtc, wait_for_vblank);
2017-08-10 9283 }
2017-08-10 9284
2023-12-01 9285 /* Enable writeback */
2023-12-01 9286 for_each_new_connector_in_state(state, connector, new_con_state, i) {
2023-12-01 9287 struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state);
2023-12-01 9288 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc);
2023-12-01 9289
2023-12-01 9290 if (connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK)
2023-12-01 9291 continue;
2023-12-01 9292
2023-12-01 9293 if (!new_con_state->writeback_job)
2023-12-01 9294 continue;
2023-12-01 9295
2023-12-01 @9296 new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base);
2023-12-01 9297
Shanmugam 2024-01-13 9298 if (!new_crtc_state)
Shanmugam 2024-01-13 9299 continue;
Shanmugam 2024-01-13 9300
2023-12-01 9301 if (acrtc->wb_enabled)
2023-12-01 9302 continue;
2023-12-01 9303
2023-12-01 9304 dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
2023-12-01 9305
2023-12-01 9306 dm_set_writeback(dm, dm_new_crtc_state, connector, new_con_state);
2023-12-01 9307 acrtc->wb_enabled = true;
2023-12-01 9308 }
2023-12-01 9309
2019-07-11 9310 /* Update audio instances for each connector. */
2019-07-11 9311 amdgpu_dm_commit_audio(dev, state);
2019-07-11 9312
2020-12-10 9313 /* restore the backlight level */
2021-07-08 9314 for (i = 0; i < dm->num_of_edps; i++) {
2021-07-08 9315 if (dm->backlight_dev[i] &&
2022-03-11 9316 (dm->actual_brightness[i] != dm->brightness[i]))
2021-07-08 9317 amdgpu_dm_backlight_set_level(dm, i, dm->brightness[i]);
2021-07-08 9318 }
2022-06-20 9319
2017-08-10 9320 /*
2017-08-10 9321 * send vblank event on all events not handled in flip and
2017-08-10 9322 * mark consumed event for drm_atomic_helper_commit_hw_done
2017-08-10 9323 */
2020-08-24 9324 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
2017-10-12 9325) for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
2017-08-10 9326
2017-10-12 9327) if (new_crtc_state->event)
2017-10-12 9328) drm_send_event_locked(dev, &new_crtc_state->event->base);
2017-08-10 9329
2017-10-12 9330) new_crtc_state->event = NULL;
2017-08-10 9331 }
2020-08-24 9332 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
2017-08-10 9333
2019-01-07 9334 /* Signal HW programming completion */
2019-01-07 9335 drm_atomic_helper_commit_hw_done(state);
2017-08-10 9336
2017-08-10 9337 if (wait_for_vblank)
2017-11-14 9338 drm_atomic_helper_wait_for_flip_done(dev, state);
2017-08-10 9339
2017-08-10 9340 drm_atomic_helper_cleanup_planes(dev, state);
2018-06-04 9341
2023-06-09 9342 /* Don't free the memory if we are hitting this as part of suspend.
2023-06-09 9343 * This way we don't free any memory during suspend; see
2023-06-09 9344 * amdgpu_bo_free_kernel(). The memory will be freed in the first
2023-06-09 9345 * non-suspend modeset or when the driver is torn down.
2023-06-09 9346 */
2023-06-09 9347 if (!adev->in_suspend) {
2020-12-04 9348 /* return the stolen vga memory back to VRAM */
2020-12-04 9349 if (!adev->mman.keep_stolen_vga_memory)
2020-12-04 9350 amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
2020-12-04 9351 amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
2023-06-09 9352 }
2020-12-04 9353
2018-08-15 9354 /*
2018-08-15 9355 * Finally, drop a runtime PM reference for each newly disabled CRTC,
2018-06-04 9356 * so we can put the GPU into runtime suspend if we're not driving any
2018-06-04 9357 * displays anymore
2018-06-04 9358 */
2018-06-21 9359 for (i = 0; i < crtc_disable_count; i++)
2018-06-04 9360 pm_runtime_put_autosuspend(dev->dev);
2018-06-21 9361 pm_runtime_mark_last_busy(dev->dev);
2017-08-10 9362 }
2017-08-10 9363
line 9191 was first introduced by commit
f8de4324128a6a99afa95 drm/amd/display: Reduce stack size
Siqueira <[email protected]>
<[email protected]>
om/intel/lkp-tests/wiki">https://github.com/intel/lkp-tests/wiki