This series adds CMU_CMGP clock domain to Exynos850 clock driver. In
particular it needs to enable HSI2C (High-Speed I2C) nodes. This series
depends on CMU_APM series [1].
Tested via /sys/kernel/debug/clk/clk_summary:
<<<<<<<<<<<<<<<<<<<<<<<<<<<< cut here >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
enable prepare protect
clock count count count rate
---------------------------------------------------------------------
clk_rco_cmgp 0 0 0 49152000
oscclk 1 1 0 26000000
mout_cmgp_adc 0 0 0 26000000
...
gout_clkcmu_cmgp_bus 1 1 0 399750000
gout_cmgp_usi1_pclk 0 0 0 399750000
gout_cmgp_usi0_pclk 0 0 0 399750000
gout_gpio_cmgp_pclk 0 0 0 399750000
dout_cmgp_adc 0 0 0 28553572
mout_cmgp_usi1 0 0 0 399750000
dout_cmgp_usi1 0 0 0 199875000
gout_cmgp_usi1_ipclk 0 0 0 199875000
mout_cmgp_usi0 0 0 0 399750000
dout_cmgp_usi0 0 0 0 199875000
gout_cmgp_usi0_ipclk 0 0 0 199875000
<<<<<<<<<<<<<<<<<<<<<<<<<<<< cut here >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
[1] https://lkml.org/lkml/2021/10/22/979
Sam Protsenko (2):
dt-bindings: clock: samsung: Document Exynos850 CMU_CMGP
clk: samsung: exynos850: Implement CMU_CMGP domain
.../clock/samsung,exynos850-clock.yaml | 19 ++++
drivers/clk/samsung/clk-exynos850.c | 100 ++++++++++++++++++
include/dt-bindings/clock/exynos850.h | 17 +++
3 files changed, 136 insertions(+)
--
2.30.2
CMU_CMGP generates USI and ADC clocks for BLK_ALIVE. In particular USI
clocks are needed for HSI2C_3 and HSI2C_4 instances.
Signed-off-by: Sam Protsenko <[email protected]>
---
.../clock/samsung,exynos850-clock.yaml | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
index 5618cfa62f80..80ba60838f2b 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
@@ -33,6 +33,7 @@ properties:
enum:
- samsung,exynos850-cmu-top
- samsung,exynos850-cmu-apm
+ - samsung,exynos850-cmu-cmgp
- samsung,exynos850-cmu-core
- samsung,exynos850-cmu-dpu
- samsung,exynos850-cmu-hsi
@@ -87,6 +88,24 @@ allOf:
- const: oscclk
- const: dout_clkcmu_apm_bus
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-cmgp
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_CMGP bus clock (from CMU_APM)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: gout_clkcmu_cmgp_bus
+
- if:
properties:
compatible:
--
2.30.2
CMU_CMGP clock domain provides clocks for CMGP IP-core (Common GPIO).
CMGP module incapsulates next blocks:
- 8 GPIO lines
- 1 GPADC
- 2 USI blocks, each can be configured to provide one of
UART/SPI/HSI2C serial interfaces
Signed-off-by: Sam Protsenko <[email protected]>
---
drivers/clk/samsung/clk-exynos850.c | 100 ++++++++++++++++++++++++++
include/dt-bindings/clock/exynos850.h | 17 +++++
2 files changed, 117 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
index ecffa5c7a081..6965e1b44d24 100644
--- a/drivers/clk/samsung/clk-exynos850.c
+++ b/drivers/clk/samsung/clk-exynos850.c
@@ -492,6 +492,103 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
.clk_name = "dout_clkcmu_apm_bus",
};
+/* ---- CMU_CMGP ------------------------------------------------------------ */
+
+/* Register Offset definitions for CMU_CMGP (0x11c00000) */
+#define CLK_CON_MUX_CLK_CMGP_ADC 0x1000
+#define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0 0x1004
+#define CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1 0x1008
+#define CLK_CON_DIV_DIV_CLK_CMGP_ADC 0x1800
+#define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0 0x1804
+#define CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1 0x1808
+#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c
+#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010
+#define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018
+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044
+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048
+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c
+#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK 0x2050
+
+static const unsigned long cmgp_clk_regs[] __initconst = {
+ CLK_CON_MUX_CLK_CMGP_ADC,
+ CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0,
+ CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1,
+ CLK_CON_DIV_DIV_CLK_CMGP_ADC,
+ CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0,
+ CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1,
+ CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0,
+ CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1,
+ CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK,
+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK,
+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK,
+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK,
+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK,
+};
+
+/* List of parent clocks for Muxes in CMU_CMGP */
+PNAME(mout_cmgp_usi0_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
+PNAME(mout_cmgp_usi1_p) = { "clk_rco_cmgp", "gout_clkcmu_cmgp_bus" };
+PNAME(mout_cmgp_adc_p) = { "oscclk", "dout_cmgp_adc" };
+
+static const struct samsung_fixed_rate_clock cmgp_fixed_clks[] __initconst = {
+ FRATE(CLK_RCO_CMGP, "clk_rco_cmgp", NULL, 0, 49152000),
+};
+
+static const struct samsung_mux_clock cmgp_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_CMGP_ADC, "mout_cmgp_adc", mout_cmgp_adc_p,
+ CLK_CON_MUX_CLK_CMGP_ADC, 0, 1),
+ MUX(CLK_MOUT_CMGP_USI0, "mout_cmgp_usi0", mout_cmgp_usi0_p,
+ CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP0, 0, 1),
+ MUX(CLK_MOUT_CMGP_USI1, "mout_cmgp_usi1", mout_cmgp_usi1_p,
+ CLK_CON_MUX_MUX_CLK_CMGP_USI_CMGP1, 0, 1),
+};
+
+static const struct samsung_div_clock cmgp_div_clks[] __initconst = {
+ DIV(CLK_DOUT_CMGP_ADC, "dout_cmgp_adc", "gout_clkcmu_cmgp_bus",
+ CLK_CON_DIV_DIV_CLK_CMGP_ADC, 0, 4),
+ DIV(CLK_DOUT_CMGP_USI0, "dout_cmgp_usi0", "mout_cmgp_usi0",
+ CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP0, 0, 5),
+ DIV(CLK_DOUT_CMGP_USI1, "dout_cmgp_usi1", "mout_cmgp_usi1",
+ CLK_CON_DIV_DIV_CLK_CMGP_USI_CMGP1, 0, 5),
+};
+
+static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_CMGP_ADC_S0_PCLK, "gout_adc_s0_pclk",
+ "gout_clkcmu_cmgp_bus",
+ CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0, 21, 0, 0),
+ GATE(CLK_GOUT_CMGP_ADC_S1_PCLK, "gout_adc_s1_pclk",
+ "gout_clkcmu_cmgp_bus",
+ CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1, 21, 0, 0),
+ GATE(CLK_GOUT_CMGP_GPIO_PCLK, "gout_gpio_cmgp_pclk",
+ "gout_clkcmu_cmgp_bus",
+ CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_CMGP_USI0_IPCLK, "gout_cmgp_usi0_ipclk", "dout_cmgp_usi0",
+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK, 21, 0, 0),
+ GATE(CLK_GOUT_CMGP_USI0_PCLK, "gout_cmgp_usi0_pclk",
+ "gout_clkcmu_cmgp_bus",
+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_CMGP_USI1_IPCLK, "gout_cmgp_usi1_ipclk", "dout_cmgp_usi1",
+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK, 21, 0, 0),
+ GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk",
+ "gout_clkcmu_cmgp_bus",
+ CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
+};
+
+static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
+ .mux_clks = cmgp_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(cmgp_mux_clks),
+ .div_clks = cmgp_div_clks,
+ .nr_div_clks = ARRAY_SIZE(cmgp_div_clks),
+ .gate_clks = cmgp_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(cmgp_gate_clks),
+ .fixed_clks = cmgp_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(cmgp_fixed_clks),
+ .nr_clk_ids = CMGP_NR_CLK,
+ .clk_regs = cmgp_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(cmgp_clk_regs),
+ .clk_name = "gout_clkcmu_cmgp_bus",
+};
+
/* ---- CMU_HSI ------------------------------------------------------------- */
/* Register Offset definitions for CMU_HSI (0x13400000) */
@@ -956,6 +1053,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = {
{
.compatible = "samsung,exynos850-cmu-apm",
.data = &apm_cmu_info,
+ }, {
+ .compatible = "samsung,exynos850-cmu-cmgp",
+ .data = &cmgp_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-hsi",
.data = &hsi_cmu_info,
diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
index df3978b58304..8aa5e82af0d3 100644
--- a/include/dt-bindings/clock/exynos850.h
+++ b/include/dt-bindings/clock/exynos850.h
@@ -84,6 +84,23 @@
#define CLK_GOUT_SPEEDY_PCLK 21
#define APM_NR_CLK 22
+/* CMU_CMGP */
+#define CLK_RCO_CMGP 1
+#define CLK_MOUT_CMGP_ADC 2
+#define CLK_MOUT_CMGP_USI0 3
+#define CLK_MOUT_CMGP_USI1 4
+#define CLK_DOUT_CMGP_ADC 5
+#define CLK_DOUT_CMGP_USI0 6
+#define CLK_DOUT_CMGP_USI1 7
+#define CLK_GOUT_CMGP_ADC_S0_PCLK 8
+#define CLK_GOUT_CMGP_ADC_S1_PCLK 9
+#define CLK_GOUT_CMGP_GPIO_PCLK 10
+#define CLK_GOUT_CMGP_USI0_IPCLK 11
+#define CLK_GOUT_CMGP_USI0_PCLK 12
+#define CLK_GOUT_CMGP_USI1_IPCLK 13
+#define CLK_GOUT_CMGP_USI1_PCLK 14
+#define CMGP_NR_CLK 15
+
/* CMU_HSI */
#define CLK_MOUT_HSI_BUS_USER 1
#define CLK_MOUT_HSI_MMC_CARD_USER 2
--
2.30.2
On 09/11/2021 17:44, Sam Protsenko wrote:
> CMU_CMGP generates USI and ADC clocks for BLK_ALIVE. In particular USI
> clocks are needed for HSI2C_3 and HSI2C_4 instances.
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> .../clock/samsung,exynos850-clock.yaml | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 09/11/2021 17:44, Sam Protsenko wrote:
> CMU_CMGP clock domain provides clocks for CMGP IP-core (Common GPIO).
> CMGP module incapsulates next blocks:
> - 8 GPIO lines
> - 1 GPADC
> - 2 USI blocks, each can be configured to provide one of
> UART/SPI/HSI2C serial interfaces
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> drivers/clk/samsung/clk-exynos850.c | 100 ++++++++++++++++++++++++++
> include/dt-bindings/clock/exynos850.h | 17 +++++
> 2 files changed, 117 insertions(+)
>
The header might need to be a separate patch, I think it was
preferred... anyway, I am fine with this approach as well:
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Tue, 9 Nov 2021 at 18:44, Sam Protsenko <[email protected]> wrote:
>
> This series adds CMU_CMGP clock domain to Exynos850 clock driver. In
> particular it needs to enable HSI2C (High-Speed I2C) nodes. This series
> depends on CMU_APM series [1].
>
> Tested via /sys/kernel/debug/clk/clk_summary:
>
> <<<<<<<<<<<<<<<<<<<<<<<<<<<< cut here >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
> enable prepare protect
> clock count count count rate
> ---------------------------------------------------------------------
>
> clk_rco_cmgp 0 0 0 49152000
> oscclk 1 1 0 26000000
> mout_cmgp_adc 0 0 0 26000000
> ...
> gout_clkcmu_cmgp_bus 1 1 0 399750000
> gout_cmgp_usi1_pclk 0 0 0 399750000
> gout_cmgp_usi0_pclk 0 0 0 399750000
> gout_gpio_cmgp_pclk 0 0 0 399750000
> dout_cmgp_adc 0 0 0 28553572
> mout_cmgp_usi1 0 0 0 399750000
> dout_cmgp_usi1 0 0 0 199875000
> gout_cmgp_usi1_ipclk 0 0 0 199875000
> mout_cmgp_usi0 0 0 0 399750000
> dout_cmgp_usi0 0 0 0 199875000
> gout_cmgp_usi0_ipclk 0 0 0 199875000
> <<<<<<<<<<<<<<<<<<<<<<<<<<<< cut here >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
>
> [1] https://lkml.org/lkml/2021/10/22/979
>
> Sam Protsenko (2):
> dt-bindings: clock: samsung: Document Exynos850 CMU_CMGP
> clk: samsung: exynos850: Implement CMU_CMGP domain
>
> .../clock/samsung,exynos850-clock.yaml | 19 ++++
> drivers/clk/samsung/clk-exynos850.c | 100 ++++++++++++++++++
> include/dt-bindings/clock/exynos850.h | 17 +++
> 3 files changed, 136 insertions(+)
>
> --
Hi Sylwester,
Can you please review my patches I've submitted recently? Those are:
- [PATCH 1/2] dt-bindings: clock: samsung: Document Exynos850 CMU_APM
- [PATCH 2/2] clk: samsung: exynos850: Implement CMU_APM domain
- [PATCH 1/1] clk: samsung: exynos850: Register clocks early
- [PATCH 0/2] clk: samsung: exynos850: Implement CMU_CMGP
- [PATCH 1/2] dt-bindings: clock: samsung: Document Exynos850 CMU_CMGP
- [PATCH 2/2] clk: samsung: exynos850: Implement CMU_CMGP domain
My further series (like device tree patches for new dev board support)
depend on the status of above patches. So it'd great if those can be
reviewed and applied if it's feasible.
Thanks!
> 2.30.2
>
On Tue, 9 Nov 2021 at 18:44, Sam Protsenko <[email protected]> wrote:
>
> This series adds CMU_CMGP clock domain to Exynos850 clock driver. In
> particular it needs to enable HSI2C (High-Speed I2C) nodes. This series
> depends on CMU_APM series [1].
>
> Tested via /sys/kernel/debug/clk/clk_summary:
>
> <<<<<<<<<<<<<<<<<<<<<<<<<<<< cut here >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
> enable prepare protect
> clock count count count rate
> ---------------------------------------------------------------------
>
> clk_rco_cmgp 0 0 0 49152000
> oscclk 1 1 0 26000000
> mout_cmgp_adc 0 0 0 26000000
> ...
> gout_clkcmu_cmgp_bus 1 1 0 399750000
> gout_cmgp_usi1_pclk 0 0 0 399750000
> gout_cmgp_usi0_pclk 0 0 0 399750000
> gout_gpio_cmgp_pclk 0 0 0 399750000
> dout_cmgp_adc 0 0 0 28553572
> mout_cmgp_usi1 0 0 0 399750000
> dout_cmgp_usi1 0 0 0 199875000
> gout_cmgp_usi1_ipclk 0 0 0 199875000
> mout_cmgp_usi0 0 0 0 399750000
> dout_cmgp_usi0 0 0 0 199875000
> gout_cmgp_usi0_ipclk 0 0 0 199875000
> <<<<<<<<<<<<<<<<<<<<<<<<<<<< cut here >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
>
> [1] https://lkml.org/lkml/2021/10/22/979
>
> Sam Protsenko (2):
> dt-bindings: clock: samsung: Document Exynos850 CMU_CMGP
> clk: samsung: exynos850: Implement CMU_CMGP domain
>
> .../clock/samsung,exynos850-clock.yaml | 19 ++++
> drivers/clk/samsung/clk-exynos850.c | 100 ++++++++++++++++++
> include/dt-bindings/clock/exynos850.h | 17 +++
> 3 files changed, 136 insertions(+)
>
> --
> 2.30.2
>
This patch series is superseded by:
[PATCH 0/6] clk: samsung: exynos850: Clock driver improvements
(going to submit that soon).